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([82.78.167.190]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ceac7c8d87sm1364136a12.76.2024.11.01.02.57.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 02:57:37 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea , Krzysztof Kozlowski Subject: [PATCH v6 1/9] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB Date: Fri, 1 Nov 2024 11:57:12 +0200 Message-Id: <20241101095720.2247815-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> References: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC, the tamper detector and a small general usage memory of 128B. The VBATTB controller controls the clock for the RTC on the Renesas RZ/G3S. The HW block diagram for the clock logic is as follows: +----------+ XC `\ RTXIN --->| |----->| \ +----+ VBATTCLK | 32K clock| | |----->|gate|-----------> | osc | XBYP | | +----+ RTXOUT --->| |----->| / +----------+ ,/ One could connect as input to this HW block either a crystal or an external clock device. This is board specific. After discussions w/ Stephen Boyd the clock tree associated with this hardware block was exported in Linux as: input-xtal xbyp xc mux vbattclk where: - input-xtal is the input clock (connected to RTXIN, RTXOUT pins) - xc, xbyp are mux inputs - mux is the internal mux - vbattclk is the gate clock that feeds in the end the RTC to allow selecting the input of the MUX though assigned-clock DT properties, using the already existing clock drivers and avoid adding other DT properties. This allows select the input of the mux based on the type of the connected input clock: - if the 32768 crystal is connected as input for the VBATTB, the input of the mux should be xc - if an external clock device is connected as input for the VBATTB the input of the mux should be xbyp Add bindings for the VBATTB controller. Reviewed-by: Geert Uytterhoeven Reviewed-by: Krzysztof Kozlowski Signed-off-by: Claudiu Beznea --- Changes in v6: - collected tags Changes in v5: - used spaces in the diagram from the patch description - added "This is board specific" in the board description to emphasize the usage of the assigned-clocks in the example - added default for quartz-load-femtofarads - collected tags Changes in v4: - squashed with patch "Add clock IDs for the VBATTB controller" from v3 - removed "oscillator" word from commit description - added assigned-clocks, assigned-clock-parents to the documentation example - used clock-controller for the node name - used "quartz-load-femtofarads" property for the load capacitance - renamed include/dt-bindings/clock/r9a08g045-vbattb.h to include/dt-bindings/clock/renesas,r9a08g045-vbattb.h Changes in v3: - moved the file to clock dt bindings directory as it is the only functionality supported at the moment; the other functionalities (tamper detector, SRAM) are offered though register spreaded though the address space of the VBATTB IP and not actually individual devices; the other functionalities are not planned to be supported soon and if they will be I think they fit better on auxiliary bus than MFD - dropped interrupt names as requested in the review process - dropped the inner node for clock controller - added #clock-cells - added rtx clock - updated description for renesas,vbattb-load-nanofarads - included dt-bindings/interrupt-controller/irq.h in examples section Changes in v2: - changed file name and compatible - updated title, description sections - added clock controller part documentation and drop dedicated file for it included in v1 - used items to describe interrupts, interrupt-names, clocks, clock-names, resets - dropped node labels and status - updated clock-names for clock controller to cope with the new logic on detecting the necessity to setup bypass .../clock/renesas,r9a08g045-vbattb.yaml | 84 +++++++++++++++++++ .../clock/renesas,r9a08g045-vbattb.h | 13 +++ 2 files changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,r9a08g0= 45-vbattb.yaml create mode 100644 include/dt-bindings/clock/renesas,r9a08g045-vbattb.h diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbat= tb.yaml b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.= yaml new file mode 100644 index 000000000000..3707e4118949 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Battery Backup Function (VBATTB) + +description: + Renesas VBATTB is an always on powered module (backed by battery) which + controls the RTC clock (VBATTCLK), tamper detection logic and a small + general usage memory (128B). + +maintainers: + - Claudiu Beznea + +properties: + compatible: + const: renesas,r9a08g045-vbattb + + reg: + maxItems: 1 + + interrupts: + items: + - description: tamper detector interrupt + + clocks: + items: + - description: VBATTB module clock + - description: RTC input clock (crystal or external clock device) + + clock-names: + items: + - const: bclk + - const: rtx + + '#clock-cells': + const: 1 + + power-domains: + maxItems: 1 + + resets: + items: + - description: VBATTB module reset + + quartz-load-femtofarads: + description: load capacitance of the on board crystal + enum: [ 4000, 7000, 9000, 12500 ] + default: 4000 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - '#clock-cells' + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + clock-controller@1005c000 { + compatible =3D "renesas,r9a08g045-vbattb"; + reg =3D <0x1005c000 0x1000>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; + clock-names =3D "bclk", "rtx"; + assigned-clocks =3D <&vbattb VBATTB_MUX>; + assigned-clock-parents =3D <&vbattb VBATTB_XC>; + #clock-cells =3D <1>; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A08G045_VBAT_BRESETN>; + quartz-load-femtofarads =3D <12500>; + }; diff --git a/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h b/include= /dt-bindings/clock/renesas,r9a08g045-vbattb.h new file mode 100644 index 000000000000..67774eafad06 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ +#define __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ + +#define VBATTB_XC 0 +#define VBATTB_XBYP 1 +#define VBATTB_MUX 2 +#define VBATTB_VBATTCLK 3 + +#endif /* __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ */ --=20 2.39.2 From nobody Sun Nov 24 21:47:21 2024 Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3F2916130B for ; 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([82.78.167.190]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ceac7c8d87sm1364136a12.76.2024.11.01.02.57.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 02:57:40 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v6 2/9] clk: linux/clk-provider.h: Add devm_clk_hw_register_gate_parent_hw() Date: Fri, 1 Nov 2024 11:57:13 +0200 Message-Id: <20241101095720.2247815-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> References: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add devm_clk_hw_register_gate_parent_hw() macro to allow registering devres managed gate clocks providing struct clk_hw object as parent. Reviewed-by: Geert Uytterhoeven Acked-by: Stephen Boyd Signed-off-by: Claudiu Beznea --- Changes in v6: - collected tags Changes in v5: - none Changes in v4: - collected tags Changes in v3: - none; this patch is new include/linux/clk-provider.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 75444e250a78..a49859ef3304 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -622,6 +622,24 @@ struct clk *clk_register_gate(struct device *dev, cons= t char *name, __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ NULL, (flags), (reg), (bit_idx), \ (clk_gate_flags), (lock)) +/** + * devm_clk_hw_register_gate_parent_hw - register a gate clock with the cl= ock + * framework + * @dev: device that is registering this clock + * @name: name of this clock + * @parent_hw: pointer to parent clk + * @flags: framework-specific flags for this clock + * @reg: register address to control gating of this clock + * @bit_idx: which bit in the register controls gating of this clock + * @clk_gate_flags: gate-specific flags for this clock + * @lock: shared register lock for this clock + */ +#define devm_clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, = \ + reg, bit_idx, clk_gate_flags, \ + lock) \ + __devm_clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \ + NULL, (flags), (reg), (bit_idx), \ + (clk_gate_flags), (lock)) /** * devm_clk_hw_register_gate_parent_data - register a gate clock with the * clock framework --=20 2.39.2 From nobody Sun Nov 24 21:47:21 2024 Received: from mail-ed1-f45.google.com (mail-ed1-f45.google.com [209.85.208.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8D6A15C158 for ; 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([82.78.167.190]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ceac7c8d87sm1364136a12.76.2024.11.01.02.57.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 02:57:43 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v6 3/9] clk: renesas: clk-vbattb: Add VBATTB clock driver Date: Fri, 1 Nov 2024 11:57:14 +0200 Message-Id: <20241101095720.2247815-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> References: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used by the RTC. The input to the VBATTB could be a 32KHz crystal or an external clock device. The HW block diagram for the clock generator is as follows: +----------+ XC `\ RTXIN --->| |----->| \ +----+ VBATTCLK | 32K clock| | |----->|gate|-----------> | osc | XBYP | | +----+ RTXOUT --->| |----->| / +----------+ , After discussions w/ Stephen Boyd the clock tree associated with this hardware block was exported in Linux as: vbattb-xtal xbyp xc mux vbattbclk where: - input-xtal is the input clock (connected to RTXIN, RTXOUT pins) - xc, xbyp are mux inputs - mux is the internal mux - vbattclk is the gate clock that feeds in the end the RTC to allow selecting the input of the MUX though assigned-clock DT properties, using the already existing clock drivers and avoid adding other DT properties. If the crystal is connected on RTXIN, RTXOUT pins the XC will be selected as mux input. If an external clock device is connected on RTXIN, RTXOUT pins the XBYP will be selected as mux input. The load capacitance of the internal crystal can be configured with renesas,vbattb-load-nanofarads DT property. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v6: - used tristate - added depends ARCH_RENESAS || COMPILE_TEST Changes in v5: - collected tags Changes in v4: - dropped oscillator from patch description - s/on-board/internal in patch description - updated dt-binding included file name in the driver as it has been renamed to include/dt-bindings/clock/renesas,r9a08g045-vbattb.h - dropped the "_BIT" from driver macros - used "quartz-load-femtofarads" dt property instead of adding a new one - register the "vbattclk" as critical clock as this feeds the RTC counter logic and it needs to stay on from the moment the RTC is configured; along with it, added a comment to express this. Changes in v3: - updated patch description - dropped dependency on MFD_RENESAS_VBATTB as now there is no driver built under this flag - dropped include/clk.h - added pm_runtime and reset control support - updated register offsets - registered 4 clocks: xc, xbyp, mux, vbattclk using generic clock drivers - added MODULE_DEVICE_TABLE() Changes in v2: - updated patch description - added vendor name in Kconfig flag - used cleanup.h lock helpers - dropped the MFD code - updated registers offsets - added vbattb_clk_update_bits() and used it where possible - added vbattb_clk_need_bypass() to detect the bypass setup necessity - changed the compatible and driver names drivers/clk/renesas/Kconfig | 5 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/clk-vbattb.c | 205 +++++++++++++++++++++++++++++++ 3 files changed, 211 insertions(+) create mode 100644 drivers/clk/renesas/clk-vbattb.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 76791a1c50ac..ff01f5f0ed20 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -237,6 +237,11 @@ config CLK_RZV2H bool "RZ/V2H(P) family clock support" if COMPILE_TEST select RESET_CONTROLLER =20 +config CLK_RENESAS_VBATTB + tristate "Renesas VBATTB clock controller" + depends on ARCH_RZG2L || COMPILE_TEST + select RESET_CONTROLLER + # Generic config CLK_RENESAS_CPG_MSSR bool "CPG/MSSR clock support" if COMPILE_TEST diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 23d2e26051c8..82efaa835ac7 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -53,3 +53,4 @@ obj-$(CONFIG_CLK_RZV2H) +=3D rzv2h-cpg.o obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) +=3D renesas-cpg-mssr.o obj-$(CONFIG_CLK_RENESAS_CPG_MSTP) +=3D clk-mstp.o obj-$(CONFIG_CLK_RENESAS_DIV6) +=3D clk-div6.o +obj-$(CONFIG_CLK_RENESAS_VBATTB) +=3D clk-vbattb.o diff --git a/drivers/clk/renesas/clk-vbattb.c b/drivers/clk/renesas/clk-vba= ttb.c new file mode 100644 index 000000000000..ff9d1ead455c --- /dev/null +++ b/drivers/clk/renesas/clk-vbattb.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * VBATTB clock driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define VBATTB_BKSCCR 0x1c +#define VBATTB_BKSCCR_SOSEL 6 +#define VBATTB_SOSCCR2 0x24 +#define VBATTB_SOSCCR2_SOSTP2 0 +#define VBATTB_XOSCCR 0x30 +#define VBATTB_XOSCCR_OUTEN 16 +#define VBATTB_XOSCCR_XSEL GENMASK(1, 0) +#define VBATTB_XOSCCR_XSEL_4_PF 0x0 +#define VBATTB_XOSCCR_XSEL_7_PF 0x1 +#define VBATTB_XOSCCR_XSEL_9_PF 0x2 +#define VBATTB_XOSCCR_XSEL_12_5_PF 0x3 + +/** + * struct vbattb_clk - VBATTB clock data structure + * @base: base address + * @lock: lock + */ +struct vbattb_clk { + void __iomem *base; + spinlock_t lock; +}; + +static int vbattb_clk_validate_load_capacitance(u32 *reg_lc, u32 of_lc) +{ + switch (of_lc) { + case 4000: + *reg_lc =3D VBATTB_XOSCCR_XSEL_4_PF; + break; + case 7000: + *reg_lc =3D VBATTB_XOSCCR_XSEL_7_PF; + break; + case 9000: + *reg_lc =3D VBATTB_XOSCCR_XSEL_9_PF; + break; + case 12500: + *reg_lc =3D VBATTB_XOSCCR_XSEL_12_5_PF; + break; + default: + return -EINVAL; + } + + return 0; +} + +static void vbattb_clk_action(void *data) +{ + struct device *dev =3D data; + struct reset_control *rstc =3D dev_get_drvdata(dev); + int ret; + + ret =3D reset_control_assert(rstc); + if (ret) + dev_err(dev, "Failed to de-assert reset!"); + + ret =3D pm_runtime_put_sync(dev); + if (ret < 0) + dev_err(dev, "Failed to runtime suspend!"); + + of_clk_del_provider(dev->of_node); +} + +static int vbattb_clk_probe(struct platform_device *pdev) +{ + struct device_node *np =3D pdev->dev.of_node; + struct clk_parent_data parent_data =3D {}; + struct clk_hw_onecell_data *clk_data; + const struct clk_hw *parent_hws[2]; + struct device *dev =3D &pdev->dev; + struct reset_control *rstc; + struct vbattb_clk *vbclk; + u32 of_lc, reg_lc; + struct clk_hw *hw; + /* 4 clocks are exported: VBATTB_XC, VBATTB_XBYP, VBATTB_MUX, VBATTB_VBAT= TCLK. */ + u8 num_clks =3D 4; + int ret; + + /* Default to 4pF as this is not needed if external clock device is conne= cted. */ + of_lc =3D 4000; + of_property_read_u32(np, "quartz-load-femtofarads", &of_lc); + + ret =3D vbattb_clk_validate_load_capacitance(®_lc, of_lc); + if (ret) + return ret; + + vbclk =3D devm_kzalloc(dev, sizeof(*vbclk), GFP_KERNEL); + if (!vbclk) + return -ENOMEM; + + clk_data =3D devm_kzalloc(dev, struct_size(clk_data, hws, num_clks), GFP_= KERNEL); + if (!clk_data) + return -ENOMEM; + clk_data->num =3D num_clks; + + vbclk->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(vbclk->base)) + return PTR_ERR(vbclk->base); + + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return ret; + + rstc =3D devm_reset_control_get_shared(dev, NULL); + if (IS_ERR(rstc)) + return PTR_ERR(rstc); + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + ret =3D reset_control_deassert(rstc); + if (ret) { + pm_runtime_put_sync(dev); + return ret; + } + + dev_set_drvdata(dev, rstc); + ret =3D devm_add_action_or_reset(dev, vbattb_clk_action, dev); + if (ret) + return ret; + + spin_lock_init(&vbclk->lock); + + parent_data.fw_name =3D "rtx"; + hw =3D devm_clk_hw_register_gate_parent_data(dev, "xc", &parent_data, 0, + vbclk->base + VBATTB_SOSCCR2, + VBATTB_SOSCCR2_SOSTP2, + CLK_GATE_SET_TO_DISABLE, &vbclk->lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_XC] =3D hw; + + hw =3D devm_clk_hw_register_fixed_factor_fwname(dev, np, "xbyp", "rtx", 0= , 1, 1); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_XBYP] =3D hw; + + parent_hws[0] =3D clk_data->hws[VBATTB_XC]; + parent_hws[1] =3D clk_data->hws[VBATTB_XBYP]; + hw =3D devm_clk_hw_register_mux_parent_hws(dev, "mux", parent_hws, 2, 0, + vbclk->base + VBATTB_BKSCCR, + VBATTB_BKSCCR_SOSEL, + 1, 0, &vbclk->lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_MUX] =3D hw; + + /* Set load capacitance before registering the VBATTCLK clock. */ + scoped_guard(spinlock, &vbclk->lock) { + u32 val =3D readl_relaxed(vbclk->base + VBATTB_XOSCCR); + + val &=3D ~VBATTB_XOSCCR_XSEL; + val |=3D reg_lc; + writel_relaxed(val, vbclk->base + VBATTB_XOSCCR); + } + + /* This feeds the RTC counter clock and it needs to stay on. */ + hw =3D devm_clk_hw_register_gate_parent_hw(dev, "vbattclk", hw, CLK_IS_CR= ITICAL, + vbclk->base + VBATTB_XOSCCR, + VBATTB_XOSCCR_OUTEN, 0, + &vbclk->lock); + + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_VBATTCLK] =3D hw; + + return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); +} + +static const struct of_device_id vbattb_clk_match[] =3D { + { .compatible =3D "renesas,r9a08g045-vbattb" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, vbattb_clk_match); + +static struct platform_driver vbattb_clk_driver =3D { + .driver =3D { + .name =3D "renesas-vbattb-clk", + .of_match_table =3D vbattb_clk_match, + }, + .probe =3D vbattb_clk_probe, +}; +module_platform_driver(vbattb_clk_driver); + +MODULE_DESCRIPTION("Renesas VBATTB Clock Driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); --=20 2.39.2 From nobody Sun Nov 24 21:47:21 2024 Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 509DD198E69 for ; Fri, 1 Nov 2024 09:57:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455070; cv=none; b=lcHn219dikbmC+APyizPWWsi0Mjvnn9PTnsvD221/s+9AjXcReZnTewf6FeihLlzhP6/WwhpRP9YdFW0mmEqa38eph7dh1PMKjbYi+yS4liMKcQSicEtgdmY6tRWkotTQgQd6bHa+YErehJVl+Kjeigy5UHDc++IjmWbJF7yexw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455070; c=relaxed/simple; bh=TpRf+IPzzflEYM2PIdEujWQYh9I90S6kiE0QI6bogDE=; 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([82.78.167.190]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ceac7c8d87sm1364136a12.76.2024.11.01.02.57.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 02:57:45 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v6 4/9] rtc: renesas-rtca3: Fix compilation error on RISC-V Date: Fri, 1 Nov 2024 11:57:15 +0200 Message-Id: <20241101095720.2247815-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> References: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Fix the following compilation errors when building the RTCA3 for RISCV: ../drivers/rtc/rtc-renesas-rtca3.c:270:23: error: call to undeclared functi= on 'FIELD_GET'; ISO C99 and later do not support implicit function declarat= ions [-Wimplicit-function-declaration] 270 | tm->tm_sec =3D bcd2bin(FIELD_GET(RTCA3_RSECCNT_SEC, sec)); | ^ ../drivers/rtc/rtc-renesas-rtca3.c:369:23: error: call to undeclared functi= on 'FIELD_GET'; ISO C99 and later do not support implicit function declarat= ions [-Wimplicit-function-declaration] 369 | tm->tm_sec =3D bcd2bin(FIELD_GET(RTCA3_RSECAR_SEC, sec)); | ^ ../drivers/rtc/rtc-renesas-rtca3.c:476:11: error: call to undeclared functi= on 'FIELD_GET'; ISO C99 and later do not support implicit function declarat= ions [-Wimplicit-function-declaration] 476 | cycles =3D FIELD_GET(RTCA3_RADJ_ADJ, radj); | ^ ../drivers/rtc/rtc-renesas-rtca3.c:523:9: error: call to undeclared functio= n 'FIELD_PREP'; ISO C99 and later do not support implicit function declarat= ions [-Wimplicit-function-declaration] 523 | radj =3D FIELD_PREP(RTCA3_RADJ_ADJ, abs(cycles)); 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([82.78.167.190]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ceac7c8d87sm1364136a12.76.2024.11.01.02.57.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 02:57:47 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v6 5/9] arm64: dts: renesas: r9a08g045: Add VBATTB node Date: Fri, 1 Nov 2024 11:57:16 +0200 Message-Id: <20241101095720.2247815-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> References: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add the DT node for the VBATTB IP along with DT bindings for the clock it provides. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v6: - none Changes in v5: - dropped the status =3D "disabled"; for the vbattb-xtal node Changes in v4: - used clock-controller for the vbattb node name - move the node near scif0 for ordering - set the vbattb_xtal status as disabled to avoid having it exported in linux with frequency =3D 0 in boards that don't use it - collected tags Changes in v3: - dropped the child nodes of vbattb; along with this dropped ranges, interrupt-names, #address-cells, #size-cells - added vbattb_xtal as input clock for vbattb Changes in v2: - update compatibles - updated clocks and clock-names for clock-controller node - removed the power domain from the clock-controller as this is controlled by parent node in v2 =20 =20 arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g045.dtsi index 067a26a66c24..a1d5084b074a 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -72,6 +72,18 @@ scif0: serial@1004b800 { status =3D "disabled"; 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([82.78.167.190]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ceac7c8d87sm1364136a12.76.2024.11.01.02.57.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 02:57:50 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v6 6/9] arm64: dts: renesas: r9a08g045: Add RTC node Date: Fri, 1 Nov 2024 11:57:17 +0200 Message-Id: <20241101095720.2247815-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> References: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add the DT node for the RTC IP available on the Renesas RZ/G3S SoC. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v6: - none Changes in v5: - collected tags Changes in v4: - dropped the assigned-clocks, assigned-clock-parents properties as they fit better on vbattb node - moved the RTC close to serial node for ordering Changes in v3: - added CPG clock, power domain, reset - and assigned-clocks, assigned-clock-parents to configure the VBATTCLK - included dt-bindings/clock/r9a08g045-vbattb.h Changes in v2: - updated compatibles arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g045.dtsi index a1d5084b074a..be8a0a768c65 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -7,6 +7,7 @@ =20 #include #include +#include =20 / { compatible =3D "renesas,r9a08g045"; @@ -72,6 +73,20 @@ scif0: serial@1004b800 { status =3D "disabled"; }; =20 + rtc: rtc@1004ec00 { + compatible =3D "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; 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([82.78.167.190]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ceac7c8d87sm1364136a12.76.2024.11.01.02.57.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 02:57:52 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v6 7/9] arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB Date: Fri, 1 Nov 2024 11:57:18 +0200 Message-Id: <20241101095720.2247815-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> References: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Enable the VBATTB controller. It provides the clock for RTC. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v6: - none Changes in v5: - dropped the status =3D "okay"; from vbattb_xtal node Changes in v4: - added assigned-clocks, assigned-clock-parents properties - set vbattb_xtal status =3D "okay" - collected tags Changes in v3: - updated patch description - dropped vbattclk - added renesas,vbattb-load-nanofarads on vbattb - moved vbattb before vbattb_xtal Changes in v2: - none arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3s-smarc-som.dtsi index 71424e69939e..30bb4f5a7dfd 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2023 Renesas Electronics Corp. */ =20 +#include #include #include =20 @@ -344,6 +345,17 @@ mux { }; }; =20 +&vbattb { + assigned-clocks =3D <&vbattb VBATTB_MUX>; + assigned-clock-parents =3D <&vbattb VBATTB_XC>; + quartz-load-femtofarads =3D <12500>; + status =3D "okay"; +}; + +&vbattb_xtal { + clock-frequency =3D <32768>; +}; + &wdt0 { timeout-sec =3D <60>; status =3D "okay"; --=20 2.39.2 From nobody Sun Nov 24 21:47:21 2024 Received: from mail-ed1-f42.google.com (mail-ed1-f42.google.com [209.85.208.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B47ED19CD1B for ; Fri, 1 Nov 2024 09:57:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455079; cv=none; b=IFOQ/8mhXczCSgkMYfdOS861zR6aE6xHoqfwWw25CWXQQZHpZh3eKm+f5fBYRlT7E2z7z7MZT/hcngu3KN+CCj6xU922/eaKm/MHZKdGRrU3OiSCN+ALH6XCWFFyWWPw2WeYTseBU+a4z8IAzQ3Ju2jVxRZsi+moy9zQFc+AVJw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455079; c=relaxed/simple; bh=Pf9k322Noul/AUoZF1lcvPKEcxZYOYxw5S5eT2YDnXg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=M/UrndwWq38c+9rHtKFhBUGaiWFx9T4i4VHwa/5mlfYKGz+kxVmB55eUz5DfMsHR/06NLINbQ+ke2081/XMTyMhYwNQzppAZhWFUfzmu8BkEVD/izjX10DP+SFFKHHdtaYYf0XoNVQ9UcEP1ePu1mGo8aqrHmnlvZMGcVeSICPg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=DfXQFLSs; arc=none smtp.client-ip=209.85.208.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="DfXQFLSs" Received: by mail-ed1-f42.google.com with SMTP id 4fb4d7f45d1cf-5c9709c9b0cso2666260a12.1 for ; Fri, 01 Nov 2024 02:57:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1730455076; x=1731059876; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CsdPZF9emf18XQgtgS7Xp71XPblYsQ7NBPKTENRn3uQ=; b=DfXQFLSsrbMNA5VOknfWfhySdFrCjvu0tDgwrTEWF1sUtGqbT8H2o/gCGINS0nfl7j nouq6LwZH23a9x2wml4xQCO7kR5XuND8zx1qG4+OwTqPart8LGYYvU///slPG0xfhNRz 3iGfjI65SIjGdrP6opiRuR27K2hWE3QtrLCR6ZdSmbeKwAVCGhYio8n4rqw9VdZCHmJc SbCp6ML4isJAZ4q0w80/ROUfyOvxpRSM+mZwYUVUxnWEf2Za4rbFiVXnZO/X2SiJmFRV lKCrJsV+lA9gi1SEv1bh8fr+HWB1HJOU5aSTYsUeATkfWePam0hr28Fg989jaizKmSfM WDyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730455076; x=1731059876; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CsdPZF9emf18XQgtgS7Xp71XPblYsQ7NBPKTENRn3uQ=; b=CLGBe6z4aq0o9/e4W51Q8zCO1msozJWSQxt6MeaceoDkdpxHdHrn/jcawHeqHJfsEw DtbmTuJMJr4PgSWMgRKsbsOjak5l8W75JOYy0qyNdvaFllVXRaxMYLaSU9g27oCMctvH SfhFUGhn+ts5os91/NjhsAvHE4kkt+WCl4PJK146a8T09AraaELHVIMXojrowjhGuGnn 7X6YHyGpI4MQDdKGMhEQuGsCm2PgSAi6d9Vae7PtGWybAtEkiRlahzqvIxb8Y4RLClsH BuFCNQeaj+ibhA3anvwPqu/W1yS3vPtmLTLStqE7GCGXd8iarYWYmHRSw8j4UZp3D754 KfDA== X-Forwarded-Encrypted: i=1; AJvYcCWrWOsNUCP+2WJ7VtBnOT3MXXBzz3Z/fMThmlUbj4Ulky24g2NRARnAyYiBgyYmAXcuB/vpVORJz8M/L0A=@vger.kernel.org X-Gm-Message-State: AOJu0Ywxb2FkNpHevLd2kM3yaxk3dnh0cCX5CNroHbaPsdEtMO+HDY4W vqzCypCMOLwbHKeBUM0dZUXtLaOWymi64kr9Cng0d2zB/fuTyEuJxAOYTXJKuIM= X-Google-Smtp-Source: AGHT+IHIInFyvvZ21N4w9XKZUzECowUn+aG9F5+oWwykmTnOmG6gYMfAOXIH3hB+PUh/16T6BdSrwQ== X-Received: by 2002:a05:6402:518a:b0:5c9:76ca:705b with SMTP id 4fb4d7f45d1cf-5cd54afde73mr7392400a12.34.1730455075953; Fri, 01 Nov 2024 02:57:55 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.190]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ceac7c8d87sm1364136a12.76.2024.11.01.02.57.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 02:57:54 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v6 8/9] arm64: dts: renesas: rzg3s-smarc-som: Enable RTC Date: Fri, 1 Nov 2024 11:57:19 +0200 Message-Id: <20241101095720.2247815-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> References: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Enable RTC. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v6: - none Changes in v5: - none Changes in v4: - collected tags Changes in v3: - none Changes in v2: - none arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3s-smarc-som.dtsi index 30bb4f5a7dfd..2ed01d391554 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -345,6 +345,10 @@ mux { }; }; =20 +&rtc { + status =3D "okay"; +}; + &vbattb { assigned-clocks =3D <&vbattb VBATTB_MUX>; assigned-clock-parents =3D <&vbattb VBATTB_XC>; --=20 2.39.2 From nobody Sun Nov 24 21:47:21 2024 Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7284019F117 for ; Fri, 1 Nov 2024 09:58:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455082; cv=none; b=ePJQWuDRTc9qFSwZuf4pclvZI/8i+xk1mqKVi0dUPlIg6lM4+zAS6JFX2azJqonrA14GPNylVJlPkSCxKYo2utEoRTwp/2lP/N4gW5QNzBl/+g3IA07mQgFP8mWIB/a60ZG04EsijiKYqsupohzn4ftMx36VvUaXQm7e6nrQUjY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455082; c=relaxed/simple; bh=5q3sZ67C/C9aXpvq5Ph2rdpLI36199ziQrN6XfaKdN8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=AvSyBiV0JfI2P4QCYoe1n34h5Myk5aTBDEAdY0FErFe1S8L+VEJIMYwqqzzZJRnvvLH2+fpEUgyTF60yUTWSOdlOxdztqVP2/+SOtd7S54mYKOZtnByFTEMf25E+554AxoaY+5eR246omoLx6WHQi7T/99WepAX8lDJv6jVRV2c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=rCrJOyjE; arc=none smtp.client-ip=209.85.208.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="rCrJOyjE" Received: by mail-ed1-f44.google.com with SMTP id 4fb4d7f45d1cf-5cb6ca2a776so2542455a12.0 for ; Fri, 01 Nov 2024 02:58:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1730455079; x=1731059879; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uDVeB7Y+VIp/FplukcEJ+LJ4Vz9niC4RyWfPRl3XIfk=; b=rCrJOyjEbqtAfGFSmF9fitisxGo6N/aRbGgwTYNNlDFTUVgrFwiO+alJUk5H/vdHTT ADRy0YSjkVKM5qnrf4cULKAzriMFJlEiPQ7i5oulnl7meAjB0/Astm4gms3dMMi9dQnE ygqQ+HDq/YfLeSgj7sfW5TbOAUMhoGiPurgD2px1kMBInsyFE7qkoQs/yNCNiO/FVdpK 8K+bwlrA/I9xyeany5P9TJSqC0OyyrqOoCU6uq9ipyX8ex+O0o4/LrSxfMMlxA51SBxp ZtOzksRmPQZLtLEEqhXsdKAbBtszq/9ju79/9Aw7IAIivTyzv2XAD3JPM90NVLl/dZvc OQXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730455079; x=1731059879; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uDVeB7Y+VIp/FplukcEJ+LJ4Vz9niC4RyWfPRl3XIfk=; b=vPodRBCxqzw3HOQCTEVWSMMUToza0nmJ8qB+4LLMmSE6gDtoh5v8N2cH5e5LwT1g+B 6FFZED9sz0bV4Rj5YcUvpJKserZj8cB1DSUYkgfR7P9bMGFX7v6Qrqz9RymeOe2FabLo +vRY77tFfjrac704HwWE1ZOOTM5SK/RfVU4dhZyUxgz+g2oQcX3Acj5eKNmqCeF9E4cz M1+vWy2YMtEJ1ZbgTPDOWTdFIoLYcNlZ0dQZtohkhLc2TudH67egjEOYBQy8V1suUybH qWBaHKmuqLBpIl89HBa3qAhjdMx0k8A7DHcsJBjwtf3KhE0Nmpa73MyOIe97bJBGfAOs 3tNw== X-Forwarded-Encrypted: i=1; AJvYcCUPuMiW2Q/NKLmxUTq9kyE4bprMsmyRWMjJa7uecIpQVmYtVrr5zJ+bzF9NAoq+fgCC6dzfxDSQk4EwS2o=@vger.kernel.org X-Gm-Message-State: AOJu0YyVt6Ev2Qlysu7JrS6qr4uxRxnYxvRK8IPLBb+MNCmSQ01AaLoQ SJkTRjv/3fQWk17SaUCmTGyLT+rKz6drtNSVPMv1uSsXbcGcMGBNCzFYMgCr9YA= X-Google-Smtp-Source: AGHT+IFm5mOqj3B/Gyi2brvekA2DF+HNO4SlxfDE0BQcyiDTfbNWcuu/umQTldMEOxZlW5iJz8fSBQ== X-Received: by 2002:a05:6402:3585:b0:5ce:bb37:c2e1 with SMTP id 4fb4d7f45d1cf-5cebb37c36emr1662850a12.19.1730455078849; Fri, 01 Nov 2024 02:57:58 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.190]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ceac7c8d87sm1364136a12.76.2024.11.01.02.57.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 02:57:57 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v6 9/9] arm64: defconfig: Enable VBATTB clock and Renesas RTCA-3 flags Date: Fri, 1 Nov 2024 11:57:20 +0200 Message-Id: <20241101095720.2247815-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> References: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Enable the Renesas VBATTB clock and RTCA-3 RTC drivers. These are available on the Renesas RZ/G3S SoC. VBATTB is the clock provider for the RTC counter. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v6: - enabled as modules - Geert: I kept your tag, let me know if you consider otherwise Changes in v5: - none Changes in v4: - squashed w/ patch "arm64: defconfig: Enable Renesas RTCA-3 flag" from v3 - updated patch description - collected tags Changes in v3: - update patch title and description - dropped CONFIG_MFD_RENESAS_VBATTB Changes in v2: - added CONFIG_MFD_RENESAS_VBATTB - added vendor name in the VBATTB clock flag arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 0fad83642034..c62831e61586 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1222,6 +1222,7 @@ CONFIG_RTC_DRV_IMX_SC=3Dm CONFIG_RTC_DRV_MT6397=3Dm CONFIG_RTC_DRV_XGENE=3Dy CONFIG_RTC_DRV_TI_K3=3Dm +CONFIG_RTC_DRV_RENESAS_RTCA3=3Dm CONFIG_DMADEVICES=3Dy CONFIG_DMA_BCM2835=3Dy CONFIG_DMA_SUN6I=3Dm @@ -1371,6 +1372,7 @@ CONFIG_SM_VIDEOCC_8250=3Dy CONFIG_QCOM_HFPLL=3Dy CONFIG_CLK_GFM_LPASS_SM8250=3Dm CONFIG_CLK_RCAR_USB2_CLOCK_SEL=3Dy +CONFIG_CLK_RENESAS_VBATTB=3Dm CONFIG_HWSPINLOCK=3Dy CONFIG_HWSPINLOCK_QCOM=3Dy CONFIG_TEGRA186_TIMER=3Dy --=20 2.39.2