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charset="utf-8" Add "ref" clock to enable reference clock. To avoid the DT compatibility, i.MX95 REF clock might be optional. Replace the devm_clk_bulk_get() by devm_clk_bulk_get_optional() to fetch i.MX95 PCIe optional clocks in driver. If use external clock, ref clock should point to external reference. If use internal clock, CREF_EN in LAST_TO_REG controls reference output, which implement in drivers/clk/imx/clk-imx95-blk-ctl.c. Signed-off-by: Richard Zhu Reviewed-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 808d1f105417..bc8567677a67 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -82,6 +82,7 @@ enum imx_pcie_variants { #define IMX_PCIE_FLAG_HAS_SERDES BIT(6) #define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7) #define IMX_PCIE_FLAG_CPU_ADDR_FIXUP BIT(8) +#define IMX_PCIE_FLAG_CUSTOM_PME_TURNOFF BIT(9) =20 #define imx_check_flag(pci, val) (pci->drvdata->flags & val) =20 @@ -98,6 +99,7 @@ struct imx_pcie_drvdata { const char *gpr; const char * const *clk_names; const u32 clks_cnt; + const u32 clks_optional_cnt; const u32 ltssm_off; const u32 ltssm_mask; const u32 mode_off[IMX_PCIE_MAX_INSTANCES]; @@ -1278,9 +1280,8 @@ static int imx_pcie_probe(struct platform_device *pde= v) struct device_node *np; struct resource *dbi_base; struct device_node *node =3D dev->of_node; - int ret; + int ret, i, req_cnt; u16 val; - int i; =20 imx_pcie =3D devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL); if (!imx_pcie) @@ -1330,7 +1331,10 @@ static int imx_pcie_probe(struct platform_device *pd= ev) imx_pcie->clks[i].id =3D imx_pcie->drvdata->clk_names[i]; =20 /* Fetch clocks */ - ret =3D devm_clk_bulk_get(dev, imx_pcie->drvdata->clks_cnt, imx_pcie->clk= s); + req_cnt =3D imx_pcie->drvdata->clks_cnt - imx_pcie->drvdata->clks_optiona= l_cnt; + ret =3D devm_clk_bulk_get(dev, req_cnt, imx_pcie->clks); + ret |=3D devm_clk_bulk_get_optional(dev, imx_pcie->drvdata->clks_optional= _cnt, + imx_pcie->clks + req_cnt); if (ret) return ret; =20 @@ -1480,6 +1484,7 @@ static const char * const imx8mm_clks[] =3D {"pcie_bu= s", "pcie", "pcie_aux"}; static const char * const imx8mq_clks[] =3D {"pcie_bus", "pcie", "pcie_phy= ", "pcie_aux"}; static const char * const imx6sx_clks[] =3D {"pcie_bus", "pcie", "pcie_phy= ", "pcie_inbound_axi"}; static const char * const imx8q_clks[] =3D {"mstr", "slv", "dbi"}; +static const char * const imx95_clks[] =3D {"pcie_bus", "pcie", "pcie_phy"= , "pcie_aux", "ref"}; =20 static const struct imx_pcie_drvdata drvdata[] =3D { [IMX6Q] =3D { @@ -1592,9 +1597,11 @@ static const struct imx_pcie_drvdata drvdata[] =3D { }, [IMX95] =3D { .variant =3D IMX95, - .flags =3D IMX_PCIE_FLAG_HAS_SERDES, - .clk_names =3D imx8mq_clks, - .clks_cnt =3D ARRAY_SIZE(imx8mq_clks), + .flags =3D IMX_PCIE_FLAG_HAS_SERDES | + IMX_PCIE_FLAG_SUPPORTS_SUSPEND, + .clk_names =3D imx95_clks, + .clks_cnt =3D ARRAY_SIZE(imx95_clks), + .clks_optional_cnt =3D 1, .ltssm_off =3D IMX95_PE0_GEN_CTRL_3, .ltssm_mask =3D IMX95_PCIE_LTSSM_EN, .mode_off[0] =3D IMX95_PE0_GEN_CTRL_1, --=20 2.37.1