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charset="utf-8" Previous reference clock of i.MX95 PCIe RC is on when system boot to kernel. But boot firmware change the behavor, it is off when boot. So it needs be turn on when it is used. Also it needs be turn off/on when suspend and resume. Add one ref clock for i.MX95 PCIe RC. Increase clocks' maxItems to 5 and keep the same restriction with other compatible string. Signed-off-by: Richard Zhu Reviewed-by: Krzysztof Kozlowski --- .../bindings/pci/fsl,imx6q-pcie-common.yaml | 4 +-- .../bindings/pci/fsl,imx6q-pcie-ep.yaml | 1 + .../bindings/pci/fsl,imx6q-pcie.yaml | 25 ++++++++++++++++--- 3 files changed, 24 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.ya= ml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml index a8b34f58f8f4..cddbe21f99f2 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml @@ -17,11 +17,11 @@ description: properties: clocks: minItems: 3 - maxItems: 4 + maxItems: 5 =20 clock-names: minItems: 3 - maxItems: 4 + maxItems: 5 =20 num-lanes: const: 1 diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b= /Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml index 84ca12e8b25b..f41f704c6729 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml @@ -103,6 +103,7 @@ allOf: properties: clocks: minItems: 4 + maxItems: 4 clock-names: items: - const: pcie diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Do= cumentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 1e05c560d797..4c76cd3f98a9 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -40,10 +40,11 @@ properties: - description: PCIe PHY clock. - description: Additional required clock entry for imx6sx-pcie, imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep. + - description: PCIe reference clock. =20 clock-names: minItems: 3 - maxItems: 4 + maxItems: 5 =20 interrupts: items: @@ -127,7 +128,7 @@ allOf: then: properties: clocks: - minItems: 4 + maxItems: 4 clock-names: items: - const: pcie @@ -140,11 +141,10 @@ allOf: compatible: enum: - fsl,imx8mq-pcie - - fsl,imx95-pcie then: properties: clocks: - minItems: 4 + maxItems: 4 clock-names: items: - const: pcie @@ -200,6 +200,23 @@ allOf: - const: mstr - const: slv =20 + - if: + properties: + compatible: + enum: + - fsl,imx95-pcie + then: + properties: + clocks: + maxItems: 5 + clock-names: + items: + - const: pcie + - const: pcie_bus + - const: pcie_phy + - const: pcie_aux + - const: ref + unevaluatedProperties: false =20 examples: --=20 2.37.1 From nobody Sun Nov 24 21:50:37 2024 Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2083.outbound.protection.outlook.com [40.107.21.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C2B813C8EA; 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Received: from AS8PR04MB8676.eurprd04.prod.outlook.com (2603:10a6:20b:42b::10) by PAXPR04MB8573.eurprd04.prod.outlook.com (2603:10a6:102:214::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.32; Fri, 1 Nov 2024 06:56:21 +0000 Received: from AS8PR04MB8676.eurprd04.prod.outlook.com ([fe80::28b2:de72:ad25:5d93]) by AS8PR04MB8676.eurprd04.prod.outlook.com ([fe80::28b2:de72:ad25:5d93%6]) with mapi id 15.20.8114.015; Fri, 1 Nov 2024 06:56:20 +0000 From: Richard Zhu To: l.stach@pengutronix.de, bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, frank.li@nxp.com, s.hauer@pengutronix.de, festevam@gmail.com Cc: imx@lists.linux.dev, kernel@pengutronix.de, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Richard Zhu , Frank Li Subject: [PATCH v6 02/10] PCI: imx6: Add ref clock for i.MX95 PCIe Date: Fri, 1 Nov 2024 15:06:02 +0800 Message-Id: <20241101070610.1267391-3-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20241101070610.1267391-1-hongxing.zhu@nxp.com> References: <20241101070610.1267391-1-hongxing.zhu@nxp.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SI1PR02CA0017.apcprd02.prod.outlook.com (2603:1096:4:1f4::10) To AS8PR04MB8676.eurprd04.prod.outlook.com (2603:10a6:20b:42b::10) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AS8PR04MB8676:EE_|PAXPR04MB8573:EE_ X-MS-Office365-Filtering-Correlation-Id: 46311ece-e334-4ec0-2562-08dcfa424a9f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|52116014|376014|7416014|1800799024|38350700014|921020; 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charset="utf-8" Add "ref" clock to enable reference clock. To avoid the DT compatibility, i.MX95 REF clock might be optional. Replace the devm_clk_bulk_get() by devm_clk_bulk_get_optional() to fetch i.MX95 PCIe optional clocks in driver. If use external clock, ref clock should point to external reference. If use internal clock, CREF_EN in LAST_TO_REG controls reference output, which implement in drivers/clk/imx/clk-imx95-blk-ctl.c. Signed-off-by: Richard Zhu Reviewed-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 808d1f105417..bc8567677a67 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -82,6 +82,7 @@ enum imx_pcie_variants { #define IMX_PCIE_FLAG_HAS_SERDES BIT(6) #define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7) #define IMX_PCIE_FLAG_CPU_ADDR_FIXUP BIT(8) +#define IMX_PCIE_FLAG_CUSTOM_PME_TURNOFF BIT(9) =20 #define imx_check_flag(pci, val) (pci->drvdata->flags & val) =20 @@ -98,6 +99,7 @@ struct imx_pcie_drvdata { const char *gpr; const char * const *clk_names; const u32 clks_cnt; + const u32 clks_optional_cnt; const u32 ltssm_off; const u32 ltssm_mask; const u32 mode_off[IMX_PCIE_MAX_INSTANCES]; @@ -1278,9 +1280,8 @@ static int imx_pcie_probe(struct platform_device *pde= v) struct device_node *np; struct resource *dbi_base; struct device_node *node =3D dev->of_node; - int ret; + int ret, i, req_cnt; u16 val; - int i; =20 imx_pcie =3D devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL); if (!imx_pcie) @@ -1330,7 +1331,10 @@ static int imx_pcie_probe(struct platform_device *pd= ev) imx_pcie->clks[i].id =3D imx_pcie->drvdata->clk_names[i]; =20 /* Fetch clocks */ - ret =3D devm_clk_bulk_get(dev, imx_pcie->drvdata->clks_cnt, imx_pcie->clk= s); + req_cnt =3D imx_pcie->drvdata->clks_cnt - imx_pcie->drvdata->clks_optiona= l_cnt; + ret =3D devm_clk_bulk_get(dev, req_cnt, imx_pcie->clks); + ret |=3D devm_clk_bulk_get_optional(dev, imx_pcie->drvdata->clks_optional= _cnt, + imx_pcie->clks + req_cnt); if (ret) return ret; =20 @@ -1480,6 +1484,7 @@ static const char * const imx8mm_clks[] =3D {"pcie_bu= s", "pcie", "pcie_aux"}; static const char * const imx8mq_clks[] =3D {"pcie_bus", "pcie", "pcie_phy= ", "pcie_aux"}; static const char * const imx6sx_clks[] =3D {"pcie_bus", "pcie", "pcie_phy= ", "pcie_inbound_axi"}; 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Received: from AS8PR04MB8676.eurprd04.prod.outlook.com (2603:10a6:20b:42b::10) by PAXPR04MB8573.eurprd04.prod.outlook.com (2603:10a6:102:214::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.32; Fri, 1 Nov 2024 06:56:26 +0000 Received: from AS8PR04MB8676.eurprd04.prod.outlook.com ([fe80::28b2:de72:ad25:5d93]) by AS8PR04MB8676.eurprd04.prod.outlook.com ([fe80::28b2:de72:ad25:5d93%6]) with mapi id 15.20.8114.015; Fri, 1 Nov 2024 06:56:26 +0000 From: Richard Zhu To: l.stach@pengutronix.de, bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, frank.li@nxp.com, s.hauer@pengutronix.de, festevam@gmail.com Cc: imx@lists.linux.dev, kernel@pengutronix.de, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Richard Zhu Subject: [PATCH v6 03/10] PCI: imx6: Fetch dbi2 and iATU base addesses from DT Date: Fri, 1 Nov 2024 15:06:03 +0800 Message-Id: <20241101070610.1267391-4-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20241101070610.1267391-1-hongxing.zhu@nxp.com> References: <20241101070610.1267391-1-hongxing.zhu@nxp.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SI1PR02CA0017.apcprd02.prod.outlook.com (2603:1096:4:1f4::10) To AS8PR04MB8676.eurprd04.prod.outlook.com (2603:10a6:20b:42b::10) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AS8PR04MB8676:EE_|PAXPR04MB8573:EE_ X-MS-Office365-Filtering-Correlation-Id: c4ad2b65-6f72-4681-ba05-08dcfa424dea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|52116014|376014|7416014|1800799024|38350700014|921020; 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charset="utf-8" Since dbi2 and atu regs are added for i.MX8M PCIes. Fetch the dbi2 and iATU base addresses from DT directly, and remove the useless codes. Upsteam dts's have not enabled EP function. So no function broken for old upsteam's dtb. Signed-off-by: Richard Zhu Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pci-imx6.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index bc8567677a67..462decd1d589 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1115,7 +1115,6 @@ static int imx_add_pcie_ep(struct imx_pcie *imx_pcie, struct platform_device *pdev) { int ret; - unsigned int pcie_dbi2_offset; struct dw_pcie_ep *ep; struct dw_pcie *pci =3D imx_pcie->pci; struct dw_pcie_rp *pp =3D &pci->pp; @@ -1125,25 +1124,6 @@ static int imx_add_pcie_ep(struct imx_pcie *imx_pcie, ep =3D &pci->ep; ep->ops =3D &pcie_ep_ops; =20 - switch (imx_pcie->drvdata->variant) { - case IMX8MQ_EP: - case IMX8MM_EP: - case IMX8MP_EP: - pcie_dbi2_offset =3D SZ_1M; - break; - default: - pcie_dbi2_offset =3D SZ_4K; - break; - } - - pci->dbi_base2 =3D pci->dbi_base + pcie_dbi2_offset; - - /* - * FIXME: Ideally, dbi2 base address should come from DT. But since only = IMX95 is defining - * "dbi2" in DT, "dbi_base2" is set to NULL here for that platform alone = so that the DWC - * core code can fetch that from DT. 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Fri, 1 Nov 2024 06:56:32 +0000 Received: from AS8PR04MB8676.eurprd04.prod.outlook.com ([fe80::28b2:de72:ad25:5d93]) by AS8PR04MB8676.eurprd04.prod.outlook.com ([fe80::28b2:de72:ad25:5d93%6]) with mapi id 15.20.8114.015; Fri, 1 Nov 2024 06:56:32 +0000 From: Richard Zhu To: l.stach@pengutronix.de, bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, frank.li@nxp.com, s.hauer@pengutronix.de, festevam@gmail.com Cc: imx@lists.linux.dev, kernel@pengutronix.de, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Richard Zhu , Frank Li Subject: [PATCH v6 04/10] PCI: imx6: Correct controller_id generation logic for i.MX7D Date: Fri, 1 Nov 2024 15:06:04 +0800 Message-Id: <20241101070610.1267391-5-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20241101070610.1267391-1-hongxing.zhu@nxp.com> References: <20241101070610.1267391-1-hongxing.zhu@nxp.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SI1PR02CA0017.apcprd02.prod.outlook.com (2603:1096:4:1f4::10) To AS8PR04MB8676.eurprd04.prod.outlook.com (2603:10a6:20b:42b::10) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AS8PR04MB8676:EE_|PAXPR04MB8573:EE_ X-MS-Office365-Filtering-Correlation-Id: 63c4728a-7d60-4744-5d19-08dcfa425157 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|52116014|376014|7416014|1800799024|38350700014|921020; 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charset="utf-8" i.MX7D only has one PCIe controller, so controller_id should always be 0. The previous code is incorrect although yielding the correct result. Fix by removing IMX7D from the switch case branch. Signed-off-by: Richard Zhu Reviewed-by: Frank Li Reviewed-by: Manivannan Sadhasivam --- "This is just *wrong*. You cannot hardcode the MMIO address in the driver. Even though this code is old, you should fix it instead of building on top of it. - Mani" IMX7D here is wrong athough check IMX8MQ_PCIE2_BASE_ADDR is not good method. Previously try to use 'linux,pci-domain' to replace this check logic. Need more discussion to improve it and keep old compatiblity. Let's fix this code error firstly. --- drivers/pci/controller/dwc/pci-imx6.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 462decd1d589..996333e9017d 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1342,7 +1342,6 @@ static int imx_pcie_probe(struct platform_device *pde= v) switch (imx_pcie->drvdata->variant) { case IMX8MQ: case IMX8MQ_EP: - case IMX7D: if (dbi_base->start =3D=3D IMX8MQ_PCIE2_BASE_ADDR) imx_pcie->controller_id =3D 1; break; --=20 2.37.1 From nobody Sun Nov 24 21:50:37 2024 Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2052.outbound.protection.outlook.com [40.107.21.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F361815624B; Fri, 1 Nov 2024 06:56:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Add apps_reset deassertion in the imx_pcie_deassert_core_reset(). Let it be symmetric with imx_pcie_assert_core_reset(). In the commit first introduced apps_reset, apps_reset is asserted in imx6_pcie_assert_core_reset(), but it is de-asserted in another place, in stead of the according symmetric function imx6_pcie_deassert_core_reset(). Use this patch to fix it, and make core reset assertion deasertion symmetric. Fixes: 9b3fe6796d7c ("PCI: imx6: Add code to support i.MX7D") Signed-off-by: Richard Zhu Reviewed-by: Frank Li Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pci-imx6.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 996333e9017d..54039d2760d5 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -772,6 +772,7 @@ static void imx_pcie_assert_core_reset(struct imx_pcie = *imx_pcie) static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie) { reset_control_deassert(imx_pcie->pciephy_reset); + reset_control_deassert(imx_pcie->apps_reset); =20 if (imx_pcie->drvdata->core_reset) imx_pcie->drvdata->core_reset(imx_pcie, false); --=20 2.37.1 From nobody Sun Nov 24 21:50:37 2024 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2074.outbound.protection.outlook.com [40.107.20.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20F62153BEE; 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charset="utf-8" Ensure the *_enable_ref_clk() function is symmetric by addressing missing disable parts on some platforms. Fixes: d0a75c791f98 ("PCI: imx6: Factor out ref clock disable to match enab= le") Signed-off-by: Richard Zhu Reviewed-by: Frank Li Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pci-imx6.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 54039d2760d5..bb130c84c016 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -595,10 +595,9 @@ static int imx_pcie_attach_pd(struct device *dev) =20 static int imx6sx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enab= le) { - if (enable) - regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_TEST_POWERDOWN); - + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX6SX_GPR12_PCIE_TEST_POWERDOWN, + enable ? 0 : IMX6SX_GPR12_PCIE_TEST_POWERDOWN); return 0; } =20 @@ -627,19 +626,20 @@ static int imx8mm_pcie_enable_ref_clk(struct imx_pcie= *imx_pcie, bool enable) { int offset =3D imx_pcie_grp_offset(imx_pcie); =20 - if (enable) { - regmap_clear_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_= OVERRIDE); - regmap_set_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OV= ERRIDE_EN); - } - + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, + IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, + enable ? 0 : IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE); + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, + IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, + enable ? 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charset="utf-8" Remove the duplicate imx7d_pcie_init_phy() function as it is the same as imx7d_pcie_enable_ref_clk(). Signed-off-by: Richard Zhu Reviewed-by: Frank Li Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pci-imx6.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index bb130c84c016..fde2f4eaf804 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -390,13 +390,6 @@ static int imx8mq_pcie_init_phy(struct imx_pcie *imx_p= cie) return 0; } =20 -static int imx7d_pcie_init_phy(struct imx_pcie *imx_pcie) -{ - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_P= HY_REFCLK_SEL, 0); - - return 0; -} - static int imx_pcie_init_phy(struct imx_pcie *imx_pcie) { regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, @@ -1526,7 +1519,6 @@ static const struct imx_pcie_drvdata drvdata[] =3D { .clks_cnt =3D ARRAY_SIZE(imx6q_clks), .mode_off[0] =3D IOMUXC_GPR12, .mode_mask[0] =3D IMX6Q_GPR12_DEVICE_TYPE, - .init_phy =3D imx7d_pcie_init_phy, .enable_ref_clk =3D imx7d_pcie_enable_ref_clk, .core_reset =3D imx7d_pcie_core_reset, }, --=20 2.37.1 From nobody Sun Nov 24 21:50:37 2024 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2042.outbound.protection.outlook.com [40.107.20.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3232715749C; 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charset="utf-8" From: Frank Li Call common dwc suspend/resume function. Use dwc common iATU method to send out PME_TURN_OFF message. In Old DWC implementations, PCIE_ATU_INHIBIT_PAYLOAD bit in iATU Ctrl2 register is reserved. So the generic DWC implementation of sending the PME_Turn_Off message using a dummy MMIO write cannot be used. Use previouse method to kick off PME_TURN_OFF MSG for these platforms. Replace the imx_pcie_stop_link() and imx_pcie_host_exit() by dw_pcie_suspend_noirq() in imx_pcie_suspend_noirq(). Since dw_pcie_suspend_noirq() already does these, see below call stack: dw_pcie_suspend_noirq() dw_pcie_stop_link(); imx_pcie_stop_link(); pci->pp.ops->deinit(); imx_pcie_host_exit(); Replace the imx_pcie_host_init(), dw_pcie_setup_rc() and imx_pcie_start_link() by dw_pcie_resume_noirq() in imx_pcie_resume_noirq(). Since dw_pcie_resume_noirq() already does these, see below call stack: dw_pcie_resume_noirq() pci->pp.ops->init(); imx_pcie_host_init(); dw_pcie_setup_rc(); dw_pcie_start_link(); imx_pcie_start_link(); Signed-off-by: Frank Li Signed-off-by: Richard Zhu --- drivers/pci/controller/dwc/pci-imx6.c | 95 ++++++++++----------------- 1 file changed, 34 insertions(+), 61 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index fde2f4eaf804..3c074cc2605f 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -33,6 +33,7 @@ #include #include =20 +#include "../../pci.h" #include "pcie-designware.h" =20 #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9) @@ -108,19 +109,18 @@ struct imx_pcie_drvdata { int (*init_phy)(struct imx_pcie *pcie); int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable); int (*core_reset)(struct imx_pcie *pcie, bool assert); + const struct dw_pcie_host_ops *ops; }; =20 struct imx_pcie { struct dw_pcie *pci; struct gpio_desc *reset_gpiod; - bool link_is_up; struct clk_bulk_data clks[IMX_PCIE_MAX_CLKS]; struct regmap *iomuxc_gpr; u16 msi_ctrl; u32 controller_id; struct reset_control *pciephy_reset; struct reset_control *apps_reset; - struct reset_control *turnoff_reset; u32 tx_deemph_gen1; u32 tx_deemph_gen2_3p5db; u32 tx_deemph_gen2_6db; @@ -899,13 +899,11 @@ static int imx_pcie_start_link(struct dw_pcie *pci) dev_info(dev, "Link: Only Gen1 is enabled\n"); } =20 - imx_pcie->link_is_up =3D true; tmp =3D dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS); return 0; =20 err_reset_phy: - imx_pcie->link_is_up =3D false; dev_dbg(dev, "PHY DEBUG_R0=3D0x%08x DEBUG_R1=3D0x%08x\n", dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0), dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1)); @@ -1024,9 +1022,32 @@ static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *p= cie, u64 cpu_addr) return cpu_addr - entry->offset; } =20 +/* + * In Old DWC implementations, PCIE_ATU_INHIBIT_PAYLOAD bit in iATU Ctrl2 + * register is reserved. So the generic DWC implementation of sending the + * PME_Turn_Off message using a dummy MMIO write cannot be used. + */ +static void imx_pcie_pme_turn_off(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct imx_pcie *imx_pcie =3D to_imx_pcie(pci); + + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_PM_= TURN_OFF); + regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_P= M_TURN_OFF); + + usleep_range(PCIE_PME_TO_L2_TIMEOUT_US/10, PCIE_PME_TO_L2_TIMEOUT_US); +} + + static const struct dw_pcie_host_ops imx_pcie_host_ops =3D { .init =3D imx_pcie_host_init, .deinit =3D imx_pcie_host_exit, + .pme_turn_off =3D imx_pcie_pme_turn_off, +}; + +static const struct dw_pcie_host_ops imx_pcie_host_dw_pme_ops =3D { + .init =3D imx_pcie_host_init, + .deinit =3D imx_pcie_host_exit, }; =20 static const struct dw_pcie_ops dw_pcie_ops =3D { @@ -1147,43 +1168,6 @@ static int imx_add_pcie_ep(struct imx_pcie *imx_pcie, return 0; } =20 -static void imx_pcie_pm_turnoff(struct imx_pcie *imx_pcie) -{ - struct device *dev =3D imx_pcie->pci->dev; - - /* Some variants have a turnoff reset in DT */ - if (imx_pcie->turnoff_reset) { - reset_control_assert(imx_pcie->turnoff_reset); - reset_control_deassert(imx_pcie->turnoff_reset); - goto pm_turnoff_sleep; - } - - /* Others poke directly at IOMUXC registers */ - switch (imx_pcie->drvdata->variant) { - case IMX6SX: - case IMX6QP: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_PM_TURN_OFF, - IMX6SX_GPR12_PCIE_PM_TURN_OFF); - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0); - break; - default: - dev_err(dev, "PME_Turn_Off not implemented\n"); - return; - } - - /* - * Components with an upstream port must respond to - * PME_Turn_Off with PME_TO_Ack but we can't check. - * - * The standard recommends a 1-10ms timeout after which to - * proceed anyway as if acks were received. - */ -pm_turnoff_sleep: - usleep_range(1000, 10000); -} - static void imx_pcie_msi_save_restore(struct imx_pcie *imx_pcie, bool save) { u8 offset; @@ -1207,36 +1191,26 @@ static void imx_pcie_msi_save_restore(struct imx_pc= ie *imx_pcie, bool save) static int imx_pcie_suspend_noirq(struct device *dev) { struct imx_pcie *imx_pcie =3D dev_get_drvdata(dev); - struct dw_pcie_rp *pp =3D &imx_pcie->pci->pp; =20 if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) return 0; =20 imx_pcie_msi_save_restore(imx_pcie, true); - imx_pcie_pm_turnoff(imx_pcie); - imx_pcie_stop_link(imx_pcie->pci); - imx_pcie_host_exit(pp); - - return 0; + return dw_pcie_suspend_noirq(imx_pcie->pci); } =20 static int imx_pcie_resume_noirq(struct device *dev) { int ret; struct imx_pcie *imx_pcie =3D dev_get_drvdata(dev); - struct dw_pcie_rp *pp =3D &imx_pcie->pci->pp; =20 if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) return 0; =20 - ret =3D imx_pcie_host_init(pp); + ret =3D dw_pcie_resume_noirq(imx_pcie->pci); if (ret) return ret; imx_pcie_msi_save_restore(imx_pcie, false); - dw_pcie_setup_rc(pp); - - if (imx_pcie->link_is_up) - imx_pcie_start_link(imx_pcie->pci); =20 return 0; } @@ -1267,11 +1241,14 @@ static int imx_pcie_probe(struct platform_device *p= dev) =20 pci->dev =3D dev; pci->ops =3D &dw_pcie_ops; - pci->pp.ops =3D &imx_pcie_host_ops; =20 imx_pcie->pci =3D pci; imx_pcie->drvdata =3D of_device_get_match_data(dev); =20 + pci->pp.ops =3D &imx_pcie_host_dw_pme_ops; + if (imx_pcie->drvdata->ops) + pci->pp.ops =3D imx_pcie->drvdata->ops; + /* Find the PHY if one is defined, only imx7d uses it */ np =3D of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); if (np) { @@ -1343,13 +1320,6 @@ static int imx_pcie_probe(struct platform_device *pd= ev) break; } =20 - /* Grab turnoff reset */ - imx_pcie->turnoff_reset =3D devm_reset_control_get_optional_exclusive(dev= , "turnoff"); - if (IS_ERR(imx_pcie->turnoff_reset)) { - dev_err(dev, "Failed to get TURNOFF reset control\n"); - return PTR_ERR(imx_pcie->turnoff_reset); - } - if (imx_pcie->drvdata->gpr) { /* Grab GPR config register range */ imx_pcie->iomuxc_gpr =3D @@ -1428,6 +1398,7 @@ static int imx_pcie_probe(struct platform_device *pde= v) if (ret < 0) return ret; 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charset="utf-8" Add iMX8MQ i.MX8Q and i.MX95 PCIe suspend/resume support. Signed-off-by: Richard Zhu Reviewed-by: Frank Li Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pci-imx6.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 3c074cc2605f..cf2a9918537e 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1498,7 +1498,8 @@ static const struct imx_pcie_drvdata drvdata[] =3D { [IMX8MQ] =3D { .variant =3D IMX8MQ, .flags =3D IMX_PCIE_FLAG_HAS_APP_RESET | - IMX_PCIE_FLAG_HAS_PHY_RESET, + IMX_PCIE_FLAG_HAS_PHY_RESET | + IMX_PCIE_FLAG_SUPPORTS_SUSPEND, .gpr =3D "fsl,imx8mq-iomuxc-gpr", .clk_names =3D imx8mq_clks, .clks_cnt =3D ARRAY_SIZE(imx8mq_clks), @@ -1536,7 +1537,8 @@ static const struct imx_pcie_drvdata drvdata[] =3D { [IMX8Q] =3D { .variant =3D IMX8Q, .flags =3D IMX_PCIE_FLAG_HAS_PHYDRV | - IMX_PCIE_FLAG_CPU_ADDR_FIXUP, + IMX_PCIE_FLAG_CPU_ADDR_FIXUP | + IMX_PCIE_FLAG_SUPPORTS_SUSPEND, .clk_names =3D imx8q_clks, .clks_cnt =3D ARRAY_SIZE(imx8q_clks), }, --=20 2.37.1 From nobody Sun Nov 24 21:50:37 2024 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2047.outbound.protection.outlook.com [40.107.20.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96A8E158DC8; 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charset="utf-8" Add ref clock for i.MX95 PCIe here, when the internal PLL is used as PCIe reference clock. Signed-off-by: Richard Zhu Reviewed-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95.dtsi | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts= /freescale/imx95.dtsi index 03661e76550f..5cb504b5f851 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -1473,6 +1473,14 @@ smmu: iommu@490d0000 { }; }; =20 + hsio_blk_ctl: syscon@4c0100c0 { + compatible =3D "nxp,imx95-hsio-blk-ctl", "syscon"; + reg =3D <0x0 0x4c0100c0 0x0 0x4>; + #clock-cells =3D <1>; + clocks =3D <&dummy>; + power-domains =3D <&scmi_devpd IMX95_PD_HSIO_TOP>; + }; + pcie0: pcie@4c300000 { compatible =3D "fsl,imx95-pcie"; reg =3D <0 0x4c300000 0 0x10000>, @@ -1500,8 +1508,9 @@ pcie0: pcie@4c300000 { clocks =3D <&scmi_clk IMX95_CLK_HSIO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; - clock-names =3D "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>; + clock-names =3D "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; assigned-clocks =3D<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; @@ -1528,8 +1537,9 @@ pcie0_ep: pcie-ep@4c300000 { clocks =3D <&scmi_clk IMX95_CLK_HSIO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; - clock-names =3D "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>; + clock-names =3D "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; assigned-clocks =3D<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; --=20 2.37.1