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charset="utf-8" The rxmacro, txmacro, vamacro, soundwire nodes, lpass clock controllers are required to support audio playback and audio capture on sm6115 and its derivatives. Cc: Konrad Dybcio Cc: Konrad Dybcio Cc: Srinivas Kandagatla Co-developed-by: Konrad Dybcio Signed-off-by: Alexey Klimov --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 132 +++++++++++++++++++++++++++ 1 file changed, 132 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qco= m/sm6115.dtsi index df2241237b26..8518a04edcbf 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -2687,6 +2687,138 @@ funnel_apss1_in: endpoint { }; }; =20 + rxmacro: codec@a600000 { + compatible =3D "qcom,sm6115-lpass-rx-macro", "qcom,sm8250-lpass-rx-macr= o"; + reg =3D <0x0 0xa600000 0x0 0x1000>; + + clocks =3D <&q6afecc LPASS_CLK_ID_RX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6afecc LPASS_CLK_ID_RX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO= >, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names =3D "mclk", + "npl", + "dcodec", + "fsgen"; + assigned-clocks =3D <&q6afecc LPASS_CLK_ID_RX_CORE_MCLK LPASS_CLK_ATTRI= BUTE_COUPLE_NO>, + <&q6afecc LPASS_CLK_ID_RX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_= NO>; + assigned-clock-rates =3D <22579200>, + <22579200>; + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + }; + + swr1: soundwire-controller@a610000 { + compatible =3D "qcom,soundwire-v1.6.0"; + reg =3D <0x0 0x0a610000 0x0 0x2000>; + interrupts =3D ; + + clocks =3D <&rxmacro>; + clock-names =3D "iface"; + + resets =3D <&lpass_audiocc 0>; + reset-names =3D "swr_audio_cgcr"; + + label =3D "RX"; + qcom,din-ports =3D <0>; + qcom,dout-ports =3D <5>; + + qcom,ports-sinterval-low =3D /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; + qcom,ports-offset1 =3D /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; + qcom,ports-word-length =3D /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; + qcom,ports-lane-control =3D /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; + + #sound-dai-cells =3D <1>; + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + + txmacro: codec@a620000 { + compatible =3D "qcom,sm6115-lpass-tx-macro"; + reg =3D <0x0 0x0a620000 0x0 0x1000>; + + clocks =3D <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO= >, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names =3D "mclk", + "npl", + "dcodec", + "fsgen"; + assigned-clocks =3D <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRI= BUTE_COUPLE_NO>, + <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_= NO>; + assigned-clock-rates =3D <19200000>, + <19200000>; + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + }; + + lpass_audiocc: clock-controller@a6a9000 { + compatible =3D "qcom,sm6115-lpassaudiocc"; + reg =3D <0x0 0x0a6a9000 0x0 0x1000>; + #reset-cells =3D <1>; + }; + + vamacro: codec@a730000 { + compatible =3D "qcom,sm6115-lpass-va-macro", "qcom,sm8450-lpass-va-macr= o"; + reg =3D <0x0 0x0a730000 0x0 0x1000>; + clocks =3D <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO= >; + clock-names =3D "mclk", + "dcodec", + "npl"; + assigned-clocks =3D <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRI= BUTE_COUPLE_NO>, + <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_= NO>; + assigned-clock-rates =3D <19200000>, + <19200000>; + #clock-cells =3D <0>; + clock-output-names =3D "fsgen"; + #sound-dai-cells =3D <1>; + }; + + swr0: soundwire-controller@a740000 { + compatible =3D "qcom,soundwire-v1.6.0"; + reg =3D <0x0 0x0a740000 0x0 0x2000>; + interrupts =3D , + ; + clocks =3D <&txmacro>; + clock-names =3D "iface"; + + resets =3D <&lpasscc 0>; + reset-names =3D "swr_audio_cgcr"; + + label =3D "VA_TX"; + qcom,din-ports =3D <3>; + qcom,dout-ports =3D <0>; + + qcom,ports-sinterval-low =3D /bits/ 8 <0x03 0x03 0x03>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x02 0x01>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x00>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0x00 0x00 0x00>; + + #sound-dai-cells =3D <1>; + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + + lpasscc: clock-controller@a7ec000 { + compatible =3D "qcom,sm6115-lpasscc"; + reg =3D <0x0 0x0a7ec000 0x0 0x1000>; + #reset-cells =3D <1>; + }; + remoteproc_adsp: remoteproc@ab00000 { compatible =3D "qcom,sm6115-adsp-pas"; reg =3D <0x0 0x0ab00000 0x0 0x100>; --=20 2.45.2