From nobody Mon Nov 25 00:35:00 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2B205D8F0; Fri, 1 Nov 2024 07:10:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730445040; cv=none; b=ggDvc6WrOnfZqsqeKXAhgVbZQleNM/a0/vJ0lnzOwWm/5HKV9MvCUROJB083gFzO76IZ4pPhx8IRUq5TtDu1s0IH7jwN9bHq9QZbuBGR+9m0RVoxMK+OT7k5w5vEEre6unpsbICFJXbPz5xrViCHcrQGQ++zzbtFaClX1CHWxqo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730445040; c=relaxed/simple; bh=yCEiD1fSKVYVBKnay6M7zI4FI8mv2M02DwwcBGReapE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=o+fbPZN7Tovc/4Cg6aBFA1A7+K04FGVf3CkUM5F5jxZuaeO77P37S8t4D9DSAvhhyo/iXu/FmG+DdMN0229usH1teCvOb0GxtVUfB+r/UJUdYq64MxDExjicBXZcg68iFU4ePecER721oNzwxhscvSVE/bno/OiMDW1H2iWm03Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=1n/Umr4u; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="1n/Umr4u" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1730445033; x=1761981033; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=yCEiD1fSKVYVBKnay6M7zI4FI8mv2M02DwwcBGReapE=; b=1n/Umr4uvJZUKZZU6R85vrfca76jTsvXJGyw6H+owJlbQ54IqqzcX/sw Gkww8FrIKW4KR7Y5xBQzTvbuMJcy6JYE6xppiPighVN5VLrqprs0IGy4l NXMiCAvXCO4PARqM/2gl9ZMf4pj52XGnvpEL521CJat2QLWK0ifm1hE/5 qnbDNaFExocnrkJ3S++Tf4vPTgaFQPIoclxUJ876+/9V0WLbIKPnpjXMx QuAFksdyKGNx7HjKcBqoZhCP+58mXWTmChN+yLEuyoupbqB49zZJJBUA8 g4K0eOA+yoBK8eZdOaZ4jLZlIDxl6sS1YPrOfuGiv0ImPdPRk5bqODR+r A==; X-CSE-ConnectionGUID: j3YBXS8JS+qztkz9gl3BFg== X-CSE-MsgGUID: 1RhtrmrdR36dzeZpfiKfcA== X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="264868825" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 01 Nov 2024 00:10:31 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 1 Nov 2024 00:10:05 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 1 Nov 2024 00:10:03 -0700 From: Daniel Machon Date: Fri, 1 Nov 2024 08:09:11 +0100 Subject: [PATCH net-next 5/6] net: lan969x: add autogenerated VCAP information Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241101-sparx5-lan969x-switch-driver-3-v1-5-3c76f22f4bfa@microchip.com> References: <20241101-sparx5-lan969x-switch-driver-3-v1-0-3c76f22f4bfa@microchip.com> In-Reply-To: <20241101-sparx5-lan969x-switch-driver-3-v1-0-3c76f22f4bfa@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Lars Povlsen , Steen Hegelund , =?utf-8?q?Jens_Emil_Schulz_=C3=98stergaard?= , , , CC: , , X-Mailer: b4 0.14-dev Platform VCAP data for each VCAP instance is auto-generated using an internal Microchip tool. The generated VCAP data contains information about keyfields, keyfield sets, actionfields, actionfield sets and typegroups, which in combination are used to encode and decode rules in the VCAP. Add the auto-generated VCAP file lan969x_vcap_ag_api.c and assign the two structs: lan969x_vcaps and lan969x_vcap_stats to the match data. Reviewed-by: Steen Hegelund Reviewed-by: Jens Emil Schulz =C3=98stergaard Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/lan969x/Makefile | 3 +- drivers/net/ethernet/microchip/lan969x/lan969x.c | 2 + drivers/net/ethernet/microchip/lan969x/lan969x.h | 5 + .../microchip/lan969x/lan969x_vcap_ag_api.c | 3843 ++++++++++++++++= ++++ 4 files changed, 3852 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/microchip/lan969x/Makefile b/drivers/net/= ethernet/microchip/lan969x/Makefile index 82d318a7219c..3ea560e08a21 100644 --- a/drivers/net/ethernet/microchip/lan969x/Makefile +++ b/drivers/net/ethernet/microchip/lan969x/Makefile @@ -5,7 +5,8 @@ =20 obj-$(CONFIG_LAN969X_SWITCH) +=3D lan969x-switch.o =20 -lan969x-switch-y :=3D lan969x_regs.o lan969x.o lan969x_calendar.o +lan969x-switch-y :=3D lan969x_regs.o lan969x.o lan969x_calendar.o \ + lan969x_vcap_ag_api.o =20 # Provide include files ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/microchip/fdma diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x.c b/drivers/net= /ethernet/microchip/lan969x/lan969x.c index 79e5bcefbd73..0cb9ec1d2054 100644 --- a/drivers/net/ethernet/microchip/lan969x/lan969x.c +++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c @@ -319,6 +319,8 @@ static const struct sparx5_consts lan969x_consts =3D { .qres_max_prio_idx =3D 315, .qres_max_colour_idx =3D 323, .tod_pin =3D 4, + .vcaps =3D lan969x_vcaps, + .vcap_stats =3D &lan969x_vcap_stats, }; =20 static const struct sparx5_ops lan969x_ops =3D { diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x.h b/drivers/net= /ethernet/microchip/lan969x/lan969x.h index 7ce047ad9ca4..167281d99c50 100644 --- a/drivers/net/ethernet/microchip/lan969x/lan969x.h +++ b/drivers/net/ethernet/microchip/lan969x/lan969x.h @@ -9,10 +9,15 @@ =20 #include "../sparx5/sparx5_main.h" #include "../sparx5/sparx5_regs.h" +#include "../sparx5/sparx5_vcap_impl.h" =20 /* lan969x.c */ extern const struct sparx5_match_data lan969x_desc; =20 +/* lan969x_vcap_ag_api.c */ +extern const struct vcap_statistics lan969x_vcap_stats; +extern const struct vcap_info lan969x_vcaps[]; + /* lan969x_regs.c */ extern const unsigned int lan969x_tsize[TSIZE_LAST]; extern const unsigned int lan969x_raddr[RADDR_LAST]; diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x_vcap_ag_api.c b= /drivers/net/ethernet/microchip/lan969x/lan969x_vcap_ag_api.c new file mode 100644 index 000000000000..7acc5bcf337a --- /dev/null +++ b/drivers/net/ethernet/microchip/lan969x/lan969x_vcap_ag_api.c @@ -0,0 +1,3843 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. + * Microchip VCAP API + */ + +/* This file is autogenerated by cml-utils 2024-10-07 11:10:56 +0200. + * Commit ID: b5ddc8e244eb2481a9524f1ddc630a8b41e7c391 + */ + +#include +#include + +#include "lan969x.h" + +/* keyfields */ +static const struct vcap_field is0_normal_7tuple_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 0, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 1, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_GEN_IDX_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 2, + .width =3D 2, + }, + [VCAP_KF_LOOKUP_GEN_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 4, + .width =3D 10, + }, + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 14, + .width =3D 2, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U72, + .offset =3D 16, + .width =3D 65, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 81, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 82, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 83, + .width =3D 3, + }, + [VCAP_KF_8021Q_TPID0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 86, + .width =3D 3, + }, + [VCAP_KF_8021Q_PCP0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 89, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 92, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 93, + .width =3D 12, + }, + [VCAP_KF_8021Q_TPID1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 105, + .width =3D 3, + }, + [VCAP_KF_8021Q_PCP1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 108, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI1] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 111, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 112, + .width =3D 12, + }, + [VCAP_KF_8021Q_TPID2] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 124, + .width =3D 3, + }, + [VCAP_KF_8021Q_PCP2] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 127, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI2] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 130, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID2] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 131, + .width =3D 12, + }, + [VCAP_KF_L2_DMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 144, + .width =3D 48, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 192, + .width =3D 48, + }, + [VCAP_KF_IP_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 240, + .width =3D 1, + }, + [VCAP_KF_ETYPE_LEN_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 241, + .width =3D 1, + }, + [VCAP_KF_ETYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 242, + .width =3D 16, + }, + [VCAP_KF_IP_SNAP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 258, + .width =3D 1, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 259, + .width =3D 1, + }, + [VCAP_KF_L3_FRAGMENT_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 260, + .width =3D 2, + }, + [VCAP_KF_L3_FRAG_INVLD_L4_LEN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 262, + .width =3D 1, + }, + [VCAP_KF_L3_OPTIONS_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 263, + .width =3D 1, + }, + [VCAP_KF_L3_DSCP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 264, + .width =3D 6, + }, + [VCAP_KF_L3_IP6_DIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 270, + .width =3D 128, + }, + [VCAP_KF_L3_IP6_SIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 398, + .width =3D 128, + }, + [VCAP_KF_TCP_UDP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 526, + .width =3D 1, + }, + [VCAP_KF_TCP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 527, + .width =3D 1, + }, + [VCAP_KF_L4_SPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 528, + .width =3D 16, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 544, + .width =3D 8, + }, +}; + +static const struct vcap_field is0_normal_5tuple_ip4_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 2, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 2, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_GEN_IDX_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 3, + .width =3D 2, + }, + [VCAP_KF_LOOKUP_GEN_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 10, + }, + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 15, + .width =3D 2, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U72, + .offset =3D 17, + .width =3D 65, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 82, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 83, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 84, + .width =3D 3, + }, + [VCAP_KF_8021Q_TPID0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 87, + .width =3D 3, + }, + [VCAP_KF_8021Q_PCP0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 90, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 93, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 94, + .width =3D 12, + }, + [VCAP_KF_8021Q_TPID1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 106, + .width =3D 3, + }, + [VCAP_KF_8021Q_PCP1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 109, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI1] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 112, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 113, + .width =3D 12, + }, + [VCAP_KF_8021Q_TPID2] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 125, + .width =3D 3, + }, + [VCAP_KF_8021Q_PCP2] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 128, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI2] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 131, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID2] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 132, + .width =3D 12, + }, + [VCAP_KF_IP_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 145, + .width =3D 1, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 146, + .width =3D 1, + }, + [VCAP_KF_L3_FRAGMENT_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 147, + .width =3D 2, + }, + [VCAP_KF_L3_FRAG_INVLD_L4_LEN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 149, + .width =3D 1, + }, + [VCAP_KF_L3_OPTIONS_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 150, + .width =3D 1, + }, + [VCAP_KF_L3_DSCP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 151, + .width =3D 6, + }, + [VCAP_KF_L3_IP4_DIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 157, + .width =3D 32, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 189, + .width =3D 32, + }, + [VCAP_KF_L3_IP_PROTO] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 221, + .width =3D 8, + }, + [VCAP_KF_TCP_UDP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 229, + .width =3D 1, + }, + [VCAP_KF_TCP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 230, + .width =3D 1, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 231, + .width =3D 8, + }, + [VCAP_KF_IP_PAYLOAD_5TUPLE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 239, + .width =3D 32, + }, +}; + +static const struct vcap_field is2_mac_etype_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 14, + .width =3D 4, + }, + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 18, + .width =3D 2, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 20, + .width =3D 32, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 52, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 53, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 54, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 56, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 57, + .width =3D 10, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 67, + .width =3D 13, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 80, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 81, + .width =3D 3, + }, + [VCAP_KF_L2_FWD_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 84, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 87, + .width =3D 1, + }, + [VCAP_KF_L3_DST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 88, + .width =3D 1, + }, + [VCAP_KF_L2_DMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 89, + .width =3D 48, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 137, + .width =3D 48, + }, + [VCAP_KF_ETYPE_LEN_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 185, + .width =3D 1, + }, + [VCAP_KF_ETYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 186, + .width =3D 16, + }, + [VCAP_KF_L2_PAYLOAD_ETYPE] =3D { + .type =3D VCAP_FIELD_U64, + .offset =3D 202, + .width =3D 64, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 266, + .width =3D 16, + }, + [VCAP_KF_OAM_CCM_CNTS_EQ0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 282, + .width =3D 1, + }, + [VCAP_KF_OAM_Y1731_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 283, + .width =3D 1, + }, +}; + +static const struct vcap_field is2_arp_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 14, + .width =3D 4, + }, + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 18, + .width =3D 2, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 20, + .width =3D 32, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 52, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 53, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 54, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 56, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 57, + .width =3D 10, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 67, + .width =3D 13, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 80, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 81, + .width =3D 3, + }, + [VCAP_KF_L2_FWD_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 84, + .width =3D 1, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 85, + .width =3D 48, + }, + [VCAP_KF_ARP_ADDR_SPACE_OK_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 133, + .width =3D 1, + }, + [VCAP_KF_ARP_PROTO_SPACE_OK_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 134, + .width =3D 1, + }, + [VCAP_KF_ARP_LEN_OK_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 135, + .width =3D 1, + }, + [VCAP_KF_ARP_TGT_MATCH_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 136, + .width =3D 1, + }, + [VCAP_KF_ARP_SENDER_MATCH_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 137, + .width =3D 1, + }, + [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 138, + .width =3D 1, + }, + [VCAP_KF_ARP_OPCODE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 139, + .width =3D 2, + }, + [VCAP_KF_L3_IP4_DIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 141, + .width =3D 32, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 173, + .width =3D 32, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 205, + .width =3D 1, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 206, + .width =3D 16, + }, +}; + +static const struct vcap_field is2_ip4_tcp_udp_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 14, + .width =3D 4, + }, + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 18, + .width =3D 2, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 20, + .width =3D 32, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 52, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 53, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 54, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 56, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 57, + .width =3D 10, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 67, + .width =3D 13, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 80, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 81, + .width =3D 3, + }, + [VCAP_KF_L2_FWD_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 84, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 87, + .width =3D 1, + }, + [VCAP_KF_L3_DST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 88, + .width =3D 1, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 89, + .width =3D 1, + }, + [VCAP_KF_L3_FRAGMENT_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 90, + .width =3D 2, + }, + [VCAP_KF_L3_FRAG_INVLD_L4_LEN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 92, + .width =3D 1, + }, + [VCAP_KF_L3_OPTIONS_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 93, + .width =3D 1, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 94, + .width =3D 1, + }, + [VCAP_KF_L3_TOS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 95, + .width =3D 8, + }, + [VCAP_KF_L3_IP4_DIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 103, + .width =3D 32, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 135, + .width =3D 32, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 167, + .width =3D 1, + }, + [VCAP_KF_TCP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 168, + .width =3D 1, + }, + [VCAP_KF_L4_DPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 169, + .width =3D 16, + }, + [VCAP_KF_L4_SPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 185, + .width =3D 16, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 201, + .width =3D 16, + }, + [VCAP_KF_L4_SPORT_EQ_DPORT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 217, + .width =3D 1, + }, + [VCAP_KF_L4_SEQUENCE_EQ0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 218, + .width =3D 1, + }, + [VCAP_KF_L4_FIN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 219, + .width =3D 1, + }, + [VCAP_KF_L4_SYN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 220, + .width =3D 1, + }, + [VCAP_KF_L4_RST] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 221, + .width =3D 1, + }, + [VCAP_KF_L4_PSH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 222, + .width =3D 1, + }, + [VCAP_KF_L4_ACK] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 223, + .width =3D 1, + }, + [VCAP_KF_L4_URG] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 224, + .width =3D 1, + }, + [VCAP_KF_L4_PAYLOAD] =3D { + .type =3D VCAP_FIELD_U64, + .offset =3D 225, + .width =3D 64, + }, +}; + +static const struct vcap_field is2_ip4_other_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 14, + .width =3D 4, + }, + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 18, + .width =3D 2, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 20, + .width =3D 32, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 52, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 53, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 54, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 56, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 57, + .width =3D 10, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 67, + .width =3D 13, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 80, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 81, + .width =3D 3, + }, + [VCAP_KF_L2_FWD_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 84, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 87, + .width =3D 1, + }, + [VCAP_KF_L3_DST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 88, + .width =3D 1, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 89, + .width =3D 1, + }, + [VCAP_KF_L3_FRAGMENT_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 90, + .width =3D 2, + }, + [VCAP_KF_L3_FRAG_INVLD_L4_LEN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 92, + .width =3D 1, + }, + [VCAP_KF_L3_OPTIONS_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 93, + .width =3D 1, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 94, + .width =3D 1, + }, + [VCAP_KF_L3_TOS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 95, + .width =3D 8, + }, + [VCAP_KF_L3_IP4_DIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 103, + .width =3D 32, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 135, + .width =3D 32, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 167, + .width =3D 1, + }, + [VCAP_KF_L3_IP_PROTO] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 168, + .width =3D 8, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 176, + .width =3D 16, + }, + [VCAP_KF_L3_PAYLOAD] =3D { + .type =3D VCAP_FIELD_U112, + .offset =3D 192, + .width =3D 96, + }, +}; + +static const struct vcap_field is2_ip6_std_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 14, + .width =3D 4, + }, + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 18, + .width =3D 2, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 20, + .width =3D 32, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 52, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 53, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 54, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 56, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 57, + .width =3D 10, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 67, + .width =3D 13, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 80, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 81, + .width =3D 3, + }, + [VCAP_KF_L2_FWD_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 84, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 87, + .width =3D 1, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 89, + .width =3D 1, + }, + [VCAP_KF_L3_IP6_SIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 90, + .width =3D 128, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 218, + .width =3D 1, + }, + [VCAP_KF_L3_IP_PROTO] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 219, + .width =3D 8, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 227, + .width =3D 16, + }, + [VCAP_KF_L3_PAYLOAD] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 243, + .width =3D 40, + }, +}; + +static const struct vcap_field is2_ip_7tuple_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 2, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 2, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 3, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 11, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 12, + .width =3D 4, + }, + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 16, + .width =3D 2, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U72, + .offset =3D 18, + .width =3D 65, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 83, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 84, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 85, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 87, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 88, + .width =3D 10, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 98, + .width =3D 13, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 111, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 112, + .width =3D 3, + }, + [VCAP_KF_L2_FWD_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 115, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 118, + .width =3D 1, + }, + [VCAP_KF_L3_DST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 119, + .width =3D 1, + }, + [VCAP_KF_L2_DMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 120, + .width =3D 48, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 168, + .width =3D 48, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 218, + .width =3D 1, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 219, + .width =3D 1, + }, + [VCAP_KF_L3_TOS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 220, + .width =3D 8, + }, + [VCAP_KF_L3_IP6_DIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 228, + .width =3D 128, + }, + [VCAP_KF_L3_IP6_SIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 356, + .width =3D 128, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 484, + .width =3D 1, + }, + [VCAP_KF_TCP_UDP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 485, + .width =3D 1, + }, + [VCAP_KF_TCP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 486, + .width =3D 1, + }, + [VCAP_KF_L4_DPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 487, + .width =3D 16, + }, + [VCAP_KF_L4_SPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 503, + .width =3D 16, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 519, + .width =3D 16, + }, + [VCAP_KF_L4_SPORT_EQ_DPORT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 535, + .width =3D 1, + }, + [VCAP_KF_L4_SEQUENCE_EQ0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 536, + .width =3D 1, + }, + [VCAP_KF_L4_FIN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 537, + .width =3D 1, + }, + [VCAP_KF_L4_SYN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 538, + .width =3D 1, + }, + [VCAP_KF_L4_RST] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 539, + .width =3D 1, + }, + [VCAP_KF_L4_PSH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 540, + .width =3D 1, + }, + [VCAP_KF_L4_ACK] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 541, + .width =3D 1, + }, + [VCAP_KF_L4_URG] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 542, + .width =3D 1, + }, + [VCAP_KF_L4_PAYLOAD] =3D { + .type =3D VCAP_FIELD_U64, + .offset =3D 543, + .width =3D 64, + }, +}; + +static const struct vcap_field es0_isdx_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 0, + .width =3D 1, + }, + [VCAP_KF_IF_EGR_PORT_NO] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 1, + .width =3D 6, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 7, + .width =3D 13, + }, + [VCAP_KF_COSID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 20, + .width =3D 3, + }, + [VCAP_KF_8021Q_TPID] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 23, + .width =3D 3, + }, + [VCAP_KF_L3_DPL_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 26, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 27, + .width =3D 1, + }, + [VCAP_KF_PROT_ACTIVE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 28, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 38, + .width =3D 10, + }, +}; + +static const struct vcap_field es2_mac_etype_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 3, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 3, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 14, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 15, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 16, + .width =3D 10, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 26, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 28, + .width =3D 13, + }, + [VCAP_KF_IF_EGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 41, + .width =3D 3, + }, + [VCAP_KF_IF_EGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 44, + .width =3D 32, + }, + [VCAP_KF_IF_IGR_PORT_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 76, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 77, + .width =3D 7, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 84, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 87, + .width =3D 1, + }, + [VCAP_KF_COSID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 88, + .width =3D 3, + }, + [VCAP_KF_L3_DPL_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 91, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 92, + .width =3D 1, + }, + [VCAP_KF_L2_DMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 96, + .width =3D 48, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 144, + .width =3D 48, + }, + [VCAP_KF_ETYPE_LEN_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 192, + .width =3D 1, + }, + [VCAP_KF_ETYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 193, + .width =3D 16, + }, + [VCAP_KF_L2_PAYLOAD_ETYPE] =3D { + .type =3D VCAP_FIELD_U64, + .offset =3D 209, + .width =3D 64, + }, + [VCAP_KF_OAM_CCM_CNTS_EQ0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 273, + .width =3D 1, + }, + [VCAP_KF_OAM_Y1731_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 274, + .width =3D 1, + }, +}; + +static const struct vcap_field es2_arp_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 3, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 3, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 14, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 15, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 16, + .width =3D 10, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 26, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 28, + .width =3D 13, + }, + [VCAP_KF_IF_EGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 41, + .width =3D 3, + }, + [VCAP_KF_IF_EGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 44, + .width =3D 32, + }, + [VCAP_KF_IF_IGR_PORT_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 76, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 77, + .width =3D 7, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 84, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 87, + .width =3D 1, + }, + [VCAP_KF_COSID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 88, + .width =3D 3, + }, + [VCAP_KF_L3_DPL_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 91, + .width =3D 1, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 95, + .width =3D 48, + }, + [VCAP_KF_ARP_ADDR_SPACE_OK_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 143, + .width =3D 1, + }, + [VCAP_KF_ARP_PROTO_SPACE_OK_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 144, + .width =3D 1, + }, + [VCAP_KF_ARP_LEN_OK_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 145, + .width =3D 1, + }, + [VCAP_KF_ARP_TGT_MATCH_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 146, + .width =3D 1, + }, + [VCAP_KF_ARP_SENDER_MATCH_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 147, + .width =3D 1, + }, + [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 148, + .width =3D 1, + }, + [VCAP_KF_ARP_OPCODE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 149, + .width =3D 2, + }, + [VCAP_KF_L3_IP4_DIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 151, + .width =3D 32, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 183, + .width =3D 32, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 215, + .width =3D 1, + }, +}; + +static const struct vcap_field es2_ip4_tcp_udp_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 3, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 3, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 14, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 15, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 16, + .width =3D 10, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 26, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 28, + .width =3D 13, + }, + [VCAP_KF_IF_EGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 41, + .width =3D 3, + }, + [VCAP_KF_IF_EGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 44, + .width =3D 32, + }, + [VCAP_KF_IF_IGR_PORT_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 76, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 77, + .width =3D 7, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 84, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 87, + .width =3D 1, + }, + [VCAP_KF_COSID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 88, + .width =3D 3, + }, + [VCAP_KF_L3_DPL_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 91, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 92, + .width =3D 1, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 96, + .width =3D 1, + }, + [VCAP_KF_L3_FRAGMENT_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 97, + .width =3D 2, + }, + [VCAP_KF_L3_OPTIONS_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 99, + .width =3D 1, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 100, + .width =3D 1, + }, + [VCAP_KF_L3_TOS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 101, + .width =3D 8, + }, + [VCAP_KF_L3_IP4_DIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 109, + .width =3D 32, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 141, + .width =3D 32, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 173, + .width =3D 1, + }, + [VCAP_KF_TCP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 174, + .width =3D 1, + }, + [VCAP_KF_L4_DPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 175, + .width =3D 16, + }, + [VCAP_KF_L4_SPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 191, + .width =3D 16, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 207, + .width =3D 16, + }, + [VCAP_KF_L4_SPORT_EQ_DPORT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 223, + .width =3D 1, + }, + [VCAP_KF_L4_SEQUENCE_EQ0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 224, + .width =3D 1, + }, + [VCAP_KF_L4_FIN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 225, + .width =3D 1, + }, + [VCAP_KF_L4_SYN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 226, + .width =3D 1, + }, + [VCAP_KF_L4_RST] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 227, + .width =3D 1, + }, + [VCAP_KF_L4_PSH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 228, + .width =3D 1, + }, + [VCAP_KF_L4_ACK] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 229, + .width =3D 1, + }, + [VCAP_KF_L4_URG] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 230, + .width =3D 1, + }, + [VCAP_KF_L4_PAYLOAD] =3D { + .type =3D VCAP_FIELD_U64, + .offset =3D 231, + .width =3D 64, + }, +}; + +static const struct vcap_field es2_ip4_other_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 3, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 3, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 14, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 15, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 16, + .width =3D 10, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 26, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 28, + .width =3D 13, + }, + [VCAP_KF_IF_EGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 41, + .width =3D 3, + }, + [VCAP_KF_IF_EGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 44, + .width =3D 32, + }, + [VCAP_KF_IF_IGR_PORT_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 76, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 77, + .width =3D 7, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 84, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 87, + .width =3D 1, + }, + [VCAP_KF_COSID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 88, + .width =3D 3, + }, + [VCAP_KF_L3_DPL_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 91, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 92, + .width =3D 1, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 96, + .width =3D 1, + }, + [VCAP_KF_L3_FRAGMENT_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 97, + .width =3D 2, + }, + [VCAP_KF_L3_OPTIONS_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 99, + .width =3D 1, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 100, + .width =3D 1, + }, + [VCAP_KF_L3_TOS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 101, + .width =3D 8, + }, + [VCAP_KF_L3_IP4_DIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 109, + .width =3D 32, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 141, + .width =3D 32, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 173, + .width =3D 1, + }, + [VCAP_KF_L3_IP_PROTO] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 174, + .width =3D 8, + }, + [VCAP_KF_L3_PAYLOAD] =3D { + .type =3D VCAP_FIELD_U112, + .offset =3D 182, + .width =3D 96, + }, +}; + +static const struct vcap_field es2_ip_7tuple_keyfield[] =3D { + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 0, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 10, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 11, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 12, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 13, + .width =3D 10, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 23, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 25, + .width =3D 13, + }, + [VCAP_KF_IF_EGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 38, + .width =3D 3, + }, + [VCAP_KF_IF_EGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 41, + .width =3D 32, + }, + [VCAP_KF_IF_IGR_PORT_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 73, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 74, + .width =3D 7, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 81, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 84, + .width =3D 1, + }, + [VCAP_KF_COSID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 85, + .width =3D 3, + }, + [VCAP_KF_L3_DPL_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 88, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 89, + .width =3D 1, + }, + [VCAP_KF_L2_DMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 93, + .width =3D 48, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 141, + .width =3D 48, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 191, + .width =3D 1, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 192, + .width =3D 1, + }, + [VCAP_KF_L3_TOS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 193, + .width =3D 8, + }, + [VCAP_KF_L3_IP6_DIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 201, + .width =3D 128, + }, + [VCAP_KF_L3_IP6_SIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 329, + .width =3D 128, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 457, + .width =3D 1, + }, + [VCAP_KF_TCP_UDP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 458, + .width =3D 1, + }, + [VCAP_KF_TCP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 459, + .width =3D 1, + }, + [VCAP_KF_L4_DPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 460, + .width =3D 16, + }, + [VCAP_KF_L4_SPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 476, + .width =3D 16, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 492, + .width =3D 16, + }, + [VCAP_KF_L4_SPORT_EQ_DPORT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 508, + .width =3D 1, + }, + [VCAP_KF_L4_SEQUENCE_EQ0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 509, + .width =3D 1, + }, + [VCAP_KF_L4_FIN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 510, + .width =3D 1, + }, + [VCAP_KF_L4_SYN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 511, + .width =3D 1, + }, + [VCAP_KF_L4_RST] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 512, + .width =3D 1, + }, + [VCAP_KF_L4_PSH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 513, + .width =3D 1, + }, + [VCAP_KF_L4_ACK] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 514, + .width =3D 1, + }, + [VCAP_KF_L4_URG] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 515, + .width =3D 1, + }, + [VCAP_KF_L4_PAYLOAD] =3D { + .type =3D VCAP_FIELD_U64, + .offset =3D 516, + .width =3D 64, + }, +}; + +static const struct vcap_field es2_ip6_std_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 3, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 3, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 14, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 15, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 16, + .width =3D 10, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 26, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 28, + .width =3D 13, + }, + [VCAP_KF_IF_EGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 41, + .width =3D 3, + }, + [VCAP_KF_IF_EGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 44, + .width =3D 32, + }, + [VCAP_KF_IF_IGR_PORT_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 76, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 77, + .width =3D 7, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 84, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 87, + .width =3D 1, + }, + [VCAP_KF_COSID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 88, + .width =3D 3, + }, + [VCAP_KF_L3_DPL_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 91, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 92, + .width =3D 1, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 96, + .width =3D 1, + }, + [VCAP_KF_L3_IP6_SIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 97, + .width =3D 128, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 225, + .width =3D 1, + }, + [VCAP_KF_L3_IP_PROTO] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 226, + .width =3D 8, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 234, + .width =3D 16, + }, + [VCAP_KF_L3_PAYLOAD] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 250, + .width =3D 40, + }, +}; + +/* keyfield_set */ +static const struct vcap_set is0_keyfield_set[] =3D { + [VCAP_KFS_NORMAL_7TUPLE] =3D { + .type_id =3D 0, + .sw_per_item =3D 12, + .sw_cnt =3D 1, + }, + [VCAP_KFS_NORMAL_5TUPLE_IP4] =3D { + .type_id =3D 2, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, +}; + +static const struct vcap_set is2_keyfield_set[] =3D { + [VCAP_KFS_MAC_ETYPE] =3D { + .type_id =3D 0, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_ARP] =3D { + .type_id =3D 3, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_IP4_TCP_UDP] =3D { + .type_id =3D 4, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_IP4_OTHER] =3D { + .type_id =3D 5, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_IP6_STD] =3D { + .type_id =3D 6, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_IP_7TUPLE] =3D { + .type_id =3D 1, + .sw_per_item =3D 12, + .sw_cnt =3D 1, + }, +}; + +static const struct vcap_set es0_keyfield_set[] =3D { + [VCAP_KFS_ISDX] =3D { + .type_id =3D 0, + .sw_per_item =3D 1, + .sw_cnt =3D 1, + }, +}; + +static const struct vcap_set es2_keyfield_set[] =3D { + [VCAP_KFS_MAC_ETYPE] =3D { + .type_id =3D 0, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_ARP] =3D { + .type_id =3D 1, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_IP4_TCP_UDP] =3D { + .type_id =3D 2, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_IP4_OTHER] =3D { + .type_id =3D 3, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_IP_7TUPLE] =3D { + .type_id =3D -1, + .sw_per_item =3D 12, + .sw_cnt =3D 1, + }, + [VCAP_KFS_IP6_STD] =3D { + .type_id =3D 4, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, +}; + +/* keyfield_set map */ +static const struct vcap_field *is0_keyfield_set_map[] =3D { + [VCAP_KFS_NORMAL_7TUPLE] =3D is0_normal_7tuple_keyfield, + [VCAP_KFS_NORMAL_5TUPLE_IP4] =3D is0_normal_5tuple_ip4_keyfield, +}; + +static const struct vcap_field *is2_keyfield_set_map[] =3D { + [VCAP_KFS_MAC_ETYPE] =3D is2_mac_etype_keyfield, + [VCAP_KFS_ARP] =3D is2_arp_keyfield, + [VCAP_KFS_IP4_TCP_UDP] =3D is2_ip4_tcp_udp_keyfield, + [VCAP_KFS_IP4_OTHER] =3D is2_ip4_other_keyfield, + [VCAP_KFS_IP6_STD] =3D is2_ip6_std_keyfield, + [VCAP_KFS_IP_7TUPLE] =3D is2_ip_7tuple_keyfield, +}; + +static const struct vcap_field *es0_keyfield_set_map[] =3D { + [VCAP_KFS_ISDX] =3D es0_isdx_keyfield, +}; + +static const struct vcap_field *es2_keyfield_set_map[] =3D { + [VCAP_KFS_MAC_ETYPE] =3D es2_mac_etype_keyfield, + [VCAP_KFS_ARP] =3D es2_arp_keyfield, + [VCAP_KFS_IP4_TCP_UDP] =3D es2_ip4_tcp_udp_keyfield, + [VCAP_KFS_IP4_OTHER] =3D es2_ip4_other_keyfield, + [VCAP_KFS_IP_7TUPLE] =3D es2_ip_7tuple_keyfield, + [VCAP_KFS_IP6_STD] =3D es2_ip6_std_keyfield, +}; + +/* keyfield_set map sizes */ +static int is0_keyfield_set_map_size[] =3D { + [VCAP_KFS_NORMAL_7TUPLE] =3D ARRAY_SIZE(is0_normal_7tuple_keyfield), + [VCAP_KFS_NORMAL_5TUPLE_IP4] =3D ARRAY_SIZE(is0_normal_5tuple_ip4_keyfiel= d), +}; + +static int is2_keyfield_set_map_size[] =3D { + [VCAP_KFS_MAC_ETYPE] =3D ARRAY_SIZE(is2_mac_etype_keyfield), + [VCAP_KFS_ARP] =3D ARRAY_SIZE(is2_arp_keyfield), + [VCAP_KFS_IP4_TCP_UDP] =3D ARRAY_SIZE(is2_ip4_tcp_udp_keyfield), + [VCAP_KFS_IP4_OTHER] =3D ARRAY_SIZE(is2_ip4_other_keyfield), + [VCAP_KFS_IP6_STD] =3D ARRAY_SIZE(is2_ip6_std_keyfield), + [VCAP_KFS_IP_7TUPLE] =3D ARRAY_SIZE(is2_ip_7tuple_keyfield), +}; + +static int es0_keyfield_set_map_size[] =3D { + [VCAP_KFS_ISDX] =3D ARRAY_SIZE(es0_isdx_keyfield), +}; + +static int es2_keyfield_set_map_size[] =3D { + [VCAP_KFS_MAC_ETYPE] =3D ARRAY_SIZE(es2_mac_etype_keyfield), + [VCAP_KFS_ARP] =3D ARRAY_SIZE(es2_arp_keyfield), + [VCAP_KFS_IP4_TCP_UDP] =3D ARRAY_SIZE(es2_ip4_tcp_udp_keyfield), + [VCAP_KFS_IP4_OTHER] =3D ARRAY_SIZE(es2_ip4_other_keyfield), + [VCAP_KFS_IP_7TUPLE] =3D ARRAY_SIZE(es2_ip_7tuple_keyfield), + [VCAP_KFS_IP6_STD] =3D ARRAY_SIZE(es2_ip6_std_keyfield), +}; + +/* actionfields */ +static const struct vcap_field is0_classification_actionfield[] =3D { + [VCAP_AF_TYPE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 0, + .width =3D 1, + }, + [VCAP_AF_DSCP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 1, + .width =3D 1, + }, + [VCAP_AF_DSCP_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 2, + .width =3D 6, + }, + [VCAP_AF_QOS_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 12, + .width =3D 1, + }, + [VCAP_AF_QOS_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 13, + .width =3D 3, + }, + [VCAP_AF_DP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 16, + .width =3D 1, + }, + [VCAP_AF_DP_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 17, + .width =3D 2, + }, + [VCAP_AF_DEI_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 19, + .width =3D 1, + }, + [VCAP_AF_DEI_VAL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 20, + .width =3D 1, + }, + [VCAP_AF_PCP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 21, + .width =3D 1, + }, + [VCAP_AF_PCP_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 22, + .width =3D 3, + }, + [VCAP_AF_MAP_LOOKUP_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 25, + .width =3D 2, + }, + [VCAP_AF_MAP_KEY] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 27, + .width =3D 3, + }, + [VCAP_AF_MAP_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 30, + .width =3D 7, + }, + [VCAP_AF_CLS_VID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 37, + .width =3D 3, + }, + [VCAP_AF_VID_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 43, + .width =3D 13, + }, + [VCAP_AF_ISDX_ADD_REPLACE_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 66, + .width =3D 1, + }, + [VCAP_AF_ISDX_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 67, + .width =3D 10, + }, + [VCAP_AF_PAG_OVERRIDE_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 107, + .width =3D 8, + }, + [VCAP_AF_PAG_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 115, + .width =3D 8, + }, + [VCAP_AF_NXT_IDX_CTRL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 167, + .width =3D 3, + }, + [VCAP_AF_NXT_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 170, + .width =3D 10, + }, +}; + +static const struct vcap_field is0_full_actionfield[] =3D { + [VCAP_AF_DSCP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 0, + .width =3D 1, + }, + [VCAP_AF_DSCP_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 1, + .width =3D 6, + }, + [VCAP_AF_QOS_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 11, + .width =3D 1, + }, + [VCAP_AF_QOS_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 12, + .width =3D 3, + }, + [VCAP_AF_DP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 15, + .width =3D 1, + }, + [VCAP_AF_DP_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 16, + .width =3D 2, + }, + [VCAP_AF_DEI_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 18, + .width =3D 1, + }, + [VCAP_AF_DEI_VAL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 19, + .width =3D 1, + }, + [VCAP_AF_PCP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 20, + .width =3D 1, + }, + [VCAP_AF_PCP_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 21, + .width =3D 3, + }, + [VCAP_AF_MAP_LOOKUP_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 24, + .width =3D 2, + }, + [VCAP_AF_MAP_KEY] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 26, + .width =3D 3, + }, + [VCAP_AF_MAP_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 29, + .width =3D 7, + }, + [VCAP_AF_CLS_VID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 36, + .width =3D 3, + }, + [VCAP_AF_VID_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 42, + .width =3D 13, + }, + [VCAP_AF_ISDX_ADD_REPLACE_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 65, + .width =3D 1, + }, + [VCAP_AF_ISDX_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 66, + .width =3D 10, + }, + [VCAP_AF_MASK_MODE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 76, + .width =3D 3, + }, + [VCAP_AF_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 79, + .width =3D 37, + }, + [VCAP_AF_PAG_OVERRIDE_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 174, + .width =3D 8, + }, + [VCAP_AF_PAG_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 182, + .width =3D 8, + }, + [VCAP_AF_NXT_IDX_CTRL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 266, + .width =3D 3, + }, + [VCAP_AF_NXT_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 269, + .width =3D 10, + }, +}; + +static const struct vcap_field is0_class_reduced_actionfield[] =3D { + [VCAP_AF_TYPE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 0, + .width =3D 1, + }, + [VCAP_AF_QOS_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 5, + .width =3D 1, + }, + [VCAP_AF_QOS_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 6, + .width =3D 3, + }, + [VCAP_AF_DP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 9, + .width =3D 1, + }, + [VCAP_AF_DP_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 10, + .width =3D 2, + }, + [VCAP_AF_MAP_LOOKUP_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 12, + .width =3D 2, + }, + [VCAP_AF_MAP_KEY] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 14, + .width =3D 3, + }, + [VCAP_AF_CLS_VID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 17, + .width =3D 3, + }, + [VCAP_AF_VID_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 23, + .width =3D 13, + }, + [VCAP_AF_ISDX_ADD_REPLACE_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 46, + .width =3D 1, + }, + [VCAP_AF_ISDX_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 47, + .width =3D 10, + }, + [VCAP_AF_NXT_IDX_CTRL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 89, + .width =3D 3, + }, + [VCAP_AF_NXT_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 92, + .width =3D 10, + }, +}; + +static const struct vcap_field is2_base_type_actionfield[] =3D { + [VCAP_AF_PIPELINE_FORCE_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 1, + .width =3D 1, + }, + [VCAP_AF_PIPELINE_PT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 2, + .width =3D 5, + }, + [VCAP_AF_HIT_ME_ONCE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 7, + .width =3D 1, + }, + [VCAP_AF_INTR_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 8, + .width =3D 1, + }, + [VCAP_AF_CPU_COPY_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 9, + .width =3D 1, + }, + [VCAP_AF_CPU_QUEUE_NUM] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 10, + .width =3D 3, + }, + [VCAP_AF_LRN_DIS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 15, + .width =3D 1, + }, + [VCAP_AF_RT_DIS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 16, + .width =3D 1, + }, + [VCAP_AF_POLICE_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 17, + .width =3D 1, + }, + [VCAP_AF_POLICE_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 18, + .width =3D 5, + }, + [VCAP_AF_IGNORE_PIPELINE_CTRL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 23, + .width =3D 1, + }, + [VCAP_AF_MASK_MODE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 27, + .width =3D 3, + }, + [VCAP_AF_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 30, + .width =3D 37, + }, + [VCAP_AF_MIRROR_PROBE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 78, + .width =3D 2, + }, + [VCAP_AF_MATCH_ID] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 131, + .width =3D 16, + }, + [VCAP_AF_MATCH_ID_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 147, + .width =3D 16, + }, + [VCAP_AF_CNT_ID] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 163, + .width =3D 10, + }, +}; + +static const struct vcap_field es0_es0_actionfield[] =3D { + [VCAP_AF_PUSH_OUTER_TAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 2, + }, + [VCAP_AF_PUSH_INNER_TAG] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 2, + .width =3D 1, + }, + [VCAP_AF_TAG_A_TPID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 3, + .width =3D 3, + }, + [VCAP_AF_TAG_A_VID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 6, + .width =3D 2, + }, + [VCAP_AF_TAG_A_PCP_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 8, + .width =3D 3, + }, + [VCAP_AF_TAG_A_DEI_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 11, + .width =3D 3, + }, + [VCAP_AF_TAG_B_TPID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 14, + .width =3D 3, + }, + [VCAP_AF_TAG_B_VID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 17, + .width =3D 2, + }, + [VCAP_AF_TAG_B_PCP_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 19, + .width =3D 3, + }, + [VCAP_AF_TAG_B_DEI_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 22, + .width =3D 3, + }, + [VCAP_AF_TAG_C_TPID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 25, + .width =3D 3, + }, + [VCAP_AF_TAG_C_PCP_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 28, + .width =3D 3, + }, + [VCAP_AF_TAG_C_DEI_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 31, + .width =3D 3, + }, + [VCAP_AF_VID_A_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 34, + .width =3D 12, + }, + [VCAP_AF_PCP_A_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 46, + .width =3D 3, + }, + [VCAP_AF_DEI_A_VAL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 49, + .width =3D 1, + }, + [VCAP_AF_VID_B_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 50, + .width =3D 12, + }, + [VCAP_AF_PCP_B_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 62, + .width =3D 3, + }, + [VCAP_AF_DEI_B_VAL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 65, + .width =3D 1, + }, + [VCAP_AF_VID_C_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 66, + .width =3D 12, + }, + [VCAP_AF_PCP_C_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 78, + .width =3D 3, + }, + [VCAP_AF_DEI_C_VAL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 81, + .width =3D 1, + }, + [VCAP_AF_POP_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 82, + .width =3D 2, + }, + [VCAP_AF_UNTAG_VID_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 84, + .width =3D 1, + }, + [VCAP_AF_PUSH_CUSTOMER_TAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 85, + .width =3D 2, + }, + [VCAP_AF_TAG_C_VID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 87, + .width =3D 2, + }, + [VCAP_AF_DSCP_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 127, + .width =3D 3, + }, + [VCAP_AF_DSCP_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 130, + .width =3D 6, + }, + [VCAP_AF_ESDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 319, + .width =3D 10, + }, + [VCAP_AF_FWD_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 438, + .width =3D 2, + }, + [VCAP_AF_CPU_QU] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 440, + .width =3D 3, + }, + [VCAP_AF_PIPELINE_PT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 443, + .width =3D 2, + }, + [VCAP_AF_PIPELINE_ACT] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 445, + .width =3D 1, + }, + [VCAP_AF_SWAP_MACS_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 454, + .width =3D 1, + }, + [VCAP_AF_LOOP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 455, + .width =3D 1, + }, +}; + +static const struct vcap_field es2_base_type_actionfield[] =3D { + [VCAP_AF_HIT_ME_ONCE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 0, + .width =3D 1, + }, + [VCAP_AF_INTR_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 1, + .width =3D 1, + }, + [VCAP_AF_FWD_MODE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 2, + .width =3D 2, + }, + [VCAP_AF_COPY_QUEUE_NUM] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 4, + .width =3D 14, + }, + [VCAP_AF_COPY_PORT_NUM] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 18, + .width =3D 6, + }, + [VCAP_AF_MIRROR_PROBE_ID] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 24, + .width =3D 2, + }, + [VCAP_AF_CPU_COPY_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 26, + .width =3D 1, + }, + [VCAP_AF_CPU_QUEUE_NUM] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 27, + .width =3D 3, + }, + [VCAP_AF_POLICE_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 30, + .width =3D 1, + }, + [VCAP_AF_POLICE_REMARK] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 31, + .width =3D 1, + }, + [VCAP_AF_POLICE_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 32, + .width =3D 5, + }, + [VCAP_AF_ES2_REW_CMD] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 37, + .width =3D 3, + }, + [VCAP_AF_CNT_ID] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 40, + .width =3D 9, + }, + [VCAP_AF_IGNORE_PIPELINE_CTRL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 49, + .width =3D 1, + }, +}; + +/* actionfield_set */ +static const struct vcap_set is0_actionfield_set[] =3D { + [VCAP_AFS_CLASSIFICATION] =3D { + .type_id =3D 1, + .sw_per_item =3D 2, + .sw_cnt =3D 6, + }, + [VCAP_AFS_FULL] =3D { + .type_id =3D -1, + .sw_per_item =3D 3, + .sw_cnt =3D 4, + }, + [VCAP_AFS_CLASS_REDUCED] =3D { + .type_id =3D 1, + .sw_per_item =3D 1, + .sw_cnt =3D 12, + }, +}; + +static const struct vcap_set is2_actionfield_set[] =3D { + [VCAP_AFS_BASE_TYPE] =3D { + .type_id =3D -1, + .sw_per_item =3D 3, + .sw_cnt =3D 4, + }, +}; + +static const struct vcap_set es0_actionfield_set[] =3D { + [VCAP_AFS_ES0] =3D { + .type_id =3D -1, + .sw_per_item =3D 1, + .sw_cnt =3D 1, + }, +}; + +static const struct vcap_set es2_actionfield_set[] =3D { + [VCAP_AFS_BASE_TYPE] =3D { + .type_id =3D -1, + .sw_per_item =3D 3, + .sw_cnt =3D 4, + }, +}; + +/* actionfield_set map */ +static const struct vcap_field *is0_actionfield_set_map[] =3D { + [VCAP_AFS_CLASSIFICATION] =3D is0_classification_actionfield, + [VCAP_AFS_FULL] =3D is0_full_actionfield, + [VCAP_AFS_CLASS_REDUCED] =3D is0_class_reduced_actionfield, +}; + +static const struct vcap_field *is2_actionfield_set_map[] =3D { + [VCAP_AFS_BASE_TYPE] =3D is2_base_type_actionfield, +}; + +static const struct vcap_field *es0_actionfield_set_map[] =3D { + [VCAP_AFS_ES0] =3D es0_es0_actionfield, +}; + +static const struct vcap_field *es2_actionfield_set_map[] =3D { + [VCAP_AFS_BASE_TYPE] =3D es2_base_type_actionfield, +}; + +/* actionfield_set map size */ +static int is0_actionfield_set_map_size[] =3D { + [VCAP_AFS_CLASSIFICATION] =3D ARRAY_SIZE(is0_classification_actionfield), + [VCAP_AFS_FULL] =3D ARRAY_SIZE(is0_full_actionfield), + [VCAP_AFS_CLASS_REDUCED] =3D ARRAY_SIZE(is0_class_reduced_actionfield), +}; + +static int is2_actionfield_set_map_size[] =3D { + [VCAP_AFS_BASE_TYPE] =3D ARRAY_SIZE(is2_base_type_actionfield), +}; + +static int es0_actionfield_set_map_size[] =3D { + [VCAP_AFS_ES0] =3D ARRAY_SIZE(es0_es0_actionfield), +}; + +static int es2_actionfield_set_map_size[] =3D { + [VCAP_AFS_BASE_TYPE] =3D ARRAY_SIZE(es2_base_type_actionfield), +}; + +/* Type Groups */ +static const struct vcap_typegroup is0_x12_keyfield_set_typegroups[] =3D { + { + .offset =3D 0, + .width =3D 5, + .value =3D 16, + }, + { + .offset =3D 52, + .width =3D 1, + .value =3D 0, + }, + { + .offset =3D 104, + .width =3D 2, + .value =3D 0, + }, + { + .offset =3D 156, + .width =3D 3, + .value =3D 0, + }, + { + .offset =3D 208, + .width =3D 2, + .value =3D 0, + }, + { + .offset =3D 260, + .width =3D 1, + .value =3D 0, + }, + { + .offset =3D 312, + .width =3D 4, + .value =3D 0, + }, + { + .offset =3D 364, + .width =3D 1, + .value =3D 0, + }, + { + .offset =3D 416, + .width =3D 2, + .value =3D 0, + }, + { + .offset =3D 468, + .width =3D 3, + .value =3D 0, + }, + { + .offset =3D 520, + .width =3D 2, + .value =3D 0, + }, + { + .offset =3D 572, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup is0_x6_keyfield_set_typegroups[] =3D { + { + .offset =3D 0, + .width =3D 4, + .value =3D 8, + }, + { + .offset =3D 52, + .width =3D 1, + .value =3D 0, + }, + { + .offset =3D 104, + .width =3D 2, + .value =3D 0, + }, + { + .offset =3D 156, + .width =3D 3, + .value =3D 0, + }, + { + .offset =3D 208, + .width =3D 2, + .value =3D 0, + }, + { + .offset =3D 260, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup is0_x3_keyfield_set_typegroups[] =3D { + {} +}; + +static const struct vcap_typegroup is0_x2_keyfield_set_typegroups[] =3D { + {} +}; + +static const struct vcap_typegroup is0_x1_keyfield_set_typegroups[] =3D { + {} +}; + +static const struct vcap_typegroup is2_x12_keyfield_set_typegroups[] =3D { + { + .offset =3D 0, + .width =3D 3, + .value =3D 4, + }, + { + .offset =3D 156, + .width =3D 1, + .value =3D 0, + }, + { + .offset =3D 312, + .width =3D 2, + .value =3D 0, + }, + { + .offset =3D 468, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup is2_x6_keyfield_set_typegroups[] =3D { + { + .offset =3D 0, + .width =3D 2, + .value =3D 2, + }, + { + .offset =3D 156, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup is2_x3_keyfield_set_typegroups[] =3D { + {} +}; + +static const struct vcap_typegroup is2_x1_keyfield_set_typegroups[] =3D { + {} +}; + +static const struct vcap_typegroup es0_x1_keyfield_set_typegroups[] =3D { + {} +}; + +static const struct vcap_typegroup es2_x12_keyfield_set_typegroups[] =3D { + { + .offset =3D 0, + .width =3D 3, + .value =3D 4, + }, + { + .offset =3D 156, + .width =3D 1, + .value =3D 0, + }, + { + .offset =3D 312, + .width =3D 2, + .value =3D 0, + }, + { + .offset =3D 468, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup es2_x6_keyfield_set_typegroups[] =3D { + { + .offset =3D 0, + .width =3D 2, + .value =3D 2, + }, + { + .offset =3D 156, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup es2_x3_keyfield_set_typegroups[] =3D { + {} +}; + +static const struct vcap_typegroup es2_x1_keyfield_set_typegroups[] =3D { + {} +}; + +static const struct vcap_typegroup *is0_keyfield_set_typegroups[] =3D { + [12] =3D is0_x12_keyfield_set_typegroups, + [6] =3D is0_x6_keyfield_set_typegroups, + [3] =3D is0_x3_keyfield_set_typegroups, + [2] =3D is0_x2_keyfield_set_typegroups, + [1] =3D is0_x1_keyfield_set_typegroups, + [13] =3D NULL, +}; + +static const struct vcap_typegroup *is2_keyfield_set_typegroups[] =3D { + [12] =3D is2_x12_keyfield_set_typegroups, + [6] =3D is2_x6_keyfield_set_typegroups, + [3] =3D is2_x3_keyfield_set_typegroups, + [1] =3D is2_x1_keyfield_set_typegroups, + [13] =3D NULL, +}; + +static const struct vcap_typegroup *es0_keyfield_set_typegroups[] =3D { + [1] =3D es0_x1_keyfield_set_typegroups, + [2] =3D NULL, +}; + +static const struct vcap_typegroup *es2_keyfield_set_typegroups[] =3D { + [12] =3D es2_x12_keyfield_set_typegroups, + [6] =3D es2_x6_keyfield_set_typegroups, + [3] =3D es2_x3_keyfield_set_typegroups, + [1] =3D es2_x1_keyfield_set_typegroups, + [13] =3D NULL, +}; + +static const struct vcap_typegroup is0_x3_actionfield_set_typegroups[] =3D= { + { + .offset =3D 0, + .width =3D 3, + .value =3D 4, + }, + { + .offset =3D 103, + .width =3D 2, + .value =3D 0, + }, + { + .offset =3D 206, + .width =3D 2, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup is0_x2_actionfield_set_typegroups[] =3D= { + { + .offset =3D 0, + .width =3D 2, + .value =3D 2, + }, + { + .offset =3D 103, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup is0_x1_actionfield_set_typegroups[] =3D= { + { + .offset =3D 0, + .width =3D 1, + .value =3D 1, + }, + {} +}; + +static const struct vcap_typegroup is2_x3_actionfield_set_typegroups[] =3D= { + { + .offset =3D 0, + .width =3D 2, + .value =3D 2, + }, + { + .offset =3D 95, + .width =3D 1, + .value =3D 0, + }, + { + .offset =3D 190, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup is2_x1_actionfield_set_typegroups[] =3D= { + {} +}; + +static const struct vcap_typegroup es0_x1_actionfield_set_typegroups[] =3D= { + {} +}; + +static const struct vcap_typegroup es2_x3_actionfield_set_typegroups[] =3D= { + { + .offset =3D 0, + .width =3D 2, + .value =3D 2, + }, + { + .offset =3D 19, + .width =3D 1, + .value =3D 0, + }, + { + .offset =3D 38, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup es2_x1_actionfield_set_typegroups[] =3D= { + {} +}; + +static const struct vcap_typegroup *is0_actionfield_set_typegroups[] =3D { + [3] =3D is0_x3_actionfield_set_typegroups, + [2] =3D is0_x2_actionfield_set_typegroups, + [1] =3D is0_x1_actionfield_set_typegroups, + [13] =3D NULL, +}; + +static const struct vcap_typegroup *is2_actionfield_set_typegroups[] =3D { + [3] =3D is2_x3_actionfield_set_typegroups, + [1] =3D is2_x1_actionfield_set_typegroups, + [13] =3D NULL, +}; + +static const struct vcap_typegroup *es0_actionfield_set_typegroups[] =3D { + [1] =3D es0_x1_actionfield_set_typegroups, + [2] =3D NULL, +}; + +static const struct vcap_typegroup *es2_actionfield_set_typegroups[] =3D { + [3] =3D es2_x3_actionfield_set_typegroups, + [1] =3D es2_x1_actionfield_set_typegroups, + [13] =3D NULL, +}; + +/* Keyfieldset names */ +static const char * const vcap_keyfield_set_names[] =3D { + [VCAP_KFS_NO_VALUE] =3D "(None)", + [VCAP_KFS_ARP] =3D "VCAP_KFS_ARP", + [VCAP_KFS_ETAG] =3D "VCAP_KFS_ETAG", + [VCAP_KFS_IP4_OTHER] =3D "VCAP_KFS_IP4_OTHER", + [VCAP_KFS_IP4_TCP_UDP] =3D "VCAP_KFS_IP4_TCP_UDP", + [VCAP_KFS_IP4_VID] =3D "VCAP_KFS_IP4_VID", + [VCAP_KFS_IP6_OTHER] =3D "VCAP_KFS_IP6_OTHER", + [VCAP_KFS_IP6_STD] =3D "VCAP_KFS_IP6_STD", + [VCAP_KFS_IP6_TCP_UDP] =3D "VCAP_KFS_IP6_TCP_UDP", + [VCAP_KFS_IP6_VID] =3D "VCAP_KFS_IP6_VID", + [VCAP_KFS_IP_7TUPLE] =3D "VCAP_KFS_IP_7TUPLE", + [VCAP_KFS_ISDX] =3D "VCAP_KFS_ISDX", + [VCAP_KFS_LL_FULL] =3D "VCAP_KFS_LL_FULL", + [VCAP_KFS_MAC_ETYPE] =3D "VCAP_KFS_MAC_ETYPE", + [VCAP_KFS_MAC_LLC] =3D "VCAP_KFS_MAC_LLC", + [VCAP_KFS_MAC_SNAP] =3D "VCAP_KFS_MAC_SNAP", + [VCAP_KFS_NORMAL_5TUPLE_IP4] =3D "VCAP_KFS_NORMAL_5TUPLE_IP4= ", + [VCAP_KFS_NORMAL_7TUPLE] =3D "VCAP_KFS_NORMAL_7TUPLE", + [VCAP_KFS_OAM] =3D "VCAP_KFS_OAM", + [VCAP_KFS_PURE_5TUPLE_IP4] =3D "VCAP_KFS_PURE_5TUPLE_IP4", + [VCAP_KFS_SMAC_SIP4] =3D "VCAP_KFS_SMAC_SIP4", + [VCAP_KFS_SMAC_SIP6] =3D "VCAP_KFS_SMAC_SIP6", +}; + +/* Actionfieldset names */ +static const char * const vcap_actionfield_set_names[] =3D { + [VCAP_AFS_NO_VALUE] =3D "(None)", + [VCAP_AFS_BASE_TYPE] =3D "VCAP_AFS_BASE_TYPE", + [VCAP_AFS_CLASSIFICATION] =3D "VCAP_AFS_CLASSIFICATION", + [VCAP_AFS_CLASS_REDUCED] =3D "VCAP_AFS_CLASS_REDUCED", + [VCAP_AFS_ES0] =3D "VCAP_AFS_ES0", + [VCAP_AFS_FULL] =3D "VCAP_AFS_FULL", + [VCAP_AFS_SMAC_SIP] =3D "VCAP_AFS_SMAC_SIP", +}; + +/* Keyfield names */ +static const char * const vcap_keyfield_names[] =3D { + [VCAP_KF_NO_VALUE] =3D "(None)", + [VCAP_KF_8021BR_ECID_BASE] =3D "8021BR_ECID_BASE", + [VCAP_KF_8021BR_ECID_EXT] =3D "8021BR_ECID_EXT", + [VCAP_KF_8021BR_E_TAGGED] =3D "8021BR_E_TAGGED", + [VCAP_KF_8021BR_GRP] =3D "8021BR_GRP", + [VCAP_KF_8021BR_IGR_ECID_BASE] =3D "8021BR_IGR_ECID_BASE", + [VCAP_KF_8021BR_IGR_ECID_EXT] =3D "8021BR_IGR_ECID_EXT", + [VCAP_KF_8021Q_DEI0] =3D "8021Q_DEI0", + [VCAP_KF_8021Q_DEI1] =3D "8021Q_DEI1", + [VCAP_KF_8021Q_DEI2] =3D "8021Q_DEI2", + [VCAP_KF_8021Q_DEI_CLS] =3D "8021Q_DEI_CLS", + [VCAP_KF_8021Q_PCP0] =3D "8021Q_PCP0", + [VCAP_KF_8021Q_PCP1] =3D "8021Q_PCP1", + [VCAP_KF_8021Q_PCP2] =3D "8021Q_PCP2", + [VCAP_KF_8021Q_PCP_CLS] =3D "8021Q_PCP_CLS", + [VCAP_KF_8021Q_TPID] =3D "8021Q_TPID", + [VCAP_KF_8021Q_TPID0] =3D "8021Q_TPID0", + [VCAP_KF_8021Q_TPID1] =3D "8021Q_TPID1", + [VCAP_KF_8021Q_TPID2] =3D "8021Q_TPID2", + [VCAP_KF_8021Q_VID0] =3D "8021Q_VID0", + [VCAP_KF_8021Q_VID1] =3D "8021Q_VID1", + [VCAP_KF_8021Q_VID2] =3D "8021Q_VID2", + [VCAP_KF_8021Q_VID_CLS] =3D "8021Q_VID_CLS", + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D "8021Q_VLAN_TAGGED_IS", + [VCAP_KF_8021Q_VLAN_TAGS] =3D "8021Q_VLAN_TAGS", + [VCAP_KF_ACL_GRP_ID] =3D "ACL_GRP_ID", + [VCAP_KF_ARP_ADDR_SPACE_OK_IS] =3D "ARP_ADDR_SPACE_OK_IS", + [VCAP_KF_ARP_LEN_OK_IS] =3D "ARP_LEN_OK_IS", + [VCAP_KF_ARP_OPCODE] =3D "ARP_OPCODE", + [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] =3D "ARP_OPCODE_UNKNOWN_IS", + [VCAP_KF_ARP_PROTO_SPACE_OK_IS] =3D "ARP_PROTO_SPACE_OK_IS", + [VCAP_KF_ARP_SENDER_MATCH_IS] =3D "ARP_SENDER_MATCH_IS", + [VCAP_KF_ARP_TGT_MATCH_IS] =3D "ARP_TGT_MATCH_IS", + [VCAP_KF_COSID_CLS] =3D "COSID_CLS", + [VCAP_KF_ES0_ISDX_KEY_ENA] =3D "ES0_ISDX_KEY_ENA", + [VCAP_KF_ETYPE] =3D "ETYPE", + [VCAP_KF_ETYPE_LEN_IS] =3D "ETYPE_LEN_IS", + [VCAP_KF_HOST_MATCH] =3D "HOST_MATCH", + [VCAP_KF_IF_EGR_PORT_MASK] =3D "IF_EGR_PORT_MASK", + [VCAP_KF_IF_EGR_PORT_MASK_RNG] =3D "IF_EGR_PORT_MASK_RNG", + [VCAP_KF_IF_EGR_PORT_NO] =3D "IF_EGR_PORT_NO", + [VCAP_KF_IF_IGR_PORT] =3D "IF_IGR_PORT", + [VCAP_KF_IF_IGR_PORT_MASK] =3D "IF_IGR_PORT_MASK", + [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D "IF_IGR_PORT_MASK_L3", + [VCAP_KF_IF_IGR_PORT_MASK_RNG] =3D "IF_IGR_PORT_MASK_RNG", + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D "IF_IGR_PORT_MASK_SEL", + [VCAP_KF_IF_IGR_PORT_SEL] =3D "IF_IGR_PORT_SEL", + [VCAP_KF_IP4_IS] =3D "IP4_IS", + [VCAP_KF_IP_MC_IS] =3D "IP_MC_IS", + [VCAP_KF_IP_PAYLOAD_5TUPLE] =3D "IP_PAYLOAD_5TUPLE", + [VCAP_KF_IP_SNAP_IS] =3D "IP_SNAP_IS", + [VCAP_KF_ISDX_CLS] =3D "ISDX_CLS", + [VCAP_KF_ISDX_GT0_IS] =3D "ISDX_GT0_IS", + [VCAP_KF_L2_BC_IS] =3D "L2_BC_IS", + [VCAP_KF_L2_DMAC] =3D "L2_DMAC", + [VCAP_KF_L2_FRM_TYPE] =3D "L2_FRM_TYPE", + [VCAP_KF_L2_FWD_IS] =3D "L2_FWD_IS", + [VCAP_KF_L2_LLC] =3D "L2_LLC", + [VCAP_KF_L2_MC_IS] =3D "L2_MC_IS", + [VCAP_KF_L2_PAYLOAD0] =3D "L2_PAYLOAD0", + [VCAP_KF_L2_PAYLOAD1] =3D "L2_PAYLOAD1", + [VCAP_KF_L2_PAYLOAD2] =3D "L2_PAYLOAD2", + [VCAP_KF_L2_PAYLOAD_ETYPE] =3D "L2_PAYLOAD_ETYPE", + [VCAP_KF_L2_SMAC] =3D "L2_SMAC", + [VCAP_KF_L2_SNAP] =3D "L2_SNAP", + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D "L3_DIP_EQ_SIP_IS", + [VCAP_KF_L3_DPL_CLS] =3D "L3_DPL_CLS", + [VCAP_KF_L3_DSCP] =3D "L3_DSCP", + [VCAP_KF_L3_DST_IS] =3D "L3_DST_IS", + [VCAP_KF_L3_FRAGMENT] =3D "L3_FRAGMENT", + [VCAP_KF_L3_FRAGMENT_TYPE] =3D "L3_FRAGMENT_TYPE", + [VCAP_KF_L3_FRAG_INVLD_L4_LEN] =3D "L3_FRAG_INVLD_L4_LEN", + [VCAP_KF_L3_FRAG_OFS_GT0] =3D "L3_FRAG_OFS_GT0", + [VCAP_KF_L3_IP4_DIP] =3D "L3_IP4_DIP", + [VCAP_KF_L3_IP4_SIP] =3D "L3_IP4_SIP", + [VCAP_KF_L3_IP6_DIP] =3D "L3_IP6_DIP", + [VCAP_KF_L3_IP6_SIP] =3D "L3_IP6_SIP", + [VCAP_KF_L3_IP_PROTO] =3D "L3_IP_PROTO", + [VCAP_KF_L3_OPTIONS_IS] =3D "L3_OPTIONS_IS", + [VCAP_KF_L3_PAYLOAD] =3D "L3_PAYLOAD", + [VCAP_KF_L3_RT_IS] =3D "L3_RT_IS", + [VCAP_KF_L3_TOS] =3D "L3_TOS", + [VCAP_KF_L3_TTL_GT0] =3D "L3_TTL_GT0", + [VCAP_KF_L4_1588_DOM] =3D "L4_1588_DOM", + [VCAP_KF_L4_1588_VER] =3D "L4_1588_VER", + [VCAP_KF_L4_ACK] =3D "L4_ACK", + [VCAP_KF_L4_DPORT] =3D "L4_DPORT", + [VCAP_KF_L4_FIN] =3D "L4_FIN", + [VCAP_KF_L4_PAYLOAD] =3D "L4_PAYLOAD", + [VCAP_KF_L4_PSH] =3D "L4_PSH", + [VCAP_KF_L4_RNG] =3D "L4_RNG", + [VCAP_KF_L4_RST] =3D "L4_RST", + [VCAP_KF_L4_SEQUENCE_EQ0_IS] =3D "L4_SEQUENCE_EQ0_IS", + [VCAP_KF_L4_SPORT] =3D "L4_SPORT", + [VCAP_KF_L4_SPORT_EQ_DPORT_IS] =3D "L4_SPORT_EQ_DPORT_IS", + [VCAP_KF_L4_SYN] =3D "L4_SYN", + [VCAP_KF_L4_URG] =3D "L4_URG", + [VCAP_KF_LOOKUP_FIRST_IS] =3D "LOOKUP_FIRST_IS", + [VCAP_KF_LOOKUP_GEN_IDX] =3D "LOOKUP_GEN_IDX", + [VCAP_KF_LOOKUP_GEN_IDX_SEL] =3D "LOOKUP_GEN_IDX_SEL", + [VCAP_KF_LOOKUP_PAG] =3D "LOOKUP_PAG", + [VCAP_KF_MIRROR_PROBE] =3D "MIRROR_PROBE", + [VCAP_KF_OAM_CCM_CNTS_EQ0] =3D "OAM_CCM_CNTS_EQ0", + [VCAP_KF_OAM_DETECTED] =3D "OAM_DETECTED", + [VCAP_KF_OAM_FLAGS] =3D "OAM_FLAGS", + [VCAP_KF_OAM_MEL_FLAGS] =3D "OAM_MEL_FLAGS", + [VCAP_KF_OAM_MEPID] =3D "OAM_MEPID", + [VCAP_KF_OAM_OPCODE] =3D "OAM_OPCODE", + [VCAP_KF_OAM_VER] =3D "OAM_VER", + [VCAP_KF_OAM_Y1731_IS] =3D "OAM_Y1731_IS", + [VCAP_KF_PROT_ACTIVE] =3D "PROT_ACTIVE", + [VCAP_KF_TCP_IS] =3D "TCP_IS", + [VCAP_KF_TCP_UDP_IS] =3D "TCP_UDP_IS", + [VCAP_KF_TYPE] =3D "TYPE", +}; + +/* Actionfield names */ +static const char * const vcap_actionfield_names[] =3D { + [VCAP_AF_NO_VALUE] =3D "(None)", + [VCAP_AF_ACL_ID] =3D "ACL_ID", + [VCAP_AF_CLS_VID_SEL] =3D "CLS_VID_SEL", + [VCAP_AF_CNT_ID] =3D "CNT_ID", + [VCAP_AF_COPY_PORT_NUM] =3D "COPY_PORT_NUM", + [VCAP_AF_COPY_QUEUE_NUM] =3D "COPY_QUEUE_NUM", + [VCAP_AF_CPU_COPY_ENA] =3D "CPU_COPY_ENA", + [VCAP_AF_CPU_QU] =3D "CPU_QU", + [VCAP_AF_CPU_QUEUE_NUM] =3D "CPU_QUEUE_NUM", + [VCAP_AF_DEI_A_VAL] =3D "DEI_A_VAL", + [VCAP_AF_DEI_B_VAL] =3D "DEI_B_VAL", + [VCAP_AF_DEI_C_VAL] =3D "DEI_C_VAL", + [VCAP_AF_DEI_ENA] =3D "DEI_ENA", + [VCAP_AF_DEI_VAL] =3D "DEI_VAL", + [VCAP_AF_DP_ENA] =3D "DP_ENA", + [VCAP_AF_DP_VAL] =3D "DP_VAL", + [VCAP_AF_DSCP_ENA] =3D "DSCP_ENA", + [VCAP_AF_DSCP_SEL] =3D "DSCP_SEL", + [VCAP_AF_DSCP_VAL] =3D "DSCP_VAL", + [VCAP_AF_ES2_REW_CMD] =3D "ES2_REW_CMD", + [VCAP_AF_ESDX] =3D "ESDX", + [VCAP_AF_FWD_KILL_ENA] =3D "FWD_KILL_ENA", + [VCAP_AF_FWD_MODE] =3D "FWD_MODE", + [VCAP_AF_FWD_SEL] =3D "FWD_SEL", + [VCAP_AF_HIT_ME_ONCE] =3D "HIT_ME_ONCE", + [VCAP_AF_HOST_MATCH] =3D "HOST_MATCH", + [VCAP_AF_IGNORE_PIPELINE_CTRL] =3D "IGNORE_PIPELINE_CTRL", + [VCAP_AF_INTR_ENA] =3D "INTR_ENA", + [VCAP_AF_ISDX_ADD_REPLACE_SEL] =3D "ISDX_ADD_REPLACE_SEL", + [VCAP_AF_ISDX_ENA] =3D "ISDX_ENA", + [VCAP_AF_ISDX_VAL] =3D "ISDX_VAL", + [VCAP_AF_LOOP_ENA] =3D "LOOP_ENA", + [VCAP_AF_LRN_DIS] =3D "LRN_DIS", + [VCAP_AF_MAP_IDX] =3D "MAP_IDX", + [VCAP_AF_MAP_KEY] =3D "MAP_KEY", + [VCAP_AF_MAP_LOOKUP_SEL] =3D "MAP_LOOKUP_SEL", + [VCAP_AF_MASK_MODE] =3D "MASK_MODE", + [VCAP_AF_MATCH_ID] =3D "MATCH_ID", + [VCAP_AF_MATCH_ID_MASK] =3D "MATCH_ID_MASK", + [VCAP_AF_MIRROR_ENA] =3D "MIRROR_ENA", + [VCAP_AF_MIRROR_PROBE] =3D "MIRROR_PROBE", + [VCAP_AF_MIRROR_PROBE_ID] =3D "MIRROR_PROBE_ID", + [VCAP_AF_NXT_IDX] =3D "NXT_IDX", + [VCAP_AF_NXT_IDX_CTRL] =3D "NXT_IDX_CTRL", + [VCAP_AF_PAG_OVERRIDE_MASK] =3D "PAG_OVERRIDE_MASK", + [VCAP_AF_PAG_VAL] =3D "PAG_VAL", + [VCAP_AF_PCP_A_VAL] =3D "PCP_A_VAL", + [VCAP_AF_PCP_B_VAL] =3D "PCP_B_VAL", + [VCAP_AF_PCP_C_VAL] =3D "PCP_C_VAL", + [VCAP_AF_PCP_ENA] =3D "PCP_ENA", + [VCAP_AF_PCP_VAL] =3D "PCP_VAL", + [VCAP_AF_PIPELINE_ACT] =3D "PIPELINE_ACT", + [VCAP_AF_PIPELINE_FORCE_ENA] =3D "PIPELINE_FORCE_ENA", + [VCAP_AF_PIPELINE_PT] =3D "PIPELINE_PT", + [VCAP_AF_POLICE_ENA] =3D "POLICE_ENA", + [VCAP_AF_POLICE_IDX] =3D "POLICE_IDX", + [VCAP_AF_POLICE_REMARK] =3D "POLICE_REMARK", + [VCAP_AF_POLICE_VCAP_ONLY] =3D "POLICE_VCAP_ONLY", + [VCAP_AF_POP_VAL] =3D "POP_VAL", + [VCAP_AF_PORT_MASK] =3D "PORT_MASK", + [VCAP_AF_PUSH_CUSTOMER_TAG] =3D "PUSH_CUSTOMER_TAG", + [VCAP_AF_PUSH_INNER_TAG] =3D "PUSH_INNER_TAG", + [VCAP_AF_PUSH_OUTER_TAG] =3D "PUSH_OUTER_TAG", + [VCAP_AF_QOS_ENA] =3D "QOS_ENA", + [VCAP_AF_QOS_VAL] =3D "QOS_VAL", + [VCAP_AF_REW_OP] =3D "REW_OP", + [VCAP_AF_RT_DIS] =3D "RT_DIS", + [VCAP_AF_SWAP_MACS_ENA] =3D "SWAP_MACS_ENA", + [VCAP_AF_TAG_A_DEI_SEL] =3D "TAG_A_DEI_SEL", + [VCAP_AF_TAG_A_PCP_SEL] =3D "TAG_A_PCP_SEL", + [VCAP_AF_TAG_A_TPID_SEL] =3D "TAG_A_TPID_SEL", + [VCAP_AF_TAG_A_VID_SEL] =3D "TAG_A_VID_SEL", + [VCAP_AF_TAG_B_DEI_SEL] =3D "TAG_B_DEI_SEL", + [VCAP_AF_TAG_B_PCP_SEL] =3D "TAG_B_PCP_SEL", + [VCAP_AF_TAG_B_TPID_SEL] =3D "TAG_B_TPID_SEL", + [VCAP_AF_TAG_B_VID_SEL] =3D "TAG_B_VID_SEL", + [VCAP_AF_TAG_C_DEI_SEL] =3D "TAG_C_DEI_SEL", + [VCAP_AF_TAG_C_PCP_SEL] =3D "TAG_C_PCP_SEL", + [VCAP_AF_TAG_C_TPID_SEL] =3D "TAG_C_TPID_SEL", + [VCAP_AF_TAG_C_VID_SEL] =3D "TAG_C_VID_SEL", + [VCAP_AF_TYPE] =3D "TYPE", + [VCAP_AF_UNTAG_VID_ENA] =3D "UNTAG_VID_ENA", + [VCAP_AF_VID_A_VAL] =3D "VID_A_VAL", + [VCAP_AF_VID_B_VAL] =3D "VID_B_VAL", + [VCAP_AF_VID_C_VAL] =3D "VID_C_VAL", + [VCAP_AF_VID_VAL] =3D "VID_VAL", +}; + +/* VCAPs */ +const struct vcap_info lan969x_vcaps[] =3D { + [VCAP_TYPE_IS0] =3D { + .name =3D "is0", + .rows =3D 256, + .sw_count =3D 12, + .sw_width =3D 52, + .sticky_width =3D 1, + .act_width =3D 103, + .default_cnt =3D 70, + .require_cnt_dis =3D 0, + .version =3D 1, + .keyfield_set =3D is0_keyfield_set, + .keyfield_set_size =3D ARRAY_SIZE(is0_keyfield_set), + .actionfield_set =3D is0_actionfield_set, + .actionfield_set_size =3D ARRAY_SIZE(is0_actionfield_set), + .keyfield_set_map =3D is0_keyfield_set_map, + .keyfield_set_map_size =3D is0_keyfield_set_map_size, + .actionfield_set_map =3D is0_actionfield_set_map, + .actionfield_set_map_size =3D is0_actionfield_set_map_size, + .keyfield_set_typegroups =3D is0_keyfield_set_typegroups, + .actionfield_set_typegroups =3D is0_actionfield_set_typegroups, + }, + [VCAP_TYPE_IS2] =3D { + .name =3D "is2", + .rows =3D 256, + .sw_count =3D 12, + .sw_width =3D 52, + .sticky_width =3D 1, + .act_width =3D 103, + .default_cnt =3D 38, + .require_cnt_dis =3D 0, + .version =3D 1, + .keyfield_set =3D is2_keyfield_set, + .keyfield_set_size =3D ARRAY_SIZE(is2_keyfield_set), + .actionfield_set =3D is2_actionfield_set, + .actionfield_set_size =3D ARRAY_SIZE(is2_actionfield_set), + .keyfield_set_map =3D is2_keyfield_set_map, + .keyfield_set_map_size =3D is2_keyfield_set_map_size, + .actionfield_set_map =3D is2_actionfield_set_map, + .actionfield_set_map_size =3D is2_actionfield_set_map_size, + .keyfield_set_typegroups =3D is2_keyfield_set_typegroups, + .actionfield_set_typegroups =3D is2_actionfield_set_typegroups, + }, + [VCAP_TYPE_ES0] =3D { + .name =3D "es0", + .rows =3D 1536, + .sw_count =3D 1, + .sw_width =3D 51, + .sticky_width =3D 1, + .act_width =3D 469, + .default_cnt =3D 35, + .require_cnt_dis =3D 0, + .version =3D 1, + .keyfield_set =3D es0_keyfield_set, + .keyfield_set_size =3D ARRAY_SIZE(es0_keyfield_set), + .actionfield_set =3D es0_actionfield_set, + .actionfield_set_size =3D ARRAY_SIZE(es0_actionfield_set), + .keyfield_set_map =3D es0_keyfield_set_map, + .keyfield_set_map_size =3D es0_keyfield_set_map_size, + .actionfield_set_map =3D es0_actionfield_set_map, + .actionfield_set_map_size =3D es0_actionfield_set_map_size, + .keyfield_set_typegroups =3D es0_keyfield_set_typegroups, + .actionfield_set_typegroups =3D es0_actionfield_set_typegroups, + }, + [VCAP_TYPE_ES2] =3D { + .name =3D "es2", + .rows =3D 256, + .sw_count =3D 12, + .sw_width =3D 52, + .sticky_width =3D 1, + .act_width =3D 19, + .default_cnt =3D 39, + .require_cnt_dis =3D 0, + .version =3D 1, + .keyfield_set =3D es2_keyfield_set, + .keyfield_set_size =3D ARRAY_SIZE(es2_keyfield_set), + .actionfield_set =3D es2_actionfield_set, + .actionfield_set_size =3D ARRAY_SIZE(es2_actionfield_set), + .keyfield_set_map =3D es2_keyfield_set_map, + .keyfield_set_map_size =3D es2_keyfield_set_map_size, + .actionfield_set_map =3D es2_actionfield_set_map, + .actionfield_set_map_size =3D es2_actionfield_set_map_size, + .keyfield_set_typegroups =3D es2_keyfield_set_typegroups, + .actionfield_set_typegroups =3D es2_actionfield_set_typegroups, + }, +}; + +const struct vcap_statistics lan969x_vcap_stats =3D { + .name =3D "lan969x", + .count =3D 4, + .keyfield_set_names =3D vcap_keyfield_set_names, + .actionfield_set_names =3D vcap_actionfield_set_names, + .keyfield_names =3D vcap_keyfield_names, + .actionfield_names =3D vcap_actionfield_names, +}; --=20 2.34.1