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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241101-sm8750-audio-v1-2-730aec176459@linaro.org> References: <20241101-sm8750-audio-v1-0-730aec176459@linaro.org> In-Reply-To: <20241101-sm8750-audio-v1-0-730aec176459@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Melody Olvera , Satya Durga Srinivasu Prabhala , Srinivas Kandagatla , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6665; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=v8N/E1MOA6ZgOQNnGcaGJb2KY2m9e/2WC35Ddu9CIss=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnJQ2XbzaVa70MV0ZU9sgf1qyjMHSL9Zzi1RUop JjykjFlXU+JAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZyUNlwAKCRDBN2bmhouD 1xVUD/9Elk6ZjE43TFLfGTx/red5EcCr+xW53kwc2qW8sDgCPnyXBrhuDn2rPNSg+6x78AUqYcF 36XxiPp1l0kU/Sz/uvrbRpQKlmVLxuj1d1xSRl4v/C4Hth5q3oxWEtlNhaekpaEiCZPjBbAlEO8 x6kV8mST3SkMBz1v3Ri2nM71ljFPcf3ruBY4q0nq3LNJcd+ybCSS9f5BCikw1xNPjiuKDY/GJQD SxZUwQtz+MN8a7vhvw3llB1j+b2YmhsrGk5TrT1G9IPGWwBfIx85/rq2Co0EWI2QI6SPzEmCYMv oJeR8IqCXBCigut9jTpjs2IbSvnknGWF3sLimYXaneYlz3qvCVtT1xopKzJmTnmkl4Wva+t8VKE M5kCGS7P1TXE8JoH8xhqR2p8AVw4b/UHIbSerLPZSeD0t3mP/bxdiEJ983Oj/sEinXk6a4Nx/UJ TmKAzlh7Dl3NXzYE95oTHyDwXDBXZvp0rqaIuI3GEMfNhDPYGwUvVTKp+MrsaoQezyHSE3w4LyF 5deyCk57IWeTGbp9enTVclLASO+9OxsucWV7x4FlPmu7upBcf3agFAG+pdmBWL1T80HlpFeVpDG QVmQnTOu5oCPbHUyOj72WogEZnXzb1Il02LFXBbJBE1O+VFoE1YirmPzaWWRLQowEY8bl0qlz49 gKyoiAdl19h5I9g== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add LPASS macro codecs and LPASS TLMM pin controller on Qualcomm SM8750 for proper sound support. These are fully compatible with earlier SM8550. Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 202 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 202 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index eb826b154dcb2d8165426ba2225548efd7547da8..bd50a78534a3182d102385f2cc4= 3a2688dd782cd 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include =20 / { interrupt-parent =3D <&intc>; @@ -2002,6 +2003,207 @@ lpass_lpicx_noc: interconnect@7420000 { #interconnect-cells =3D <2>; }; =20 + lpass_wsa2macro: codec@6aa0000 { + compatible =3D "qcom,sm8750-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-ma= cro"; + reg =3D <0 0x06aa0000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE= _COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "wsa2-mclk"; + #sound-dai-cells =3D <1>; + }; + + lpass_rxmacro: codec@6ac0000 { + compatible =3D "qcom,sm8750-lpass-rx-macro", "qcom,sm8550-lpass-rx-macr= o"; + reg =3D <0 0x06ac0000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_C= OUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + }; + + lpass_txmacro: codec@6ae0000 { + compatible =3D "qcom,sm8750-lpass-tx-macro", "qcom,sm8550-lpass-tx-macr= o"; + reg =3D <0 0x06ae0000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + }; + + lpass_wsamacro: codec@6b00000 { + compatible =3D "qcom,sm8750-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-ma= cro"; + reg =3D <0 0x06b00000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_= COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + }; + + lpass_vamacro: codec@7660000 { + compatible =3D "qcom,sm8750-lpass-va-macro", "qcom,sm8550-lpass-va-macr= o"; + reg =3D <0 0x07660000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "mclk", + "macro", + "dcodec"; + + #clock-cells =3D <0>; + clock-output-names =3D "fsgen"; + #sound-dai-cells =3D <1>; + }; + + lpass_tlmm: pinctrl@7760000 { + compatible =3D "qcom,sm8750-lpass-lpi-pinctrl", + "qcom,sm8650-lpass-lpi-pinctrl"; + reg =3D <0 0x07760000 0 0x20000>; + + clocks =3D <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "core", "audio"; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpass_tlmm 0 0 23>; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins =3D "gpio0"; + function =3D "swr_tx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio1", "gpio2", "gpio14"; + function =3D "swr_tx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins =3D "gpio3"; + function =3D "swr_rx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio4", "gpio5"; + function =3D "swr_rx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + dmic01_default: dmic01-default-state { + clk-pins { + pins =3D "gpio6"; + function =3D "dmic1_clk"; + drive-strength =3D <8>; + output-high; + }; + + data-pins { + pins =3D "gpio7"; + function =3D "dmic1_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + dmic23_default: dmic23-default-state { + clk-pins { + pins =3D "gpio8"; + function =3D "dmic2_clk"; + drive-strength =3D <8>; + output-high; + }; + + data-pins { + pins =3D "gpio9"; + function =3D "dmic2_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + wsa_swr_active: wsa-swr-active-state { + clk-pins { + pins =3D "gpio10"; + function =3D "wsa_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio11"; + function =3D "wsa_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + wsa2_swr_active: wsa2-swr-active-state { + clk-pins { + pins =3D "gpio15"; + function =3D "wsa2_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio16"; + function =3D "wsa2_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,sm8750-pdc", "qcom,pdc"; reg =3D <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; --=20 2.43.0