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Fri, 01 Nov 2024 11:34:24 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4A1BYO2H031472 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 1 Nov 2024 11:34:24 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 1 Nov 2024 04:34:20 -0700 From: Krishna chaitanya chundru Date: Fri, 1 Nov 2024 17:04:12 +0530 Subject: [PATCH v3 1/3] PCI: dwc: Skip waiting for link up if vendor drivers can detect Link up event Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241101-remove_wait-v3-1-7accf27f7202@quicinc.com> References: <20241101-remove_wait-v3-0-7accf27f7202@quicinc.com> In-Reply-To: <20241101-remove_wait-v3-0-7accf27f7202@quicinc.com> To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas CC: , , , , , Krishna chaitanya chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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So skip waiting for link to be up if the driver supports 'linkup_irq'. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 10 ++++++++-- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 3e41865c7290..26418873ce14 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -530,8 +530,14 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) goto err_remove_edma; } =20 - /* Ignore errors, the link may come up later */ - dw_pcie_wait_for_link(pci); + /* + * Note: The link up delay is skipped only when a link up IRQ is present. + * This flag should not be used to bypass the link up delay for arbitrary + * reasons. + */ + if (!pp->linkup_irq) + /* Ignore errors, the link may come up later */ + dw_pcie_wait_for_link(pci); =20 bridge->sysdata =3D pp; =20 diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 347ab74ac35a..539c6d106bb0 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -379,6 +379,7 @@ struct dw_pcie_rp { bool use_atu_msg; int msg_atu_index; struct resource *msg_res; + bool linkup_irq; }; =20 struct dw_pcie_ep_ops { --=20 2.34.1