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Fri, 01 Nov 2024 10:39:04 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4A1Ad4PD026965 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 1 Nov 2024 10:39:04 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 1 Nov 2024 03:38:58 -0700 From: Taniya Das Date: Fri, 1 Nov 2024 16:08:18 +0530 Subject: [PATCH v2 06/11] clk: qcom: dispcc-qcs615: Add QCS615 display clock controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241101-qcs615-mm-clockcontroller-v2-6-d1a4870a4aed@quicinc.com> References: <20241101-qcs615-mm-clockcontroller-v2-0-d1a4870a4aed@quicinc.com> In-Reply-To: <20241101-qcs615-mm-clockcontroller-v2-0-d1a4870a4aed@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Abhishek Sahu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , , , Taniya Das , Dmitry Baryshkov X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: KuTxLgZZ8HxFVCcVk04Q_HeqG2gk4grg X-Proofpoint-GUID: KuTxLgZZ8HxFVCcVk04Q_HeqG2gk4grg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 phishscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 mlxlogscore=999 suspectscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411010076 Add support for the display clock controller for display clients to be able to request for the clocks on QCS615 platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/dispcc-qcs615.c | 786 +++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 796 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index bdb1c672dd90d96814b214afd234341e37e3c470..d0c815e8e4789958151742a8269= d7d6f2245b26c 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -460,6 +460,15 @@ config QCM_DISPCC_2290 Say Y if you want to support display devices and functionality such as splash screen. =20 +config QCS_DISPCC_615 + tristate "QCS615 Display Clock Controller" + select QCM_GCC_615 + help + Support for the display clock controller on Qualcomm Technologies, Inc + QCS615 devices. + Say Y if you want to support display devices and functionality such as + splash screen. + config QCS_CAMCC_615 tristate "QCS615 Camera Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index f69c1bc13d3eca1859d9e849399e55175df869c3..f2be0c678127c8f78c5ee708993= ebef273d02f19 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -69,6 +69,7 @@ obj-$(CONFIG_QCOM_CLK_RPMH) +=3D clk-rpmh.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) +=3D clk-smd-rpm.o obj-$(CONFIG_QCM_GCC_2290) +=3D gcc-qcm2290.o obj-$(CONFIG_QCM_DISPCC_2290) +=3D dispcc-qcm2290.o +obj-$(CONFIG_QCS_DISPCC_615) +=3D dispcc-qcs615.o obj-$(CONFIG_QCS_CAMCC_615) +=3D camcc-qcs615.o obj-$(CONFIG_QCS_GCC_404) +=3D gcc-qcs404.o obj-$(CONFIG_QCS_Q6SSTOP_404) +=3D q6sstop-qcs404.o diff --git a/drivers/clk/qcom/dispcc-qcs615.c b/drivers/clk/qcom/dispcc-qcs= 615.c new file mode 100644 index 0000000000000000000000000000000000000000..5dac28476b855b9650d23494466= b0a54ccef2c1f --- /dev/null +++ b/drivers/clk/qcom/dispcc-qcs615.c @@ -0,0 +1,786 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GPLL0, + DT_DSI0_PHY_PLL_OUT_BYTECLK, + DT_DSI0_PHY_PLL_OUT_DSICLK, + DT_DSI1_PHY_PLL_OUT_DSICLK, + DT_DP_PHY_PLL_LINK_CLK, + DT_DP_PHY_PLL_VCO_DIV_CLK, +}; + +enum { + P_BI_TCXO, + P_DISP_CC_PLL0_OUT_MAIN, + P_DP_PHY_PLL_LINK_CLK, + P_DP_PHY_PLL_VCO_DIV_CLK, + P_DSI0_PHY_PLL_OUT_BYTECLK, + P_DSI0_PHY_PLL_OUT_DSICLK, + P_DSI1_PHY_PLL_OUT_DSICLK, + P_GPLL0_OUT_MAIN, +}; + +static const struct pll_vco disp_cc_pll_vco[] =3D { + { 500000000, 1000000000, 2 }, +}; + +/* 576MHz configuration */ +static struct alpha_pll_config disp_cc_pll0_config =3D { + .l =3D 0x1e, + .vco_val =3D 0x2 << 20, + .vco_mask =3D 0x3 << 20, + .main_output_mask =3D BIT(0), + .config_ctl_val =3D 0x4001055b, + .test_ctl_hi_val =3D 0x1, + .test_ctl_hi_mask =3D 0x1, +}; + +static struct clk_alpha_pll disp_cc_pll0 =3D { + .offset =3D 0x0, + .vco_table =3D disp_cc_pll_vco, + .num_vco =3D ARRAY_SIZE(disp_cc_pll_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_slew_ops, + }, + }, +}; + +static const struct parent_map disp_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_DP_PHY_PLL_LINK_CLK, 1 }, + { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DP_PHY_PLL_LINK_CLK }, + { .index =3D DT_DP_PHY_PLL_VCO_DIV_CLK }, +}; + +static const struct parent_map disp_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map disp_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DSI0_PHY_PLL_OUT_BYTECLK }, +}; + +static const struct parent_map disp_cc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_DISP_CC_PLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_MAIN, 4 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &disp_cc_pll0.clkr.hw }, + { .index =3D DT_GPLL0 }, +}; + +static const struct parent_map disp_cc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 4 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_GPLL0 }, +}; + +static const struct parent_map disp_cc_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, + { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_5[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DSI0_PHY_PLL_OUT_DSICLK }, + { .index =3D DT_DSI1_PHY_PLL_OUT_DSICLK }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_ahb_clk_src =3D { + .cmd_rcgr =3D 0x2170, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_4, + .freq_tbl =3D ftbl_disp_cc_mdss_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_ahb_clk_src", + .parent_data =3D disp_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_4), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src =3D { + .cmd_rcgr =3D 0x20c0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_2, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte0_clk_src", + .parent_data =3D disp_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux1_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src =3D { + .cmd_rcgr =3D 0x2158, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_1, + .freq_tbl =3D ftbl_disp_cc_mdss_dp_aux1_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_dp_aux_clk_src", + .parent_data =3D disp_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src =3D { + .cmd_rcgr =3D 0x2110, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_0, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_crypto_clk_src", + .parent_data =3D disp_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src =3D { + .cmd_rcgr =3D 0x20f4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_0, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_link_clk_src", + .parent_data =3D disp_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src =3D { + .cmd_rcgr =3D 0x2140, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_0, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_pixel1_clk_src", + .parent_data =3D disp_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src =3D { + .cmd_rcgr =3D 0x2128, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_0, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_pixel_clk_src", + .parent_data =3D disp_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_esc0_clk_src =3D { + .cmd_rcgr =3D 0x20dc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_2, + .freq_tbl =3D ftbl_disp_cc_mdss_dp_aux1_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_esc0_clk_src", + .parent_data =3D disp_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(307000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_mdp_clk_src =3D { + .cmd_rcgr =3D 0x2078, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_3, + .freq_tbl =3D ftbl_disp_cc_mdss_mdp_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_mdp_clk_src", + .parent_data =3D disp_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src =3D { + .cmd_rcgr =3D 0x2060, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_5, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_pclk0_clk_src", + .parent_data =3D disp_cc_parent_data_5, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_rot_clk_src =3D { + .cmd_rcgr =3D 0x2090, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_3, + .freq_tbl =3D ftbl_disp_cc_mdss_mdp_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_rot_clk_src", + .parent_data =3D disp_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_vsync_clk_src =3D { + .cmd_rcgr =3D 0x20a8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_1, + .freq_tbl =3D ftbl_disp_cc_mdss_dp_aux1_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_vsync_clk_src", + .parent_data =3D disp_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src =3D { + .reg =3D 0x20d8, + .shift =3D 0, + .width =3D 2, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src =3D { + .reg =3D 0x210c, + .shift =3D 0, + .width =3D 2, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_link_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dp_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch disp_cc_mdss_ahb_clk =3D { + .halt_reg =3D 0x2048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_clk =3D { + .halt_reg =3D 0x2024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_intf_clk =3D { + .halt_reg =3D 0x2028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte0_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_byte0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_aux_clk =3D { + .halt_reg =3D 0x2044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dp_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_crypto_clk =3D { + .halt_reg =3D 0x2038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_crypto_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dp_crypto_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_clk =3D { + .halt_reg =3D 0x2030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_link_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dp_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_intf_clk =3D { + .halt_reg =3D 0x2034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dp_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_pixel1_clk =3D { + .halt_reg =3D 0x2040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_pixel1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_pixel_clk =3D { + .halt_reg =3D 0x203c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x203c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_pixel_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_esc0_clk =3D { + .halt_reg =3D 0x202c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x202c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_esc0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_esc0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_clk =3D { + .halt_reg =3D 0x2008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_mdp_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_lut_clk =3D { + .halt_reg =3D 0x2018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_mdp_lut_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk =3D { + .halt_reg =3D 0x4004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_non_gdsc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_pclk0_clk =3D { + .halt_reg =3D 0x2004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_pclk0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_pclk0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rot_clk =3D { + .halt_reg =3D 0x2010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_rot_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_rot_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rscc_ahb_clk =3D { + .halt_reg =3D 0x400c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x400c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_rscc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rscc_vsync_clk =3D { + .halt_reg =3D 0x4008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x4008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_rscc_vsync_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_vsync_clk =3D { + .halt_reg =3D 0x2020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_vsync_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc mdss_core_gdsc =3D { + .gdscr =3D 0x3000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "mdss_core_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL | POLL_CFG_GDSCR, +}; + +static struct clk_regmap *disp_cc_qcs615_clocks[] =3D { + [DISP_CC_MDSS_AHB_CLK] =3D &disp_cc_mdss_ahb_clk.clkr, + [DISP_CC_MDSS_AHB_CLK_SRC] =3D &disp_cc_mdss_ahb_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_CLK] =3D &disp_cc_mdss_byte0_clk.clkr, + [DISP_CC_MDSS_BYTE0_CLK_SRC] =3D &disp_cc_mdss_byte0_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] =3D &disp_cc_mdss_byte0_div_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_INTF_CLK] =3D &disp_cc_mdss_byte0_intf_clk.clkr, + [DISP_CC_MDSS_DP_AUX_CLK] =3D &disp_cc_mdss_dp_aux_clk.clkr, + [DISP_CC_MDSS_DP_AUX_CLK_SRC] =3D &disp_cc_mdss_dp_aux_clk_src.clkr, + [DISP_CC_MDSS_DP_CRYPTO_CLK] =3D &disp_cc_mdss_dp_crypto_clk.clkr, + [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] =3D &disp_cc_mdss_dp_crypto_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK_CLK] =3D &disp_cc_mdss_dp_link_clk.clkr, + [DISP_CC_MDSS_DP_LINK_CLK_SRC] =3D &disp_cc_mdss_dp_link_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] =3D &disp_cc_mdss_dp_link_div_clk_src.= clkr, + [DISP_CC_MDSS_DP_LINK_INTF_CLK] =3D &disp_cc_mdss_dp_link_intf_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL1_CLK] =3D &disp_cc_mdss_dp_pixel1_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] =3D &disp_cc_mdss_dp_pixel1_clk_src.clkr, + [DISP_CC_MDSS_DP_PIXEL_CLK] =3D &disp_cc_mdss_dp_pixel_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] =3D &disp_cc_mdss_dp_pixel_clk_src.clkr, + [DISP_CC_MDSS_ESC0_CLK] =3D &disp_cc_mdss_esc0_clk.clkr, + [DISP_CC_MDSS_ESC0_CLK_SRC] =3D &disp_cc_mdss_esc0_clk_src.clkr, + [DISP_CC_MDSS_MDP_CLK] =3D &disp_cc_mdss_mdp_clk.clkr, + [DISP_CC_MDSS_MDP_CLK_SRC] =3D &disp_cc_mdss_mdp_clk_src.clkr, + [DISP_CC_MDSS_MDP_LUT_CLK] =3D &disp_cc_mdss_mdp_lut_clk.clkr, + [DISP_CC_MDSS_NON_GDSC_AHB_CLK] =3D &disp_cc_mdss_non_gdsc_ahb_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK] =3D &disp_cc_mdss_pclk0_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK_SRC] =3D &disp_cc_mdss_pclk0_clk_src.clkr, + [DISP_CC_MDSS_ROT_CLK] =3D &disp_cc_mdss_rot_clk.clkr, + [DISP_CC_MDSS_ROT_CLK_SRC] =3D &disp_cc_mdss_rot_clk_src.clkr, + [DISP_CC_MDSS_RSCC_AHB_CLK] =3D &disp_cc_mdss_rscc_ahb_clk.clkr, + [DISP_CC_MDSS_RSCC_VSYNC_CLK] =3D &disp_cc_mdss_rscc_vsync_clk.clkr, + [DISP_CC_MDSS_VSYNC_CLK] =3D &disp_cc_mdss_vsync_clk.clkr, + [DISP_CC_MDSS_VSYNC_CLK_SRC] =3D &disp_cc_mdss_vsync_clk_src.clkr, + [DISP_CC_PLL0] =3D &disp_cc_pll0.clkr, +}; + +static struct gdsc *disp_cc_qcs615_gdscs[] =3D { + [MDSS_CORE_GDSC] =3D &mdss_core_gdsc, +}; + +static const struct regmap_config disp_cc_qcs615_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x10000, + .fast_io =3D true, +}; + +static const struct qcom_cc_desc disp_cc_qcs615_desc =3D { + .config =3D &disp_cc_qcs615_regmap_config, + .clks =3D disp_cc_qcs615_clocks, + .num_clks =3D ARRAY_SIZE(disp_cc_qcs615_clocks), + .gdscs =3D disp_cc_qcs615_gdscs, + .num_gdscs =3D ARRAY_SIZE(disp_cc_qcs615_gdscs), +}; + +static const struct of_device_id disp_cc_qcs615_match_table[] =3D { + { .compatible =3D "qcom,qcs615-dispcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, disp_cc_qcs615_match_table); + +static int disp_cc_qcs615_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap =3D qcom_cc_map(pdev, &disp_cc_qcs615_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); + + /* Keep some clocks always enabled */ + qcom_branch_set_clk_en(regmap, 0x6054); /* DISP_CC_XO_CLK */ + + return qcom_cc_really_probe(&pdev->dev, &disp_cc_qcs615_desc, regmap); +} + +static struct platform_driver disp_cc_qcs615_driver =3D { + .probe =3D disp_cc_qcs615_probe, + .driver =3D { + .name =3D "dispcc-qcs615", + .of_match_table =3D disp_cc_qcs615_match_table, + }, +}; + +module_platform_driver(disp_cc_qcs615_driver); + +MODULE_DESCRIPTION("QTI DISPCC QCS615 Driver"); +MODULE_LICENSE("GPL"); --=20 2.45.2