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Fri, 01 Nov 2024 10:38:39 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4A1Accnp026153 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 1 Nov 2024 10:38:38 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 1 Nov 2024 03:38:33 -0700 From: Taniya Das Date: Fri, 1 Nov 2024 16:08:13 +0530 Subject: [PATCH v2 01/11] clk: qcom: Update the support for alpha mode configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241101-qcs615-mm-clockcontroller-v2-1-d1a4870a4aed@quicinc.com> References: <20241101-qcs615-mm-clockcontroller-v2-0-d1a4870a4aed@quicinc.com> In-Reply-To: <20241101-qcs615-mm-clockcontroller-v2-0-d1a4870a4aed@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Abhishek Sahu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , , , Taniya Das , Dmitry Baryshkov , Gabor Juhos X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: hhO69wld8bRs9e79nmwjvovgtyWhBegm X-Proofpoint-GUID: hhO69wld8bRs9e79nmwjvovgtyWhBegm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 phishscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 mlxlogscore=999 suspectscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411010076 The alpha_en_mask and alpha_mode_mask must be applied within the clk_alpha_pll_configure() function to ensure proper configuration of the alpha mode of the PLL. Fixes: c45ae598fc16 ("clk: qcom: support for alpha mode configuration") Reviewed-by: Dmitry Baryshkov Tested-by: Gabor Juhos Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-alpha-pll.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-= pll.c index f9105443d7dbb104e3cb091e59f43df25999f8b3..03cc7aa092480bfdd9eaa986d44= f0545944b3b89 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -421,6 +421,8 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll,= struct regmap *regmap, mask |=3D config->pre_div_mask; mask |=3D config->post_div_mask; mask |=3D config->vco_mask; + mask |=3D config->alpha_en_mask; + mask |=3D config->alpha_mode_mask; =20 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); =20 --=20 2.45.2