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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , Heiner Kallweit , Russell King CC: , , , , , , , , , , , , X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730457277; l=7406; i=quic_leiwei@quicinc.com; s=20240829; h=from:subject:message-id; bh=5BCkNeRcshI9KjANnXaqdtrejbfKFp3NeWF0f9umzBg=; b=EKC/Faohp4cixOpYExMX2fd++2qoCs2XW2LN+AiwZDCKBu1IcH/N0zkQcR2XUAXxqCOfKJzwD xLKWmLwXB+PAsG5Ufj6yrSCnolMkzAw5B1gX+I6tW0mpmZMv0zH0UJ9 X-Developer-Key: i=quic_leiwei@quicinc.com; a=ed25519; pk=uFXBHtxtDjtIrTKpDEZlMLSn1i/sonZepYO8yioKACM= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 690z9GnxDjB4r-KgS961yNTXifzaispV X-Proofpoint-ORIG-GUID: 690z9GnxDjB4r-KgS961yNTXifzaispV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 impostorscore=0 mlxscore=0 suspectscore=0 adultscore=0 clxscore=1015 phishscore=0 spamscore=0 mlxlogscore=999 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411010076 USXGMII mode is enabled by PCS when 10Gbps PHYs are connected, such as Aquantia 10Gbps PHY. Signed-off-by: Lei Wei --- drivers/net/pcs/pcs-qcom-ipq.c | 180 +++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 180 insertions(+) diff --git a/drivers/net/pcs/pcs-qcom-ipq.c b/drivers/net/pcs/pcs-qcom-ipq.c index dd432303b549..19cb995f7c87 100644 --- a/drivers/net/pcs/pcs-qcom-ipq.c +++ b/drivers/net/pcs/pcs-qcom-ipq.c @@ -26,6 +26,7 @@ #define PCS_MODE_SEL_MASK GENMASK(12, 8) #define PCS_MODE_SGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x4) #define PCS_MODE_QSGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x1) +#define PCS_MODE_XPCS FIELD_PREP(PCS_MODE_SEL_MASK, 0x10) #define PCS_MODE_AN_MODE BIT(0) =20 #define PCS_MII_CTRL(x) (0x480 + 0x18 * (x)) @@ -57,6 +58,35 @@ FIELD_PREP(GENMASK(9, 2), \ FIELD_GET(XPCS_INDIRECT_ADDR_L, reg))) =20 +#define XPCS_DIG_CTRL 0x38000 +#define XPCS_USXG_ADPT_RESET BIT(10) +#define XPCS_USXG_EN BIT(9) + +#define XPCS_MII_CTRL 0x1f0000 +#define XPCS_MII_AN_EN BIT(12) +#define XPCS_DUPLEX_FULL BIT(8) +#define XPCS_SPEED_MASK (BIT(13) | BIT(6) | BIT(5)) +#define XPCS_SPEED_10000 (BIT(13) | BIT(6)) +#define XPCS_SPEED_5000 (BIT(13) | BIT(5)) +#define XPCS_SPEED_2500 BIT(5) +#define XPCS_SPEED_1000 BIT(6) +#define XPCS_SPEED_100 BIT(13) +#define XPCS_SPEED_10 0 + +#define XPCS_MII_AN_CTRL 0x1f8001 +#define XPCS_MII_AN_8BIT BIT(8) + +#define XPCS_MII_AN_INTR_STS 0x1f8002 +#define XPCS_USXG_AN_LINK_STS BIT(14) +#define XPCS_USXG_AN_DUPLEX_FULL BIT(13) +#define XPCS_USXG_AN_SPEED_MASK GENMASK(12, 10) +#define XPCS_USXG_AN_SPEED_10 0 +#define XPCS_USXG_AN_SPEED_100 1 +#define XPCS_USXG_AN_SPEED_1000 2 +#define XPCS_USXG_AN_SPEED_2500 4 +#define XPCS_USXG_AN_SPEED_5000 5 +#define XPCS_USXG_AN_SPEED_10000 3 + /* Private data for the PCS instance */ struct ipq_pcs { struct device *dev; @@ -144,9 +174,57 @@ static void ipq_pcs_get_state_sgmii(struct ipq_pcs *qp= cs, state->pause |=3D MLO_PAUSE_RX; } =20 +static void ipq_pcs_get_state_usxgmii(struct ipq_pcs *qpcs, + struct phylink_link_state *state) +{ + unsigned int val; + int ret; + + ret =3D regmap_read(qpcs->regmap, XPCS_MII_AN_INTR_STS, &val); + if (ret) { + state->link =3D 0; + return; + } + + state->link =3D !!(val & XPCS_USXG_AN_LINK_STS); + + if (!state->link) + return; + + switch (FIELD_GET(XPCS_USXG_AN_SPEED_MASK, val)) { + case XPCS_USXG_AN_SPEED_10000: + state->speed =3D SPEED_10000; + break; + case XPCS_USXG_AN_SPEED_5000: + state->speed =3D SPEED_5000; + break; + case XPCS_USXG_AN_SPEED_2500: + state->speed =3D SPEED_2500; + break; + case XPCS_USXG_AN_SPEED_1000: + state->speed =3D SPEED_1000; + break; + case XPCS_USXG_AN_SPEED_100: + state->speed =3D SPEED_100; + break; + case XPCS_USXG_AN_SPEED_10: + state->speed =3D SPEED_10; + break; + default: + state->link =3D false; + return; + } + + if (val & XPCS_USXG_AN_DUPLEX_FULL) + state->duplex =3D DUPLEX_FULL; + else + state->duplex =3D DUPLEX_HALF; +} + static int ipq_pcs_config_mode(struct ipq_pcs *qpcs, phy_interface_t interface) { + unsigned long rate =3D 125000000; unsigned int val; int ret; =20 @@ -167,6 +245,13 @@ static int ipq_pcs_config_mode(struct ipq_pcs *qpcs, if (ret) return ret; break; + case PHY_INTERFACE_MODE_USXGMII: + rate =3D 312500000; + ret =3D regmap_update_bits(qpcs->regmap, PCS_MODE_CTRL, + PCS_MODE_SEL_MASK, PCS_MODE_XPCS); + if (ret) + return ret; + break; default: dev_err(qpcs->dev, "Unsupported interface %s\n", phy_modes(interface)); @@ -196,6 +281,21 @@ static int ipq_pcs_config_mode(struct ipq_pcs *qpcs, =20 qpcs->interface =3D interface; =20 + /* Configure the RX and TX clock to NSSCC as 125M or 312.5M based + * on current interface mode. + */ + ret =3D clk_set_rate(qpcs->rx_hw.clk, rate); + if (ret) { + dev_err(qpcs->dev, "Failed to set RX clock rate\n"); + return ret; + } + + ret =3D clk_set_rate(qpcs->tx_hw.clk, rate); + if (ret) { + dev_err(qpcs->dev, "Failed to set TX clock rate\n"); + return ret; + } + return 0; } =20 @@ -240,6 +340,35 @@ static int ipq_pcs_config_sgmii(struct ipq_pcs *qpcs, return ret; } =20 +static int ipq_pcs_config_usxgmii(struct ipq_pcs *qpcs) +{ + int ret; + + /* Configure the XPCS for USXGMII mode if required */ + if (qpcs->interface !=3D PHY_INTERFACE_MODE_USXGMII) { + ret =3D ipq_pcs_config_mode(qpcs, PHY_INTERFACE_MODE_USXGMII); + if (ret) + return ret; + + ret =3D regmap_update_bits(qpcs->regmap, XPCS_DIG_CTRL, + XPCS_USXG_EN, XPCS_USXG_EN); + if (ret) + return ret; + + ret =3D regmap_update_bits(qpcs->regmap, XPCS_MII_AN_CTRL, + XPCS_MII_AN_8BIT, XPCS_MII_AN_8BIT); + if (ret) + return ret; + + ret =3D regmap_update_bits(qpcs->regmap, XPCS_MII_CTRL, + XPCS_MII_AN_EN, XPCS_MII_AN_EN); + if (ret) + return ret; + } + + return 0; +} + static int ipq_pcs_link_up_config_sgmii(struct ipq_pcs *qpcs, int index, unsigned int neg_mode, @@ -288,6 +417,49 @@ static int ipq_pcs_link_up_config_sgmii(struct ipq_pcs= *qpcs, PCS_MII_ADPT_RESET, PCS_MII_ADPT_RESET); } =20 +static int ipq_pcs_link_up_config_usxgmii(struct ipq_pcs *qpcs, int speed) +{ + unsigned int val; + int ret; + + switch (speed) { + case SPEED_10000: + val =3D XPCS_SPEED_10000; + break; + case SPEED_5000: + val =3D XPCS_SPEED_5000; + break; + case SPEED_2500: + val =3D XPCS_SPEED_2500; + break; + case SPEED_1000: + val =3D XPCS_SPEED_1000; + break; + case SPEED_100: + val =3D XPCS_SPEED_100; + break; + case SPEED_10: + val =3D XPCS_SPEED_10; + break; + default: + dev_err(qpcs->dev, "Invalid USXGMII speed %d\n", speed); + return -EINVAL; + } + + /* USXGMII only support full duplex mode */ + val |=3D XPCS_DUPLEX_FULL; + + /* Configure XPCS speed */ + ret =3D regmap_update_bits(qpcs->regmap, XPCS_MII_CTRL, + XPCS_SPEED_MASK | XPCS_DUPLEX_FULL, val); + if (ret) + return ret; + + /* XPCS adapter reset */ + return regmap_update_bits(qpcs->regmap, XPCS_DIG_CTRL, + XPCS_USXG_ADPT_RESET, XPCS_USXG_ADPT_RESET); +} + static void ipq_pcs_get_state(struct phylink_pcs *pcs, struct phylink_link_state *state) { @@ -300,6 +472,9 @@ static void ipq_pcs_get_state(struct phylink_pcs *pcs, case PHY_INTERFACE_MODE_QSGMII: ipq_pcs_get_state_sgmii(qpcs, index, state); break; + case PHY_INTERFACE_MODE_USXGMII: + ipq_pcs_get_state_usxgmii(qpcs, state); + break; default: break; } @@ -326,6 +501,8 @@ static int ipq_pcs_config(struct phylink_pcs *pcs, case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: return ipq_pcs_config_sgmii(qpcs, index, neg_mode, interface); + case PHY_INTERFACE_MODE_USXGMII: + return ipq_pcs_config_usxgmii(qpcs); default: dev_err(qpcs->dev, "Unsupported interface %s\n", phy_modes(interface)); @@ -349,6 +526,9 @@ static void ipq_pcs_link_up(struct phylink_pcs *pcs, ret =3D ipq_pcs_link_up_config_sgmii(qpcs, index, neg_mode, speed); break; + case PHY_INTERFACE_MODE_USXGMII: + ret =3D ipq_pcs_link_up_config_usxgmii(qpcs, speed); + break; default: dev_err(qpcs->dev, "Unsupported interface %s\n", phy_modes(interface)); --=20 2.34.1