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This involves examining the msi-map and smmu-map to ensure consistent mapping of PCI BDF to the same stream IDs. Subsequently, LUT-related registers are configured. In the absence of an msi-map, the built-in MSI controller is utilized as a fallback. Additionally, register a PCI bus callback function enable_device() and disable_device() to config LUT when enable a new PCI device. Signed-off-by: Frank Li --- Change from v3 to v4 - Check target value at of_map_id(). - of_node_put() for target. - add case for msi-map exist, but rid entry is not exist. Change from v2 to v3 - Use the "target" argument of of_map_id() - Check if rid already in lut table when enable device change from v1 to v2 - set callback to pci_host_bridge instead pci->ops. --- drivers/pci/controller/dwc/pci-imx6.c | 177 ++++++++++++++++++++++++++++++= +++- 1 file changed, 176 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 94f3411352bf0..1be17bc39ce54 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -55,6 +55,22 @@ #define IMX95_PE0_GEN_CTRL_3 0x1058 #define IMX95_PCIE_LTSSM_EN BIT(0) =20 +#define IMX95_PE0_LUT_ACSCTRL 0x1008 +#define IMX95_PEO_LUT_RWA BIT(16) +#define IMX95_PE0_LUT_ENLOC GENMASK(4, 0) + +#define IMX95_PE0_LUT_DATA1 0x100c +#define IMX95_PE0_LUT_VLD BIT(31) +#define IMX95_PE0_LUT_DAC_ID GENMASK(10, 8) +#define IMX95_PE0_LUT_STREAM_ID GENMASK(5, 0) + +#define IMX95_PE0_LUT_DATA2 0x1010 +#define IMX95_PE0_LUT_REQID GENMASK(31, 16) +#define IMX95_PE0_LUT_MASK GENMASK(15, 0) + +#define IMX95_SID_MASK GENMASK(5, 0) +#define IMX95_MAX_LUT 32 + #define to_imx_pcie(x) dev_get_drvdata((x)->dev) =20 enum imx_pcie_variants { @@ -82,6 +98,7 @@ enum imx_pcie_variants { #define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5) #define IMX_PCIE_FLAG_HAS_SERDES BIT(6) #define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7) +#define IMX_PCIE_FLAG_HAS_LUT BIT(8) =20 #define imx_check_flag(pci, val) (pci->drvdata->flags & val) =20 @@ -134,6 +151,7 @@ struct imx_pcie { struct device *pd_pcie_phy; struct phy *phy; const struct imx_pcie_drvdata *drvdata; + struct mutex lock; }; =20 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ @@ -925,6 +943,155 @@ static void imx_pcie_stop_link(struct dw_pcie *pci) imx_pcie_ltssm_disable(dev); } =20 +static int imx_pcie_add_lut(struct imx_pcie *imx_pcie, u16 reqid, u8 sid) +{ + struct dw_pcie *pci =3D imx_pcie->pci; + struct device *dev =3D pci->dev; + u32 data1, data2; + int i; + + if (sid >=3D 64) { + dev_err(dev, "Invalid SID for index %d\n", sid); + return -EINVAL; + } + + guard(mutex)(&imx_pcie->lock); + + for (i =3D 0; i < IMX95_MAX_LUT; i++) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, IMX95_PEO_LUT_= RWA | i); + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, &data1); + + if (!(data1 & IMX95_PE0_LUT_VLD)) + continue; + + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); + + /* Needn't add duplicated Request ID */ + if (reqid =3D=3D FIELD_GET(IMX95_PE0_LUT_REQID, data2)) + return 0; + } + + for (i =3D 0; i < IMX95_MAX_LUT; i++) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, IMX95_PEO_LUT_= RWA | i); + + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, &data1); + if (data1 & IMX95_PE0_LUT_VLD) + continue; + + data1 =3D FIELD_PREP(IMX95_PE0_LUT_DAC_ID, 0); + data1 |=3D FIELD_PREP(IMX95_PE0_LUT_STREAM_ID, sid); + data1 |=3D IMX95_PE0_LUT_VLD; + + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, data1); + + data2 =3D 0xffff; + data2 |=3D FIELD_PREP(IMX95_PE0_LUT_REQID, reqid); + + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, data2); + + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, i); + + return 0; + } + + dev_err(dev, "All lut already used\n"); + return -EINVAL; +} + +static void imx_pcie_remove_lut(struct imx_pcie *imx_pcie, u16 reqid) +{ + u32 data2 =3D 0; + int i; + + guard(mutex)(&imx_pcie->lock); + + for (i =3D 0; i < IMX95_MAX_LUT; i++) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, IMX95_PEO_LUT_= RWA | i); + + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); + if (FIELD_GET(IMX95_PE0_LUT_REQID, data2) =3D=3D reqid) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, 0); + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, 0); + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, i); + + break; + } + } +} + +static int imx_pcie_enable_device(struct pci_host_bridge *bridge, struct p= ci_dev *pdev) +{ + u32 sid_i =3D 0, sid_m =3D 0, rid =3D pci_dev_id(pdev); + struct device_node *target; + struct imx_pcie *imx_pcie; + struct device *dev; + int err_i, err_m; + + imx_pcie =3D to_imx_pcie(to_dw_pcie_from_pp(bridge->sysdata)); + dev =3D imx_pcie->pci->dev; + + target =3D NULL; + err_i =3D of_map_id(dev->of_node, rid, "iommu-map", "iommu-map-mask", &ta= rget, &sid_i); + if (target) + of_node_put(target); + else + err_i =3D -EINVAL; + + target =3D NULL; + err_m =3D of_map_id(dev->of_node, rid, "msi-map", "msi-map-mask", &target= , &sid_m); + + /* + * Return failure if msi-map exist and no entry for rid because dwc common + * driver will skip setting up built-in MSI controller if msi-map existed. + * + * err_m target + * 0 NULL Return failure, function not work. + * !0 NULL msi-map not exist, use built-in MSI. + * 0 !NULL Find one entry. + * !0 !NULL Invalidate case. + */ + if (!err_m && !target) + return -EINVAL; + else if (target) + of_node_put(target); /* Find entry for rid in msi-map */ + + /* + * msi-map iommu-map + * Y Y ITS + SMMU, require the same sid + * Y N ITS + * N Y DWC MSI Ctrl + SMMU + * N N DWC MSI Ctrl + */ + if (!err_i && !err_m) + if ((sid_i & IMX95_SID_MASK) !=3D (sid_m & IMX95_SID_MASK)) { + dev_err(dev, "its and iommu stream id miss match, please check dts file= \n"); + return -EINVAL; + } + + /* + * Both iommu-map and msi-map not exist, use dwc built-in MSI + * controller, do nothing here. + */ + if (err_i && err_m) + return 0; + + if (!err_i) + return imx_pcie_add_lut(imx_pcie, rid, sid_i); + else if (!err_m) + /* Hardware auto add 2 bit controller id ahead of stream ID */ + return imx_pcie_add_lut(imx_pcie, rid, sid_m & IMX95_SID_MASK); + + return 0; +} + +static void imx_pcie_disable_device(struct pci_host_bridge *bridge, struct= pci_dev *pdev) +{ + struct imx_pcie *imx_pcie; + + imx_pcie =3D to_imx_pcie(to_dw_pcie_from_pp(bridge->sysdata)); + imx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev)); +} + static int imx_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); @@ -941,6 +1108,11 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) } } =20 + if (pp->bridge && imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) { + pp->bridge->enable_device =3D imx_pcie_enable_device; + pp->bridge->disable_device =3D imx_pcie_disable_device; + } + imx_pcie_assert_core_reset(imx_pcie); =20 if (imx_pcie->drvdata->init_phy) @@ -1292,6 +1464,8 @@ static int imx_pcie_probe(struct platform_device *pde= v) imx_pcie->pci =3D pci; imx_pcie->drvdata =3D of_device_get_match_data(dev); =20 + mutex_init(&imx_pcie->lock); + /* Find the PHY if one is defined, only imx7d uses it */ np =3D of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); if (np) { @@ -1587,7 +1761,8 @@ static const struct imx_pcie_drvdata drvdata[] =3D { }, [IMX95] =3D { .variant =3D IMX95, - .flags =3D IMX_PCIE_FLAG_HAS_SERDES, + .flags =3D IMX_PCIE_FLAG_HAS_SERDES | + IMX_PCIE_FLAG_HAS_LUT, .clk_names =3D imx8mq_clks, .clks_cnt =3D ARRAY_SIZE(imx8mq_clks), .ltssm_off =3D IMX95_PE0_GEN_CTRL_3, --=20 2.34.1