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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241101-imx-emmc-reset-v3-1-184965eed476@solid-run.com> References: <20241101-imx-emmc-reset-v3-0-184965eed476@solid-run.com> In-Reply-To: <20241101-imx-emmc-reset-v3-0-184965eed476@solid-run.com> To: Adrian Hunter , Haibo Chen , Ulf Hansson , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: Mikhail Anikin , Jon Nettleton , Yazan Shhady , Rabeeh Khoury , imx@lists.linux.dev, linux-mmc@vger.kernel.org, s32@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Josua Mayer X-Mailer: b4 0.14.2 X-ClientProxiedBy: FR0P281CA0198.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:ad::8) To AM9PR04MB7586.eurprd04.prod.outlook.com (2603:10a6:20b:2d5::17) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM9PR04MB7586:EE_|GVXPR04MB10519:EE_ X-MS-Office365-Filtering-Correlation-Id: 7771ca19-1c55-4594-60a6-08dcfa6a43bd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|52116014|1800799024|38350700014; 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Documentation is available in NXP i.MX6Q Reference Manual. Implement the hw_reset function in sdhci_ops asserting reset for at least 1us and waiting at least 200us after deassertion. Lower bounds are based on: JEDEC Standard No. 84-B51, 6.15.10 H/W Reset Operation, page 159. Upper bounds are chosen allowing flexibility to the scheduler. Tested on SolidRun i.MX8DXL SoM with a scope, and confirmed that eMMC is still accessible after boot: - eMMC extcsd has RST_N_FUNCTION=3D0x01 - sdhc node has cap-mmc-hw-reset - pinmux set for EMMC0_RESET_B - Linux v5.15 Signed-off-by: Josua Mayer --- drivers/mmc/host/sdhci-esdhc-imx.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-es= dhc-imx.c index 8f0bc6dca2b0402fd2a0695903cf261a5b4e19dc..f106e291c276d0c8063e9ac59a1= 26acf5e9e239e 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -31,6 +31,7 @@ #include "cqhci.h" =20 #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f +#define ESDHC_SYS_CTRL_IPP_RST_N BIT(23) #define ESDHC_CTRL_D3CD 0x08 #define ESDHC_BURST_LEN_EN_INCR (1 << 27) /* VENDOR SPEC register */ @@ -1402,6 +1403,17 @@ static u32 esdhc_cqhci_irq(struct sdhci_host *host, = u32 intmask) return 0; } =20 +static void esdhc_hw_reset(struct sdhci_host *host) +{ + esdhc_clrset_le(host, ESDHC_SYS_CTRL_IPP_RST_N, 0, ESDHC_SYSTEM_CONTROL); + /* eMMC spec requires minimum 1us, here delay between 1-10us */ + usleep_range(1, 10); + esdhc_clrset_le(host, ESDHC_SYS_CTRL_IPP_RST_N, + ESDHC_SYS_CTRL_IPP_RST_N, ESDHC_SYSTEM_CONTROL); + /* eMMC spec requires minimum 200us, here delay between 200-300us */ + usleep_range(200, 300); +} + static struct sdhci_ops sdhci_esdhc_ops =3D { .read_l =3D esdhc_readl_le, .read_w =3D esdhc_readw_le, @@ -1420,6 +1432,7 @@ static struct sdhci_ops sdhci_esdhc_ops =3D { .reset =3D esdhc_reset, .irq =3D esdhc_cqhci_irq, .dump_vendor_regs =3D esdhc_dump_debug_regs, + .hw_reset =3D esdhc_hw_reset, }; =20 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata =3D { --=20 2.43.0