From nobody Sun Nov 24 22:33:19 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF9D8184542; Fri, 1 Nov 2024 14:25:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730471119; cv=none; b=sSrEw7lGMMw383F79yuEvv9QurPl5E8PEerSgcrBKVpELHxfdfcewa/x596GpvaCd864SV5Pte9L9C4X93Rd0QMHDmo0kYEX628jmnwz885g5CejwGaDzH43Qg6Zp4HVoSpVRoxO94e86a498CAXK4acZbbCNFe+mM9pFP+/DOc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730471119; c=relaxed/simple; bh=Dne8V2QfqkzN1YBXZsevP5jkNB9Lrxzwn56NCsyipPA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NnZJIZw1C/OZLmj5qxS/+boVXt3p+bVmAhTqMSndPKxCu1tWR1dCmCnmJ3KrSmGYW8SDj1QTelLo9fc9MeBd0z6xfDZX47wWEFpqqUqXtv5MIIuI5llSFYcL5VI6so/1zCnaUcZhFpzjqEbVxE1ZAYjKoIEWwM+eXF0+/FWH2jo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kZT8hNhM; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kZT8hNhM" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8230CC4CED3; Fri, 1 Nov 2024 14:25:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730471118; bh=Dne8V2QfqkzN1YBXZsevP5jkNB9Lrxzwn56NCsyipPA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=kZT8hNhMeuQgUAvsSiCso93KI2QxkMTedkDLuEkkOFeDIpwCrqppsYrfvu30cIezv spw0AmoVDkrxqm6E/TA60ErVd5CeRNoKPQP7ei5MC5JSYPivzV/poKbfs8bcoDIl/8 o126ZjkOZFKWpf1jxE/tnxZSt6tm1v4SbPAw7mCWvB0mkNG/lObYfJTyYAKwdOEmZs HZEa8UR5NeRdp4ZWRvrFgtryxu/s8qNoVg8mAORluxaPzmW5BrWecJJxhEfJLxwSOc xmSajcueNgXvEUyu74rsACtBnpYyOgo5TUS75omkCFPx17Ycr73bg/EwI5SqHkPkTe 1O/uK5xWeRYVw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6542BE6F061; Fri, 1 Nov 2024 14:25:18 +0000 (UTC) From: Janne Grunau via B4 Relay Date: Fri, 01 Nov 2024 15:25:03 +0100 Subject: [PATCH v2 1/3] dt-bindings: spi: apple,spi: Add binding for Apple SPI controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241101-asahi-spi-v2-1-763a8a84d834@jannau.net> References: <20241101-asahi-spi-v2-0-763a8a84d834@jannau.net> In-Reply-To: <20241101-asahi-spi-v2-0-763a8a84d834@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2079; i=j@jannau.net; s=yk2024; h=from:subject:message-id; bh=/RFcpEoBMNWg7lClrxLf6RcMZcKkYFii4Yno81onXTg=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhnSVJ2eqaw7b7b0V2myXWnAmeqbrv0Ole50l0tc99d39a fOvw5FHOkpZGMS4GGTFFFmStF92MKyuUYypfRAGM4eVCWQIAxenAEwkTZ6RYYmA1bKPOavc2p1D 22ub5t2c8n7uwlvXTDetrM3pU8yKeM3wh2fHlIV3lTyOyvrW/egU3rGE9cb2eyJLvm5+JMXjwvB Vmh0A X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 X-Endpoint-Received: by B4 Relay for j@jannau.net/yk2024 with auth_id=264 X-Original-From: Janne Grunau Reply-To: j@jannau.net From: Hector Martin The Apple SPI controller is present in SoCs such as the M1 (t8103) and M1 Pro/Max (t600x). This controller uses one IRQ and one clock, and doesn't need any special properties, so the binding is trivial. Signed-off-by: Hector Martin Signed-off-by: Janne Grunau --- .../devicetree/bindings/spi/apple,spi.yaml | 62 ++++++++++++++++++= ++++ 1 file changed, 62 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/apple,spi.yaml b/Documen= tation/devicetree/bindings/spi/apple,spi.yaml new file mode 100644 index 0000000000000000000000000000000000000000..0f280370cca9d82ce7ce72da53a= 144b257f7bdc2 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/apple,spi.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/apple,spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple ARM SoC SPI controller + +allOf: + - $ref: "spi-controller.yaml#" + +maintainers: + - Hector Martin + +properties: + compatible: + items: + - enum: + - apple,t8103-spi + - apple,t8112-spi + - apple,t6000-spi + - const: apple,spi + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + spi: spi@39b104000 { + compatible =3D "apple,t6000-spi", "apple,spi"; + reg =3D <0x3 0x9b104000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk>; + }; + }; --=20 2.47.0