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Fri, 01 Nov 2024 15:10:44 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4A1FAhnD004688 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 1 Nov 2024 15:10:43 GMT Received: from [10.213.111.143] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 1 Nov 2024 08:10:39 -0700 From: Akhil P Oommen Date: Fri, 1 Nov 2024 20:40:17 +0530 Subject: [PATCH] drm/msm/a6xx: Add support for Adreno 612 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241101-a612-gpu-support-v1-1-bdfe8f6d9306@quicinc.com> X-B4-Tracking: v=1; b=H4sIAFjvJGcC/yXMQQ6DIBCF4auYWZeEATpKr9K4QBksC5WCNk2Md y+py+8l7z+gcI5c4NEckPkTS1yXCrw1ML7cMrGIvhqUVAalRuEIlZjSLsqe0po34UlrGbD1EgP UW8oc4veffPaXM7/3Wt6uEQZXWIzrPMft0RhHwUsio11w1trOOsk0dKZjVHdpLbVGqXaA/jx/F HQtAa4AAAA= To: Rob Clark , Sean Paul , "Konrad Dybcio" , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , "Simona Vetter" CC: , , , , Jie Zhang , Akhil P Oommen X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; 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A612 falls under ADRENO_6XX_GEN1 family and is a cut down version of A615 GPU. A612 has a new IP called Reduced Graphics Management Unit or RGMU which is a small state machine which helps to toggle GX GDSC (connected to CX rail) to implement IFPC feature. It doesn't support any other features of a full fledged GMU like clock control, resource voting to rpmh etc. So we need linux clock driver support like other gmu-wrapper implementations to control gpu core clock and gpu GX gdsc. Since there is no benefit with enabling RGMU at the moment, RGMU is entirely skipped in this patch. Signed-off-by: Jie Zhang Signed-off-by: Akhil P Oommen Reviewed-by: Konrad Dybcio --- Mesa support is already available for A612. Verified Glmark2 with weston. Some dependencies for the devicetree change are not yet available in the mailing lists. I will send it out as a separate patch later. --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 15 +++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 28 +++++++++++++++++++++------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 11 ++++++++--- 3 files changed, 44 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index 0c560e84ad5a..234083b69844 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -704,6 +704,21 @@ static const struct adreno_info a6xx_gpus[] =3D { { 157, 3 }, { 127, 4 }, ), + }, { + .chip_ids =3D ADRENO_CHIP_IDS(0x06010200), + .family =3D ADRENO_6XX_GEN1, + .fw =3D { + [ADRENO_FW_SQE] =3D "a630_sqe.fw", + }, + .gmem =3D (SZ_128K + SZ_4K), + .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, + .init =3D a6xx_gpu_init, + .a6xx =3D &(const struct a6xx_info) { + .hwcg =3D a612_hwcg, + .protect =3D &a630_protect, + .gmu_cgc_mode =3D 0x00000022, + .prim_fifo_threshold =3D 0x00080000, + }, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x06010500), .family =3D ADRENO_6XX_GEN1, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 019610341df1..f69607267262 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -504,15 +504,26 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool s= tate) =20 if (adreno_is_a630(adreno_gpu)) clock_cntl_on =3D 0x8aa8aa02; - else if (adreno_is_a610(adreno_gpu)) + else if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu)) clock_cntl_on =3D 0xaaa8aa82; else if (adreno_is_a702(adreno_gpu)) clock_cntl_on =3D 0xaaaaaa82; else clock_cntl_on =3D 0x8aa8aa82; =20 - cgc_delay =3D adreno_is_a615_family(adreno_gpu) ? 0x111 : 0x10111; - cgc_hyst =3D adreno_is_a615_family(adreno_gpu) ? 0x555 : 0x5555; + if (adreno_is_a612(adreno_gpu)) + cgc_delay =3D 0x11; + else if (adreno_is_a615_family(adreno_gpu)) + cgc_delay =3D 0x111; + else + cgc_delay =3D 0x10111; + + if (adreno_is_a612(adreno_gpu)) + cgc_hyst =3D 0x55; + else if (adreno_is_a615_family(adreno_gpu)) + cgc_delay =3D 0x555; + else + cgc_delay =3D 0x5555; =20 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); @@ -600,6 +611,9 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gp= u) gpu->ubwc_config.ubwc_swizzle =3D 0x7; } =20 + if (adreno_is_a612(gpu)) + gpu->ubwc_config.highest_bank_bit =3D 13; + if (adreno_is_a618(gpu)) gpu->ubwc_config.highest_bank_bit =3D 14; =20 @@ -1165,7 +1179,7 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); =20 /* Setting the mem pool size */ - if (adreno_is_a610(adreno_gpu)) { + if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu)) { gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48); gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47); } else if (adreno_is_a702(adreno_gpu)) { @@ -1199,7 +1213,7 @@ static int hw_init(struct msm_gpu *gpu) =20 /* Enable fault detection */ if (adreno_is_a730(adreno_gpu) || - adreno_is_a740_family(adreno_gpu)) + adreno_is_a740_family(adreno_gpu) || adreno_is_a612(adreno_gpu)) gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0xcfff= ff); else if (adreno_is_a690(adreno_gpu)) gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x4fff= ff); @@ -1864,7 +1878,7 @@ static void a7xx_llc_activate(struct a6xx_gpu *a6xx_g= pu) static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu) { /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ - if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) + if (adreno_has_gmu_wrapper(&a6xx_gpu->base) && !adreno_is_a612(&a6xx_gpu-= >base)) return; =20 llcc_slice_putd(a6xx_gpu->llc_slice); @@ -1877,7 +1891,7 @@ static void a6xx_llc_slices_init(struct platform_devi= ce *pdev, struct device_node *phandle; =20 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ - if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) + if (adreno_has_gmu_wrapper(&a6xx_gpu->base) && !adreno_is_a612(&a6xx_gpu-= >base)) return; =20 /* diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index e71f420f8b3a..5cde84817a03 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -420,6 +420,11 @@ static inline int adreno_is_a610(const struct adreno_g= pu *gpu) return adreno_is_revn(gpu, 610); } =20 +static inline int adreno_is_a612(const struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] =3D=3D 0x06010200; +} + static inline int adreno_is_a618(const struct adreno_gpu *gpu) { return adreno_is_revn(gpu, 618); @@ -489,9 +494,9 @@ static inline int adreno_is_a610_family(const struct ad= reno_gpu *gpu) { if (WARN_ON_ONCE(!gpu->info)) return false; - - /* TODO: A612 */ - return adreno_is_a610(gpu) || adreno_is_a702(gpu); + return adreno_is_a610(gpu) || + adreno_is_a702(gpu) || + adreno_is_a612(gpu); } =20 /* TODO: 615/616 */ --- base-commit: 4a6fd06643afa99989a0e6b848e125099674227b change-id: 20241031-a612-gpu-support-d6330f17d01f Best regards, --=20 Akhil P Oommen