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AJvYcCVCCWWblexOivZKk0/HvNYeMy3FxVHlYL5OORj7Pfn2Czp5QTUYiEPf0AWehOWu7UXy63ScYglirvr92Lo=@vger.kernel.org X-Gm-Message-State: AOJu0Yw+LoOchRq0cH4zQ981weBbP1iJmreRZWJqLU80ta7EuVLI2cMt 8iETp47vsKe/i/etOuDVjyY+byQ4FXyd7PVbkUORi1TuaGEZNoOHf5cTB/JVJno= X-Google-Smtp-Source: AGHT+IFz1+UYr4hSStn9sPc2pavAOWRlpkPtO9pHTEtEu9q/PXw/hM8RRdJlrb371+ewLtzLK5Lt6Q== X-Received: by 2002:a05:600c:3587:b0:42c:c401:6d67 with SMTP id 5b1f17b1804b1-4327b6f464amr27709765e9.6.1730386848476; Thu, 31 Oct 2024 08:00:48 -0700 (PDT) Received: from gpeter-l.lan ([145.224.65.232]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-431bd8e8524sm59163225e9.5.2024.10.31.08.00.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Oct 2024 08:00:48 -0700 (PDT) From: Peter Griffin To: alim.akhtar@samsung.com, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, avri.altman@wdc.com, bvanassche@acm.org, krzk@kernel.org Cc: tudor.ambarus@linaro.org, ebiggers@kernel.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, linux-scsi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Peter Griffin Subject: [PATCH v3 09/14] scsi: ufs: exynos: add gs101_ufs_drv_init() hook and enable WriteBooster Date: Thu, 31 Oct 2024 15:00:28 +0000 Message-ID: <20241031150033.3440894-10-peter.griffin@linaro.org> X-Mailer: git-send-email 2.47.0.163.g1226f6d8fa-goog In-Reply-To: <20241031150033.3440894-1-peter.griffin@linaro.org> References: <20241031150033.3440894-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Factor out the common code into a new exynos_ufs_shareability() function and provide a dedicated gs101_drv_init() hook. This allows us to enable WriteBooster capability (UFSHCD_CAP_WB_EN) in a way that doesn't effect other SoCs supported in this driver. WriteBooster improves write speeds by enabling a pseudo SLC cache. Using the `fio seqwrite` test we can achieve speeds of 945MB/s with this feature enabled (until the cache is exhausted) before dropping back to ~260MB/s (which are the speeds we see without the WriteBooster feature enabled). Assuming the UFSHCD_CAP_WB_EN capability is set by the host then WriteBooster can also be enabled and disabled via sysfs so it is possible for the system to only enable it when extra write performance is required. Signed-off-by: Peter Griffin Reviewed-by: Tudor Ambarus --- v3: update to new drv_init() protoype --- drivers/ufs/host/ufs-exynos.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 378c16d905c1..d59e1933b64e 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -198,7 +198,7 @@ static inline void exynos_ufs_ungate_clks(struct exynos= _ufs *ufs) exynos_ufs_ctrl_clkstop(ufs, false); } =20 -static int exynosauto_ufs_drv_init(struct exynos_ufs *ufs) +static int exynos_ufs_shareability(struct exynos_ufs *ufs) { /* IO Coherency setting */ if (ufs->sysreg) { @@ -210,6 +210,21 @@ static int exynosauto_ufs_drv_init(struct exynos_ufs *= ufs) return 0; } =20 +static int gs101_ufs_drv_init(struct exynos_ufs *ufs) +{ + struct ufs_hba *hba =3D ufs->hba; + + /* Enable WriteBooster */ + hba->caps |=3D UFSHCD_CAP_WB_EN; + + return exynos_ufs_shareability(ufs); +} + +static int exynosauto_ufs_drv_init(struct exynos_ufs *ufs) +{ + return exynos_ufs_shareability(ufs); +} + static int exynosauto_ufs_post_hce_enable(struct exynos_ufs *ufs) { struct ufs_hba *hba =3D ufs->hba; @@ -2120,7 +2135,7 @@ static const struct exynos_ufs_drv_data gs101_ufs_drv= s =3D { .opts =3D EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR | EXYNOS_UFS_OPT_UFSPR_SECURE | EXYNOS_UFS_OPT_TIMER_TICK_SELECT, - .drv_init =3D exynosauto_ufs_drv_init, + .drv_init =3D gs101_ufs_drv_init, .pre_link =3D gs101_ufs_pre_link, .post_link =3D gs101_ufs_post_link, .pre_pwr_change =3D gs101_ufs_pre_pwr_change, --=20 2.47.0.163.g1226f6d8fa-goog