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Thu, 31 Oct 2024 07:21:38 -0700 From: Besar Wicaksono To: , , , , CC: , , , , , , , , , Besar Wicaksono Subject: [PATCH v2 3/4] perf: arm_cspmu: nvidia: enable NVLINK-C2C port filtering Date: Thu, 31 Oct 2024 14:21:17 +0000 Message-ID: <20241031142118.1865965-4-bwicaksono@nvidia.com> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20241031142118.1865965-1-bwicaksono@nvidia.com> References: <20241031142118.1865965-1-bwicaksono@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DB:EE_|CY8PR12MB7193:EE_ X-MS-Office365-Filtering-Correlation-Id: 4d90047c-8589-4397-e0ff-08dcf9b75fbf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?GyyMkssJUU0BG8AcPFb+2p+RGFXvvG0hM0oWQoTpNPBDlvhZ7b2cEmOn7iXN?= =?us-ascii?Q?K+zEWbzPDWyuzyj9R8YMhLMIPpFfoj5kpI6zl2fwHCgHvfRvxqGXImKNEV0K?= =?us-ascii?Q?EnltL8NP+wxY0kYAbRTch+Tmb38WQB2SOGahv4JhttBrjtHd+iy29Sj/MPjW?= =?us-ascii?Q?cWWbATF8HoYgrPdX2RIehxtX6tFDc5hfOyEkrgw4nuP3HNRVxbJ7J+FL+jCy?= =?us-ascii?Q?wNtrnRBcq4BgxYDDl5LNthwKqSjxjvjJEe/cmPkpqcEP9UhUhMBvuuOhoJKC?= =?us-ascii?Q?l2sfNG9I4OxmswViePuP8FB9/pxMRQRB5jiBsuAbnrDyUGyfgGa2GLZj5wIX?= =?us-ascii?Q?vAqDMfhE5WvO6KXJBwAeBAJBJYcZfjSWi0cWOCN/RT/xwsjxbbTbNC2REy1D?= =?us-ascii?Q?bQs2Q9UYM8I1gy7amwCkKemcQRzNCRMRrrZWXYEE55W0VHEDmyozeaOQ6Jms?= =?us-ascii?Q?qX7HG+lIzECjNQOS8hLQ23THkLpA9zEcFooAxk3QgnzbjVHGEYhwD/RTIOTj?= =?us-ascii?Q?g5AZMPht0AWfsyuqkcLZRSN2qnBxUiDw8vHh180oOp6b7RDDJ3zCUOw46eeV?= =?us-ascii?Q?303xla90uAj1T84bTjyJfqKOmTTJCYvfGevcrUIg/HIzGw2KFFA43l8nd+1H?= =?us-ascii?Q?+RlcNCNC501EMKmEngfvJylQ/9HuPJMk3sN99KMxR2hBxfBL+kepDuDBdJRs?= =?us-ascii?Q?mXgPQIo1a7nyAB2v4RPCf+VgOVuLyVJZq6XO5QIQwocbBer03WBbijRQZLFf?= =?us-ascii?Q?kgf3SoiT9RNzO+Dih9SOVdpihyZYea7cJC0VRr4/cQEqQK/BSYGXuyovAvFB?= =?us-ascii?Q?c6LjxQaLT0HJe8+CBqODyQoNQCWvWe/+EsqS5aJ1aUUEIejLxaM5Fa/dGdxE?= =?us-ascii?Q?cN64xgjzZPG7AZjCuSJ+shw4zYACb1I3ucgOd/mmFaesRFzYU7cZzMp3bA87?= =?us-ascii?Q?FRwmyOeA45aHetPig1qDlyDuIVOjtx2jL5Q3h0SSDJ17cnzOeySdHD16KMY9?= =?us-ascii?Q?UQQ8L+vBw+lXO0AhId349DT/pHHrQqzv2fiD4l/wnMv+kHl6QNqpkPakw8Gt?= =?us-ascii?Q?Ye1jTkOz5IVvVAiLhap5q0Qo0W35y/3XXExgCQn0xSSsbXXvCb6UkZxQyfT6?= =?us-ascii?Q?1KzH2eerr+k95UUWpow5SGHU03cKfSa3YR8wT9nugsJOoghlx0dhOwcBwXkT?= =?us-ascii?Q?+Dq5Y//JTEkx5euE97sxUuIhEdQ8RzP3zt1fKMK3rTCppHmFlHLMY+g5/tiX?= =?us-ascii?Q?ZeiEmNa6t3uIr53BIUV1wWeTfqx4bMRQiphYZreH6uJH6vM6RQLzMxLf+1aW?= =?us-ascii?Q?pOA5PiR5XHE8tEyd+1BGjU8Wso6Wkma96IK2xyewT5tlNZxCuopoI7rSiq3V?= =?us-ascii?Q?BUbJ2c/w0ApVYbHEFc8H9swQmdF4LfDBeJsETEfrUNUiOABHDA=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2024 14:21:55.8947 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4d90047c-8589-4397-e0ff-08dcf9b75fbf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DB.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7193 Content-Type: text/plain; charset="utf-8" Enable NVLINK-C2C port filtering to distinguish traffic from different GPUs connected to NVLINK-C2C. Signed-off-by: Besar Wicaksono --- Documentation/admin-guide/perf/nvidia-pmu.rst | 30 +++++++++++++++++++ drivers/perf/arm_cspmu/nvidia_cspmu.c | 5 ++-- 2 files changed, 33 insertions(+), 2 deletions(-) diff --git a/Documentation/admin-guide/perf/nvidia-pmu.rst b/Documentation/= admin-guide/perf/nvidia-pmu.rst index 6e8ee0fcf471..4cfc806070d7 100644 --- a/Documentation/admin-guide/perf/nvidia-pmu.rst +++ b/Documentation/admin-guide/perf/nvidia-pmu.rst @@ -86,6 +86,21 @@ Example usage: =20 perf stat -a -e nvidia_nvlink_c2c0_pmu_3/event=3D0x0/ =20 +The NVLink-C2C has two ports that can be connected to one GPU (occupying b= oth +ports) or to two GPUs (one GPU per port). The user can use "port" bitmap +parameter to select the port(s) to monitor. Each bit represents the port n= umber, +e.g. "port=3D0x1" corresponds to port 0 and "port=3D0x3" is for port 0 and= 1. + +Example for port filtering: + +* Count event id 0x0 from the GPU connected with socket 0 on port 0:: + + perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=3D0x0,port=3D0x1/ + +* Count event id 0x0 from the GPUs connected with socket 0 on port 0 and p= ort 1:: + + perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=3D0x0,port=3D0x3/ + NVLink-C2C1 PMU ------------------- =20 @@ -116,6 +131,21 @@ Example usage: =20 perf stat -a -e nvidia_nvlink_c2c1_pmu_3/event=3D0x0/ =20 +The NVLink-C2C has two ports that can be connected to one GPU (occupying b= oth +ports) or to two GPUs (one GPU per port). The user can use "port" bitmap +parameter to select the port(s) to monitor. Each bit represents the port n= umber, +e.g. "port=3D0x1" corresponds to port 0 and "port=3D0x3" is for port 0 and= 1. + +Example for port filtering: + +* Count event id 0x0 from the GPU connected with socket 0 on port 0:: + + perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=3D0x0,port=3D0x1/ + +* Count event id 0x0 from the GPUs connected with socket 0 on port 0 and p= ort 1:: + + perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=3D0x0,port=3D0x3/ + CNVLink PMU --------------- =20 diff --git a/drivers/perf/arm_cspmu/nvidia_cspmu.c b/drivers/perf/arm_cspmu= /nvidia_cspmu.c index ea2d44adfa7c..7ab7d76e4ca1 100644 --- a/drivers/perf/arm_cspmu/nvidia_cspmu.c +++ b/drivers/perf/arm_cspmu/nvidia_cspmu.c @@ -130,6 +130,7 @@ static struct attribute *pcie_pmu_format_attrs[] =3D { =20 static struct attribute *nvlink_c2c_pmu_format_attrs[] =3D { ARM_CSPMU_FORMAT_EVENT_ATTR, + ARM_CSPMU_FORMAT_ATTR(port, "config1:0-1"), NULL, }; =20 @@ -210,7 +211,7 @@ static const struct nv_cspmu_match nv_cspmu_match[] =3D= { { .prodid =3D 0x104, .prodid_mask =3D NV_PRODID_MASK, - .filter_mask =3D 0x0, + .filter_mask =3D NV_NVL_C2C_FILTER_ID_MASK, .filter_default_val =3D NV_NVL_C2C_FILTER_ID_MASK, .name_pattern =3D "nvidia_nvlink_c2c1_pmu_%u", .name_fmt =3D NAME_FMT_SOCKET, @@ -220,7 +221,7 @@ static const struct nv_cspmu_match nv_cspmu_match[] =3D= { { .prodid =3D 0x105, .prodid_mask =3D NV_PRODID_MASK, - .filter_mask =3D 0x0, + .filter_mask =3D NV_NVL_C2C_FILTER_ID_MASK, .filter_default_val =3D NV_NVL_C2C_FILTER_ID_MASK, .name_pattern =3D "nvidia_nvlink_c2c0_pmu_%u", .name_fmt =3D NAME_FMT_SOCKET, --=20 2.34.1