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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2024 14:21:44.9750 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d90ab3f3-90fd-4f5e-0bea-08dcf9b75940 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000141.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB9460 Content-Type: text/plain; charset="utf-8" Remove unsupported events under SCF PMU. Signed-off-by: Besar Wicaksono --- drivers/perf/arm_cspmu/nvidia_cspmu.c | 64 --------------------------- 1 file changed, 64 deletions(-) diff --git a/drivers/perf/arm_cspmu/nvidia_cspmu.c b/drivers/perf/arm_cspmu= /nvidia_cspmu.c index d0ef611240aa..ea2d44adfa7c 100644 --- a/drivers/perf/arm_cspmu/nvidia_cspmu.c +++ b/drivers/perf/arm_cspmu/nvidia_cspmu.c @@ -54,65 +54,24 @@ static struct attribute *scf_pmu_event_attrs[] =3D { ARM_CSPMU_EVENT_ATTR(scf_cache_wb, 0xF3), =20 NV_CSPMU_EVENT_ATTR_4(socket, rd_data, 0x101), - NV_CSPMU_EVENT_ATTR_4(socket, dl_rsp, 0x105), NV_CSPMU_EVENT_ATTR_4(socket, wb_data, 0x109), - NV_CSPMU_EVENT_ATTR_4(socket, ev_rsp, 0x10d), - NV_CSPMU_EVENT_ATTR_4(socket, prb_data, 0x111), =20 NV_CSPMU_EVENT_ATTR_4(socket, rd_outstanding, 0x115), - NV_CSPMU_EVENT_ATTR_4(socket, dl_outstanding, 0x119), - NV_CSPMU_EVENT_ATTR_4(socket, wb_outstanding, 0x11d), - NV_CSPMU_EVENT_ATTR_4(socket, wr_outstanding, 0x121), - NV_CSPMU_EVENT_ATTR_4(socket, ev_outstanding, 0x125), - NV_CSPMU_EVENT_ATTR_4(socket, prb_outstanding, 0x129), =20 NV_CSPMU_EVENT_ATTR_4(socket, rd_access, 0x12d), - NV_CSPMU_EVENT_ATTR_4(socket, dl_access, 0x131), NV_CSPMU_EVENT_ATTR_4(socket, wb_access, 0x135), NV_CSPMU_EVENT_ATTR_4(socket, wr_access, 0x139), - NV_CSPMU_EVENT_ATTR_4(socket, ev_access, 0x13d), - NV_CSPMU_EVENT_ATTR_4(socket, prb_access, 0x141), - - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_rd_data, 0x145), - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_rd_access, 0x149), - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_wb_access, 0x14d), - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_rd_outstanding, 0x151), - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_wr_outstanding, 0x155), - - NV_CSPMU_EVENT_ATTR_4(ocu, rem_rd_data, 0x159), - NV_CSPMU_EVENT_ATTR_4(ocu, rem_rd_access, 0x15d), - NV_CSPMU_EVENT_ATTR_4(ocu, rem_wb_access, 0x161), - NV_CSPMU_EVENT_ATTR_4(ocu, rem_rd_outstanding, 0x165), - NV_CSPMU_EVENT_ATTR_4(ocu, rem_wr_outstanding, 0x169), =20 ARM_CSPMU_EVENT_ATTR(gmem_rd_data, 0x16d), ARM_CSPMU_EVENT_ATTR(gmem_rd_access, 0x16e), ARM_CSPMU_EVENT_ATTR(gmem_rd_outstanding, 0x16f), - ARM_CSPMU_EVENT_ATTR(gmem_dl_rsp, 0x170), - ARM_CSPMU_EVENT_ATTR(gmem_dl_access, 0x171), - ARM_CSPMU_EVENT_ATTR(gmem_dl_outstanding, 0x172), ARM_CSPMU_EVENT_ATTR(gmem_wb_data, 0x173), ARM_CSPMU_EVENT_ATTR(gmem_wb_access, 0x174), - ARM_CSPMU_EVENT_ATTR(gmem_wb_outstanding, 0x175), - ARM_CSPMU_EVENT_ATTR(gmem_ev_rsp, 0x176), - ARM_CSPMU_EVENT_ATTR(gmem_ev_access, 0x177), - ARM_CSPMU_EVENT_ATTR(gmem_ev_outstanding, 0x178), ARM_CSPMU_EVENT_ATTR(gmem_wr_data, 0x179), - ARM_CSPMU_EVENT_ATTR(gmem_wr_outstanding, 0x17a), ARM_CSPMU_EVENT_ATTR(gmem_wr_access, 0x17b), =20 NV_CSPMU_EVENT_ATTR_4(socket, wr_data, 0x17c), =20 - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_wr_data, 0x180), - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_wb_data, 0x184), - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_wr_access, 0x188), - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_wb_outstanding, 0x18c), - - NV_CSPMU_EVENT_ATTR_4(ocu, rem_wr_data, 0x190), - NV_CSPMU_EVENT_ATTR_4(ocu, rem_wb_data, 0x194), - NV_CSPMU_EVENT_ATTR_4(ocu, rem_wr_access, 0x198), - NV_CSPMU_EVENT_ATTR_4(ocu, rem_wb_outstanding, 0x19c), - ARM_CSPMU_EVENT_ATTR(gmem_wr_total_bytes, 0x1a0), ARM_CSPMU_EVENT_ATTR(remote_socket_wr_total_bytes, 0x1a1), ARM_CSPMU_EVENT_ATTR(remote_socket_rd_data, 0x1a2), @@ -122,35 +81,12 @@ static struct attribute *scf_pmu_event_attrs[] =3D { ARM_CSPMU_EVENT_ATTR(cmem_rd_data, 0x1a5), ARM_CSPMU_EVENT_ATTR(cmem_rd_access, 0x1a6), ARM_CSPMU_EVENT_ATTR(cmem_rd_outstanding, 0x1a7), - ARM_CSPMU_EVENT_ATTR(cmem_dl_rsp, 0x1a8), - ARM_CSPMU_EVENT_ATTR(cmem_dl_access, 0x1a9), - ARM_CSPMU_EVENT_ATTR(cmem_dl_outstanding, 0x1aa), ARM_CSPMU_EVENT_ATTR(cmem_wb_data, 0x1ab), ARM_CSPMU_EVENT_ATTR(cmem_wb_access, 0x1ac), - ARM_CSPMU_EVENT_ATTR(cmem_wb_outstanding, 0x1ad), - ARM_CSPMU_EVENT_ATTR(cmem_ev_rsp, 0x1ae), - ARM_CSPMU_EVENT_ATTR(cmem_ev_access, 0x1af), - ARM_CSPMU_EVENT_ATTR(cmem_ev_outstanding, 0x1b0), ARM_CSPMU_EVENT_ATTR(cmem_wr_data, 0x1b1), - ARM_CSPMU_EVENT_ATTR(cmem_wr_outstanding, 0x1b2), - - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_rd_data, 0x1b3), - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_rd_access, 0x1b7), - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_wb_access, 0x1bb), - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_rd_outstanding, 0x1bf), - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_wr_outstanding, 0x1c3), - - ARM_CSPMU_EVENT_ATTR(ocu_prb_access, 0x1c7), - ARM_CSPMU_EVENT_ATTR(ocu_prb_data, 0x1c8), - ARM_CSPMU_EVENT_ATTR(ocu_prb_outstanding, 0x1c9), =20 ARM_CSPMU_EVENT_ATTR(cmem_wr_access, 0x1ca), =20 - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_wr_access, 0x1cb), - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_wb_data, 0x1cf), - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_wr_data, 0x1d3), - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_wb_outstanding, 0x1d7), - ARM_CSPMU_EVENT_ATTR(cmem_wr_total_bytes, 0x1db), =20 ARM_CSPMU_EVENT_ATTR(cycles, ARM_CSPMU_EVT_CYCLES_DEFAULT), --=20 2.34.1 From nobody Sun Nov 24 23:56:40 2024 Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2069.outbound.protection.outlook.com [40.107.100.69]) (using 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X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6276 Content-Type: text/plain; charset="utf-8" Fix typos to the sysfs path referenced by NVIDIA uncore pmu kernel doc. Signed-off-by: Besar Wicaksono --- Documentation/admin-guide/perf/nvidia-pmu.rst | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/Documentation/admin-guide/perf/nvidia-pmu.rst b/Documentation/= admin-guide/perf/nvidia-pmu.rst index 2e0d47cfe7ea..6e8ee0fcf471 100644 --- a/Documentation/admin-guide/perf/nvidia-pmu.rst +++ b/Documentation/admin-guide/perf/nvidia-pmu.rst @@ -34,7 +34,7 @@ strongly-ordered (SO) PCIE write traffic to local/remote = memory. Please see traffic coverage. =20 The events and configuration options of this PMU device are described in s= ysfs, -see /sys/bus/event_sources/devices/nvidia_scf_pmu_. +see /sys/bus/event_source/devices/nvidia_scf_pmu_. =20 Example usage: =20 @@ -66,7 +66,7 @@ Please see :ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Secti= on` for more info about the PMU traffic coverage. =20 The events and configuration options of this PMU device are described in s= ysfs, -see /sys/bus/event_sources/devices/nvidia_nvlink_c2c0_pmu_. +see /sys/bus/event_source/devices/nvidia_nvlink_c2c0_pmu_. =20 Example usage: =20 @@ -96,7 +96,7 @@ Please see :ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Secti= on` for more info about the PMU traffic coverage. =20 The events and configuration options of this PMU device are described in s= ysfs, -see /sys/bus/event_sources/devices/nvidia_nvlink_c2c1_pmu_. +see /sys/bus/event_source/devices/nvidia_nvlink_c2c1_pmu_. =20 Example usage: =20 @@ -125,13 +125,13 @@ to local memory. For PCIE traffic, this PMU captures = read and relaxed ordered for more info about the PMU traffic coverage. =20 The events and configuration options of this PMU device are described in s= ysfs, -see /sys/bus/event_sources/devices/nvidia_cnvlink_pmu_. +see /sys/bus/event_source/devices/nvidia_cnvlink_pmu_. =20 Each SoC socket can be connected to one or more sockets via CNVLink. The u= ser can use "rem_socket" bitmap parameter to select the remote socket(s) to monito= r. Each bit represents the socket number, e.g. "rem_socket=3D0xE" corresponds= to socket 1 to 3. -/sys/bus/event_sources/devices/nvidia_cnvlink_pmu_/format/rem_s= ocket +/sys/bus/event_source/devices/nvidia_cnvlink_pmu_/format/rem_so= cket shows the valid bits that can be set in the "rem_socket" parameter. =20 The PMU can not distinguish the remote traffic initiator, therefore it doe= s not @@ -165,12 +165,12 @@ local/remote memory. Please see :ref:`NVIDIA_Uncore_P= MU_Traffic_Coverage_Section for more info about the PMU traffic coverage. =20 The events and configuration options of this PMU device are described in s= ysfs, -see /sys/bus/event_sources/devices/nvidia_pcie_pmu_. +see /sys/bus/event_source/devices/nvidia_pcie_pmu_. =20 Each SoC socket can support multiple root ports. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2024 14:21:55.8947 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4d90047c-8589-4397-e0ff-08dcf9b75fbf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DB.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7193 Content-Type: text/plain; charset="utf-8" Enable NVLINK-C2C port filtering to distinguish traffic from different GPUs connected to NVLINK-C2C. Signed-off-by: Besar Wicaksono --- Documentation/admin-guide/perf/nvidia-pmu.rst | 30 +++++++++++++++++++ drivers/perf/arm_cspmu/nvidia_cspmu.c | 5 ++-- 2 files changed, 33 insertions(+), 2 deletions(-) diff --git a/Documentation/admin-guide/perf/nvidia-pmu.rst b/Documentation/= admin-guide/perf/nvidia-pmu.rst index 6e8ee0fcf471..4cfc806070d7 100644 --- a/Documentation/admin-guide/perf/nvidia-pmu.rst +++ b/Documentation/admin-guide/perf/nvidia-pmu.rst @@ -86,6 +86,21 @@ Example usage: =20 perf stat -a -e nvidia_nvlink_c2c0_pmu_3/event=3D0x0/ =20 +The NVLink-C2C has two ports that can be connected to one GPU (occupying b= oth +ports) or to two GPUs (one GPU per port). The user can use "port" bitmap +parameter to select the port(s) to monitor. Each bit represents the port n= umber, +e.g. "port=3D0x1" corresponds to port 0 and "port=3D0x3" is for port 0 and= 1. + +Example for port filtering: + +* Count event id 0x0 from the GPU connected with socket 0 on port 0:: + + perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=3D0x0,port=3D0x1/ + +* Count event id 0x0 from the GPUs connected with socket 0 on port 0 and p= ort 1:: + + perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=3D0x0,port=3D0x3/ + NVLink-C2C1 PMU ------------------- =20 @@ -116,6 +131,21 @@ Example usage: =20 perf stat -a -e nvidia_nvlink_c2c1_pmu_3/event=3D0x0/ =20 +The NVLink-C2C has two ports that can be connected to one GPU (occupying b= oth +ports) or to two GPUs (one GPU per port). The user can use "port" bitmap +parameter to select the port(s) to monitor. Each bit represents the port n= umber, +e.g. "port=3D0x1" corresponds to port 0 and "port=3D0x3" is for port 0 and= 1. + +Example for port filtering: + +* Count event id 0x0 from the GPU connected with socket 0 on port 0:: + + perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=3D0x0,port=3D0x1/ + +* Count event id 0x0 from the GPUs connected with socket 0 on port 0 and p= ort 1:: + + perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=3D0x0,port=3D0x3/ + CNVLink PMU --------------- =20 diff --git a/drivers/perf/arm_cspmu/nvidia_cspmu.c b/drivers/perf/arm_cspmu= /nvidia_cspmu.c index ea2d44adfa7c..7ab7d76e4ca1 100644 --- a/drivers/perf/arm_cspmu/nvidia_cspmu.c +++ b/drivers/perf/arm_cspmu/nvidia_cspmu.c @@ -130,6 +130,7 @@ static struct attribute *pcie_pmu_format_attrs[] =3D { =20 static struct attribute *nvlink_c2c_pmu_format_attrs[] =3D { ARM_CSPMU_FORMAT_EVENT_ATTR, + ARM_CSPMU_FORMAT_ATTR(port, "config1:0-1"), NULL, }; =20 @@ -210,7 +211,7 @@ static const struct nv_cspmu_match nv_cspmu_match[] =3D= { { .prodid =3D 0x104, .prodid_mask =3D NV_PRODID_MASK, - .filter_mask =3D 0x0, + .filter_mask =3D NV_NVL_C2C_FILTER_ID_MASK, .filter_default_val =3D NV_NVL_C2C_FILTER_ID_MASK, .name_pattern =3D "nvidia_nvlink_c2c1_pmu_%u", .name_fmt =3D NAME_FMT_SOCKET, @@ -220,7 +221,7 @@ static const struct nv_cspmu_match nv_cspmu_match[] =3D= { { .prodid =3D 0x105, .prodid_mask =3D NV_PRODID_MASK, - .filter_mask =3D 0x0, + .filter_mask =3D NV_NVL_C2C_FILTER_ID_MASK, .filter_default_val =3D NV_NVL_C2C_FILTER_ID_MASK, .name_pattern =3D "nvidia_nvlink_c2c0_pmu_%u", .name_fmt =3D NAME_FMT_SOCKET, --=20 2.34.1 From nobody Sun Nov 24 23:56:40 2024 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2077.outbound.protection.outlook.com [40.107.223.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BBC81A257A; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2024 14:22:03.0744 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e3b2bda1-b999-4e37-cbbe-08dcf9b76409 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5978 Content-Type: text/plain; charset="utf-8" Some NVIDIA PMUs like the NVLINK-C2C, CNVLINK, and PCIE PMU provide port filtering. If the port filter is set to zero, the counter of these PMUs will not capture any event. To avoid meaningless experiment, the driver sets the port filter value to a default non-zero value. Signed-off-by: Besar Wicaksono --- Documentation/admin-guide/perf/nvidia-pmu.rst | 12 ++++++++---- drivers/perf/arm_cspmu/nvidia_cspmu.c | 6 ++++-- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/Documentation/admin-guide/perf/nvidia-pmu.rst b/Documentation/= admin-guide/perf/nvidia-pmu.rst index 4cfc806070d7..f538ef67e0e8 100644 --- a/Documentation/admin-guide/perf/nvidia-pmu.rst +++ b/Documentation/admin-guide/perf/nvidia-pmu.rst @@ -89,7 +89,8 @@ Example usage: The NVLink-C2C has two ports that can be connected to one GPU (occupying b= oth ports) or to two GPUs (one GPU per port). The user can use "port" bitmap parameter to select the port(s) to monitor. Each bit represents the port n= umber, -e.g. "port=3D0x1" corresponds to port 0 and "port=3D0x3" is for port 0 and= 1. +e.g. "port=3D0x1" corresponds to port 0 and "port=3D0x3" is for port 0 and= 1. The +PMU will monitor both ports by default if not specified. =20 Example for port filtering: =20 @@ -134,7 +135,8 @@ Example usage: The NVLink-C2C has two ports that can be connected to one GPU (occupying b= oth ports) or to two GPUs (one GPU per port). The user can use "port" bitmap parameter to select the port(s) to monitor. Each bit represents the port n= umber, -e.g. "port=3D0x1" corresponds to port 0 and "port=3D0x3" is for port 0 and= 1. +e.g. "port=3D0x1" corresponds to port 0 and "port=3D0x3" is for port 0 and= 1. The +PMU will monitor both ports by default if not specified. =20 Example for port filtering: =20 @@ -160,7 +162,8 @@ see /sys/bus/event_source/devices/nvidia_cnvlink_pmu_. Each SoC socket can be connected to one or more sockets via CNVLink. The u= ser can use "rem_socket" bitmap parameter to select the remote socket(s) to monito= r. Each bit represents the socket number, e.g. "rem_socket=3D0xE" corresponds= to -socket 1 to 3. +socket 1 to 3. The PMU will monitor all remote sockets by default if not +specified. /sys/bus/event_source/devices/nvidia_cnvlink_pmu_/format/rem_so= cket shows the valid bits that can be set in the "rem_socket" parameter. =20 @@ -199,7 +202,8 @@ see /sys/bus/event_source/devices/nvidia_pcie_pmu_. =20 Each SoC socket can support multiple root ports. The user can use "root_port" bitmap parameter to select the port(s) to monitor, i.e. -"root_port=3D0xF" corresponds to root port 0 to 3. +"root_port=3D0xF" corresponds to root port 0 to 3. The PMU will monitor al= l root +ports by default if not specified. /sys/bus/event_source/devices/nvidia_pcie_pmu_/format/root_port shows the valid bits that can be set in the "root_port" parameter. =20 diff --git a/drivers/perf/arm_cspmu/nvidia_cspmu.c b/drivers/perf/arm_cspmu= /nvidia_cspmu.c index 7ab7d76e4ca1..b926861b133a 100644 --- a/drivers/perf/arm_cspmu/nvidia_cspmu.c +++ b/drivers/perf/arm_cspmu/nvidia_cspmu.c @@ -175,10 +175,12 @@ static u32 nv_cspmu_event_filter(const struct perf_ev= ent *event) const struct nv_cspmu_ctx *ctx =3D to_nv_cspmu_ctx(to_arm_cspmu(event->pmu)); =20 - if (ctx->filter_mask =3D=3D 0) + const u32 filter_val =3D event->attr.config1 & ctx->filter_mask; + + if (filter_val =3D=3D 0) return ctx->filter_default_val; =20 - return event->attr.config1 & ctx->filter_mask; + return filter_val; } =20 enum nv_cspmu_name_fmt { --=20 2.34.1