From nobody Mon Dec 2 14:50:23 2024 Received: from EUR02-DB5-obe.outbound.protection.outlook.com (mail-db5eur02on2049.outbound.protection.outlook.com [40.107.249.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33C8A15666C; Thu, 31 Oct 2024 08:36:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.249.49 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730363772; cv=fail; b=qsCXmUeSUOpk79M40rGpxFUdjrJXDXJVKZIx08ad79WwfeAU/z2oSJDKCpbsn32/pUFDFYmJ2d2+8EVZA6QtEXi2jM2y7WHweRpwA6gksC9u9Hbs9SOJXb81UXa9Vm3sCkJFu5zRMDJDEDiEnQ5ym8bI3ZQhfBK7jMFnrstzC3w= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730363772; c=relaxed/simple; bh=TOscC/un62mUyE6aArmIFEMBvnc25EpHpOS/tmC8p2o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=p9me+MJtEe58c93sVei3yKDGrnldQ32VM6W2pSQvEusaKQi+qSxL5GZ+Cm2/tHD2v6xqLmgXz72WvyHXvGfJOAlSkVTHL+Bc1eBD+mlXSlPLSiWTLe2sxqKQU3phaIxT6mUPXh7fL093MIIhAGRsA4PwCd8s6MCAnyDZIpO00Ws= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com; spf=pass smtp.mailfrom=oss.nxp.com; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b=voREhIsD; arc=fail smtp.client-ip=40.107.249.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b="voREhIsD" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=CWzVBmadH4XFgLtS+DBLD+LWgkUgJZmBJhx0IPMqhUeCYx688Hk8taHthfJVjb36+VVGhjHlAKciLhfAVcTQbV8BAgPXHuNZtW8Ef7+JJJKNQFoyYUqkc/lYwObCEc0orUmWnKZPnmaZB4MhpZolsUrK79/8RdkXLyZt8p0Qb9WckccZADBjyxC6WeYddh7Gcb+KQP4kJ4cDVNhFRKgVswd0TyFy3RmsIps8Syg/v8AXtMGMndDLdUlkuD6XRrFA8XBI4zLHn7zPGC76IMJf8bNouu5galP/OjOA4TTrPVAJW/PbGu7tMNmzuolzqzRk+woff/aNqbVmsNqnGzLODQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=jodImk9bZdd1uS46rPT0HskxuCQQy37qKL5c8r4OT/c=; b=VgYdyVWlAG235DnQov50Hyxg8zexcQ+YtY22c2hmLKFOsaP/+qlEkLwQj/j1/e5DSgSssU2DAtWvY6z/T4oWU0rXrBmyaDT+vbJORzSmFkKOpB/gC/YIg3RzVVq9q9QycxsX0cOCez2kUFp8+ePoN/DxIS25zuYks7DiDCiKM2hEK8tVvuRanJTT0NUpRJAx6DZieqtBZk5frFqeynyxIEvs3edWqt/ObLzZ+SypxxEqX1l/PSsUUt2iWcoL0bftJjN8sCWCAkNa0O9cDuD/WdrkcbJUiHDRi2Z9P7RcJsOk8Cf+wB2uhJRr3cyoOPHFFr1eorRs1NqodLAS4sj3hQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector1-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jodImk9bZdd1uS46rPT0HskxuCQQy37qKL5c8r4OT/c=; b=voREhIsDIDGPU8oiRUbssg0IPQCrJUbeqHYTHFm1OCArH7tpiwV8+nOit0xa98lq/ZT27nbdkgRquY7UwEkSwQBkyVDYpyFpHrH5hZMBw1ViapcqeSHaWX/5CKAmG2EWmM6v8iPdgt6e4E3YlHQZ+ob+mVEEMUb2wkWaNpCuC98oVmKGrZllpTkNBf7HOdUBVfjLSZK/9UsxZIjyL6B6R9v52Ywf9UZ6o/KmqWWU0CxShmHfEteEgBiheu2ny+Q79uhxQQUs70hw6oa7/dR5uJpIKga5EtvyYxikgFGi7C1lyLnAEqsJ9EGq1OxekME0HHoW+qel12riFBeSyofOQg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from DU0PR04MB9251.eurprd04.prod.outlook.com (2603:10a6:10:352::15) by VI1PR04MB7199.eurprd04.prod.outlook.com (2603:10a6:800:11d::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.32; Thu, 31 Oct 2024 08:36:03 +0000 Received: from DU0PR04MB9251.eurprd04.prod.outlook.com ([fe80::708f:69ee:15df:6ebd]) by DU0PR04MB9251.eurprd04.prod.outlook.com ([fe80::708f:69ee:15df:6ebd%6]) with mapi id 15.20.8093.025; Thu, 31 Oct 2024 08:36:03 +0000 From: Ciprian Costea To: Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP S32 Linux Team , Christophe Lizzi , Alberto Ruiz , Enric Balletbo , Ciprian Marian Costea , Bogdan-Gabriel Roman , Ghennadi Procopciuc Subject: [PATCH v3 1/4] dt-bindings: rtc: add schema for NXP S32G2/S32G3 SoCs Date: Thu, 31 Oct 2024 10:35:54 +0200 Message-ID: <20241031083557.2156751-2-ciprianmarian.costea@oss.nxp.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241031083557.2156751-1-ciprianmarian.costea@oss.nxp.com> References: <20241031083557.2156751-1-ciprianmarian.costea@oss.nxp.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: AM0PR04CA0109.eurprd04.prod.outlook.com (2603:10a6:208:55::14) To DU0PR04MB9251.eurprd04.prod.outlook.com (2603:10a6:10:352::15) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9251:EE_|VI1PR04MB7199:EE_ X-MS-Office365-Filtering-Correlation-Id: dd22899a-bb82-4732-c950-08dcf9870de1 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|366016|1800799024; X-Microsoft-Antispam-Message-Info: =?utf-8?B?c0ltZnN2dDZQVmRLNDU0dVFvUXFmbFBSL3lqU0I2LzluN2wxMHhLVk1DZXIv?= =?utf-8?B?WVFZcjhCNm9uZWlOWklxRkJvZ2YwZjhYTlpZM3ZmaDUwT05oajROVkZtQTFm?= =?utf-8?B?MHJDQ2xkSTM1N0pBQmpSendFeDZsVnlBcnVyQUdqSGdyNkwyV2VxNkFvWDJn?= =?utf-8?B?SWZJWDlWclNvcHpLd0gzSCtiZzFYMUhXNWZNTWdYeHBaQ1hCM1BhWmVSZ0Zx?= =?utf-8?B?bTVZNmpIODArOU1ZSWQyMGRQSEkwdmlhQUhiM3JmL2xXYnJFa3pUTFBxV09C?= =?utf-8?B?R3dkUEY2Q0xRRXpMVnhtMG8xQitqOU5YZytCNTdmUUVJUG5NNW40V0IwaXEx?= =?utf-8?B?K3p2aW1HRHpCNnIyN3RKV3FTOHRWNnNxanVLeUxKYXRmNWp1VldNQzVOZkVq?= =?utf-8?B?dklpa0lCSVhpM2Y0anNJb29iNkxodHEyT01hNERzMnJSRC9xNmUvZjFxVm5H?= =?utf-8?B?UmhJcmlKR2NqUkpsYW9vb09XRmtTVmo2N3czR1lEb3NJbkUvK243blM3cGJn?= =?utf-8?B?b0ZkSDhIMUxtcXd1RkVLZmFQYXc3RHY0Uk90RWwwUXNBTmNOOW9FUmdoc3Mr?= =?utf-8?B?MjZkR3d0MnZmbE8wSmlHWFZLVmUzVGs4NzFzd1NGSkdxVm5tbmQ4NGp5K2Qz?= =?utf-8?B?WlFuRTRtT1ZjcmRCdEpwRlRQMGx2VHNkeEVlbDlnVjVqMUFzTVhkcWlBK2pK?= =?utf-8?B?YTNpeEw4MkFlZks4LzVYcHZ5a29oM1I2WUMydy9EbExUZEhSbHZpbk9kb1ZJ?= =?utf-8?B?eFB5REtGOVdoWnk0bjg5R01nZFNJcU1pcitpOFQxbkRXTE4wOGt2R2FhSk1h?= =?utf-8?B?bloyUTRPUSs0aDNTV1YzVXVFOUxvU3hqenY0ampPVVM0NExmdS82dC9aclJC?= =?utf-8?B?NkJHYlZ6YWswdEZISGgrM1BjOHpnWlE5YkVoakR3djA5OXc4VXRYalRFS21t?= =?utf-8?B?UzFKd2pjQlVsbU5PcW5xNG1yV3llS2VQMkF5eVdCVWFUU2dIZXIyZDZMU05j?= =?utf-8?B?U04yNGxyYmNERGFPdE9idW1qcVBKTWMwV2N1K28yN2h0NHd2ZXpqVjZlNFNh?= =?utf-8?B?emJOQzI5cjVnZ0EweVdoM3hIT1AvVUxpUUVVK2x4Q3d4dEVhRXJheUJHcVV5?= =?utf-8?B?dEwwNUVXcXlBUGtIVER2S1VUVGMwTDlNa0JiUVA2bmFtM01KRjJWWUtZbVdE?= =?utf-8?B?eGM2OUhhWVF5Z3QxRXA4NGU4QTQ4dmwrbnZlMUhkejgxcUVkdzZ3UkRBeE9B?= =?utf-8?B?MHkwdG4zd3JDVGJ6OWR6ZGtUN1lIZUNqZHN1MmdNRTQ0bFRyWXRFckpPaEYv?= =?utf-8?B?anpVZzZSTzdRcDFBQjFGcmVyb3VSd2M1ZWQ2UUFDZXB1ZlRvdlpDZHU0alJo?= =?utf-8?B?bjFCRzJLUmluemNwZE9CMDd3UThrbmpKVUZzdGtvRDJvVDU4Z3JlalNKSmFp?= =?utf-8?B?U2RQWXpvdlJJdkhpc1hhc2hKQ1VWRk9SNG1ZTll4cU1wK1dwVmpJNFFXT3hY?= =?utf-8?B?VzZXaHB6djJVSzJDKzVrV25URHVKYzNnRjdjYTA0aUN3bmoxbTQwNklTcVRI?= =?utf-8?B?anFvT2kzNzVidGpQcG12MHArQU94ZXVTeEpHaFZUVU1WVUZtUnZHcWdYV1or?= =?utf-8?B?WE9qN2d6ZWJ0QmFiUzJlSGcrdi9WWnB2dFg5ODNLckt6Z1ZYUE1NY0JyU25t?= =?utf-8?B?ajVNRFFXZTRRc04rWWVtUDNQMFNJK2JKQmZtUldWS3RKdmtqTDA2NzJBPT0=?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DU0PR04MB9251.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(7416014)(376014)(366016)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?SW5Rci91Qk1CK1VMenpHK1pBUERUcEFQNkNoMTRDUGtQYjlXaVIrUkJKNmdT?= =?utf-8?B?M0tyV3hJYS94eURwai9OWmZDMUZJT1VmSmZBMjF3ci9jdSsyUDNnVm1obVF4?= =?utf-8?B?bkpSckJLUUYySlhBMDdwN1B6RFVqN0JrcXViYXNCaVZDMFByMU1PTWtWVFB6?= =?utf-8?B?Wno3S0R5YUZVSmtPQTRBaGpUQlI3cm5veEwvUmRTSDcrTzBOeVVpUGJ5bzdT?= =?utf-8?B?bWFkZVRNQVRoaE1zZkJuTnRNc3lBeXh1eUZTNEZyYlRqWm5RR1Y5SHZlWXR6?= =?utf-8?B?TXlCUUEwNWJTekt5RGpEdmxDVWREM0lmRlcwV3VqdmlSWVNQNW52ZmkyY3RL?= =?utf-8?B?S2hYRStSakNuYVNNTElKUTZaQXNHbk4rTHZ0eDllTzYvd3RFRkhFUmxXaERP?= =?utf-8?B?WWthNVpPUmlGNE9vS3R0UCtCMFNaSVNnUzZnTHRKWHVqQUVmNTlKb0ExYU5S?= =?utf-8?B?RVhvM0pGeHZXaTg5YmpqOXdXVzlUYnlJbG1JenRhRzVFWm9sREhVNUZSOEwz?= =?utf-8?B?R1djWWM4S2tSK1NhUCtKRDN6WTNYUFNtZHBUdjRCMDVPV2t1NS9HWWVzN2xU?= =?utf-8?B?OUVhZlcyQitndWpwZGpSL2lIY04yOTlXOHdTOE5KYnJRbDZpTEV6WDhXT0xQ?= =?utf-8?B?UnNRUldOQ1RBWHpQN3BCSWwwYTZ1YnRKR2JwR3ZVbDFQdzVDK2Z4dlBHZFB5?= =?utf-8?B?bDMxVXQwb3RzVTdtTU43U3dMNmpSZzMzbTNJaEQvTEZ3ekhyQk9DSmtFYlhl?= =?utf-8?B?Q0M4V2hpWnRSRDRzMXB4MnpJemJwSU1US3lveFE3bzJLL0Z3STkzYU8wbzJB?= =?utf-8?B?UDF5VU96M1htL1puYnZWZDg3dTN4ellyb1UzS2JvOGJyVUJ5ZWRrUE4yUU16?= =?utf-8?B?WU1GN2dQZkh1Y2k5eFNPa3p2MU5LTDNUVktXbE53M1NDdm5nMWZ0bG9oQ2RD?= =?utf-8?B?ZnlhOGRrSC9NdExmZi8xTmxOeGdWQk1aS2I2UDlaS0kvR1J2SVFXeThpRnZt?= =?utf-8?B?aXJ6VHdzNnlNRzlwdkt1VU9SamFFOTJiQkpqUWMveVZ6RHg2YmVqa0w5emZ5?= =?utf-8?B?emVwWTZTWDhUbmtwNmh0cDRvTVRhcWU5K2t1TWoyRUkvY3l3eU1aRUZma2d5?= =?utf-8?B?WnFPcHRnYzZpamkwR0kzSE5lVWtkWW9IeDQwSUozbWcvY1BWUDEzczZoQksy?= =?utf-8?B?cEFGRFZwOVFtb21DZWNmenB0ZU5oTlk1L2owWUJKS2xHTjRMUWpPWnpraTNH?= =?utf-8?B?cDVCNWxzM3B3V25sZzZjV3hJVTZ0cXFRL042M2dMeEpidHRKUmxoRnRwRUhO?= =?utf-8?B?QW5rZmxScjBGaTlZc0tyOXFxQ056enQ1c0tLV3U4dUlXZWFLVW1Cd2tSYjBz?= =?utf-8?B?VW1Uc3hwT1M4RlBlRXZ0cU9DUHdVUDhRV3BmL3hYTlh3N3NSNjFwK1hPdGNt?= =?utf-8?B?OWwvcFBHV2NiR2RncFBXdlEydDFlY1ZmMDczSk9pSnZYNnpUNWlFcE8xS0NY?= =?utf-8?B?SGwwS256VXpiRG5Eb0ZXSmZpc1RReHZpZjA5d1BqZWdTZmM2ZEk2bm5vRk8z?= =?utf-8?B?dERwd1FIWWdwa2xYdURMdkVZVDV1VDB1Y25oY2thRGNpVkFpZEJRdlh6WDQw?= =?utf-8?B?eVlaOXdTYmVKZHNjTmRrMVF0K1JuOEtESlJWc0ttSEk3OXl4WE5BMWdPZzBy?= =?utf-8?B?c3l3TFZmakRoWGVrb0I2WkZHVkRPNlBWQjc5RlFBTmlFTERBdlk0cnRpYzZS?= =?utf-8?B?SlIwUURIZjQ3NC9LTVI3UlF4STlSYlZwWkMwR3o1b2FzTmxYREJRdkd0N3c2?= =?utf-8?B?b3pLQldWVXR2SDZSSzNxV2lZQ0Rqb3JTeUF3QjVRK1pxQnM3c1VnTFNsbU5C?= =?utf-8?B?NHY5cFliVnVMOFY5dUZ5ZmxEeXhyNW5jdy9meUlJaXpOU3ZmYnNseGt2d0RR?= =?utf-8?B?NDRQaXMvSGpBNDYvQmdSTGVCOWNManIyTWREVTg0NDRXUU5JTkhvNVFZY1o3?= =?utf-8?B?TXIvOXFOMkUvblFRUU1rNGdDc085QkJFQ1V6MkhxTDNvaXozMGhFdWdFL1Ny?= =?utf-8?B?TkVHTktReFgvM3FLU2FXTS9hR1EzK1d5Y3c2cVFMMisxY3d0N3RSQ253OTdL?= =?utf-8?B?ejJnSHZJOEdWcll4c0tuMW5uTXUwQjdPaGFwNGUyOGZZaHR2NWUyalduQy83?= =?utf-8?B?NGc9PQ==?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: dd22899a-bb82-4732-c950-08dcf9870de1 X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9251.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2024 08:36:03.0258 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Dwfkyz0AwA6fFCCKkwjGE/h3v/PGefPIS0Fz1vSvaR8PpoC5FkkLqj3BuV0272BNnTGES4yXfX9Xi7QzHBGfcaeemMLnKMVOuYlJirtxLTo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB7199 Content-Type: text/plain; charset="utf-8" From: Ciprian Marian Costea This patch adds the dt-bindings for NXP S32G2/S32G3 SoCs RTC driver. Co-developed-by: Bogdan-Gabriel Roman Signed-off-by: Bogdan-Gabriel Roman Co-developed-by: Ghennadi Procopciuc Signed-off-by: Ghennadi Procopciuc Signed-off-by: Ciprian Marian Costea --- .../devicetree/bindings/rtc/nxp,s32g-rtc.yaml | 99 +++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/nxp,s32g-rtc.yaml diff --git a/Documentation/devicetree/bindings/rtc/nxp,s32g-rtc.yaml b/Docu= mentation/devicetree/bindings/rtc/nxp,s32g-rtc.yaml new file mode 100644 index 000000000000..3694af883dc7 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/nxp,s32g-rtc.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/nxp,s32g-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP S32G2/S32G3 Real Time Clock (RTC) + +maintainers: + - Bogdan Hamciuc + - Ciprian Marian Costea + +properties: + compatible: + oneOf: + - enum: + - nxp,s32g2-rtc + - items: + - const: nxp,s32g3-rtc + - const: nxp,s32g2-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + items: + - description: ipg clock drives the access to the + RTC iomapped registers + + clock-names: + items: + - const: ipg + + assigned-clocks: + minItems: 1 + items: + - description: Runtime clock source. It must be a clock + source for the RTC module. It will be disabled by hardware + during Standby/Suspend. + - description: Standby/Suspend clock source. It is optional + and can be used in case the RTC will continue ticking during + platform/system suspend. RTC hardware module contains a + hardware mux for clock source selection. + + assigned-clock-parents: + description: List of phandles to each parent clock. + + assigned-clock-rates: + description: List of frequencies for RTC clock sources. + RTC module contains 2 hardware divisors which can be + enabled or not. Hence, available frequencies are the following + parent_freq, parent_freq / 512, parent_freq / 32 or + parent_freq / (512 * 32) + +required: + - compatible + - reg + - interrupts + - "#clock-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + rtc0: rtc@40060000 { + compatible =3D "nxp,s32g3-rtc", + "nxp,s32g2-rtc"; + reg =3D <0x40060000 0x1000>; + interrupts =3D ; + #clock-cells =3D <1>; + clocks =3D <&clks 54>; + clock-names =3D "ipg"; + /* + * Configuration of default parent clocks. + * 'assigned-clocks' 0-3 IDs are Runtime clock sources + * 4-7 IDs are Suspend/Standby clock sources. + */ + assigned-clocks =3D <&rtc0 2>, <&rtc0 4>; + assigned-clock-parents =3D <&clks 56>, <&clks 55>; + /* + * Clock frequency can be divided by value + * 512 or 32 (or both) via hardware divisors. + * Below configuration: + * Runtime clock source: FIRC (51 MHz) / 512 (DIV512) + * Suspend/Standby clock source: SIRC (32 KHz) + */ + assigned-clock-rates =3D <99609>, <32000>; + }; --=20 2.45.2 From nobody Mon Dec 2 14:50:23 2024 Received: from EUR02-DB5-obe.outbound.protection.outlook.com (mail-db5eur02on2049.outbound.protection.outlook.com [40.107.249.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E7E018453F; Thu, 31 Oct 2024 08:36:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.249.49 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730363776; cv=fail; b=WhcNF7+NFsOH3n10cBoBazIkOXQczt9ypB/NHv6TgkSFLRRMvinpR2rlDE75YTI//DKLt4NnRWkY8wfTbj4OcJgQN7wuldwnkYEsPm0G7m4BLNr2hc0O30bdNZrJGC3c9pHrxGU41ouXMZa3D8nTsb+jHTF4tgCFFn/YeLUtfgQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730363776; c=relaxed/simple; bh=rzuzLqgF1Wld1gG1tagIfccVz/W6+y7nWKkf7YrSu9Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=g8aneYotHlUdfJbr9hbMHJD/NuGMh4lGhMaPTIbMJoDNMmBcnXkhODKRvSuTeZVeAIM+SwvPXF2ZgWQGKo2mMKr+9rgIK5OlXm1lPiYeIHQtIMxEpVPQslGLN0duLYYjMyLVgY/nM7NUpaKO8YWu5ukyBZYSsxe4nhv4yCYGTsQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com; spf=pass smtp.mailfrom=oss.nxp.com; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b=EhgaPzAu; arc=fail smtp.client-ip=40.107.249.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b="EhgaPzAu" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=spCCmr1/cSpv+R/dGoFVy43lpzWg0KNmgVOLo2Fg3K7hvptUvq6JU8Pit+fNqFeWP/vD9/jDfx7rVIg9SqvTnOfPVhcOBIPk1u8fJES434GGPwyOYrf3s4Iw+U50LYRWcnB9vIyaSlR2hywF3c5Ylhyk3NkQC/0CMgbvSUsOg3a75CNWfC5WdwOwypwMvllqGP3ol4xe5BttqwnYoP/1ZrVEOkJcI9/tOXTDQxScqYHiwGTqyO6Z/QxiNHtwLldTdcATwei35t5Xdr48I4V1q2xYzntJfqqTkzVI2lQpZ5Kaf5GKFUgDfEnJctLGbU9Fq/c2dtsLB5VriCM2KxF2bA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=wWaawxt77xC7mKWZ021v9pDtAqdlR6gtuXp4zwKk9E4=; b=TugtEVmpdViwi3L8okpTvOtrRz90Xo5/iLyL7ZPeIYf27Gpz+8mgbpJOt52SRA7pikLj8yC2iPjYhrT+uUgmRztHNhjpxnV5nLurqFrrIujt8tVCdyMBltlFtBMsYq2d6vV2pbQLuOg8kz1dAByr04eMrWdGbxOB24icAF40Jm2AWArkItnXD0CIJyIl7+ADxIOZyyKGobERQIhUNGXpQqX0cySaGNuDJ+VUNyUYgA+T0do5YgVRq2DpkIy/Ze2eX4FX4LPcnkccD9Ba4bh2f1UYBnYQFNu6HDlK9DiPZYwjfx8mt8SWozgZgRyucAZnfZE6Mma4t6RDK9mJlZt5tw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector1-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=wWaawxt77xC7mKWZ021v9pDtAqdlR6gtuXp4zwKk9E4=; b=EhgaPzAuOG8H1iiEzvDzFIE5ZswIbufkWBCCkdBAcVdOLKtARJZeMYy5HRXxPHmNvPhhtaIVntSv+Kh/tmxzyeEpMWj8Q48eAl+5/i+YXeqB6G2bpevWgJ1b9t+zirmIsT2YqJpmffN4sV91zWuz58L+PLPxE/ZIEA79dT2Xd3x/wPVEIhlon6lQwOXjmKJ35wePb6hjzhVaZygYNqzFRtN6Z1ucR0kTzh5O+3fkiwTRuREz8MCWJNh/yffKqM7cpEBdzFDIRBwcIEpPH2X/e0ubFwaTdbl6HLNNw9cFuGnzpUL6yMfK0kbWXy/FGgf6/zhE8UrHNOYWXugM8eqjag== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from DU0PR04MB9251.eurprd04.prod.outlook.com (2603:10a6:10:352::15) by VI1PR04MB7199.eurprd04.prod.outlook.com (2603:10a6:800:11d::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.32; Thu, 31 Oct 2024 08:36:04 +0000 Received: from DU0PR04MB9251.eurprd04.prod.outlook.com ([fe80::708f:69ee:15df:6ebd]) by DU0PR04MB9251.eurprd04.prod.outlook.com ([fe80::708f:69ee:15df:6ebd%6]) with mapi id 15.20.8093.025; Thu, 31 Oct 2024 08:36:04 +0000 From: Ciprian Costea To: Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP S32 Linux Team , Christophe Lizzi , Alberto Ruiz , Enric Balletbo , Ciprian Marian Costea , Bogdan Hamciuc , Ghennadi Procopciuc Subject: [PATCH v3 2/4] rtc: s32g: add NXP S32G2/S32G3 SoC support Date: Thu, 31 Oct 2024 10:35:55 +0200 Message-ID: <20241031083557.2156751-3-ciprianmarian.costea@oss.nxp.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241031083557.2156751-1-ciprianmarian.costea@oss.nxp.com> References: <20241031083557.2156751-1-ciprianmarian.costea@oss.nxp.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: AM0PR04CA0143.eurprd04.prod.outlook.com (2603:10a6:208:55::48) To DU0PR04MB9251.eurprd04.prod.outlook.com (2603:10a6:10:352::15) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9251:EE_|VI1PR04MB7199:EE_ X-MS-Office365-Filtering-Correlation-Id: 7dd8dd6c-1c09-4344-c419-08dcf9870eed X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|366016|1800799024; X-Microsoft-Antispam-Message-Info: =?utf-8?B?M05pZW1uM3UxVFFrUS9vam1MS2xKRS9tRTJFRUhSczczUUhQZlNqVHp3Vkln?= =?utf-8?B?NS9YVWRjTGxrU1ljN3IzVHhIKzVRWSs2NzNmMEMyYlpXLzAxaThxUWsyZXVl?= =?utf-8?B?TVU1RlpvemkwU05lcnRmcDdVUUVkOU15VzRlY3UrcUJwSkxSRlBBMzBXL3lD?= =?utf-8?B?cmJESXp4RUs2WkN0QXVyV3VCU1ZWVWdNYlNtUERjK05RTUZFMVBlOVc0bkly?= =?utf-8?B?b0FybUZuM2UwcU5tblNvL1hqOEJIYXZ1am9BaERJSlRMNXNITmhtaUpuckFT?= =?utf-8?B?Z0NWZXRRZTQ1T3c0a1lKRlZtcDZWUXlhKzhPbHBRZUdHWmkzVWhZK1ZseUxa?= =?utf-8?B?NjdWVGQvcjFHeHcwSXlxUGpiRTRIWC9KNFRtU2F1Um51SytSejB1MUVnMUJL?= =?utf-8?B?VVdLdXRYTVV4Sld0ek1mb1Z0S0h4bEtza04ycUlhbytVY2ZtQm9wLzJTTnp4?= =?utf-8?B?RmdDTTRyWmFwTWM5bnJQRCt1eWVrUjRZRlU3RGVhUHJnWnorTTVPTHMrT2M2?= =?utf-8?B?NTlJQ0VQYXdnZTRQS2MrNkcyeXhQNnRZSTdVZC9SekxQYU9WRTYweHlZTkF3?= =?utf-8?B?ZmhsMGRjRzFzTFVTNm5rMlhEdXZFaVl2N1Q3VUZDY3JvWkw3OGREaHhBNjQw?= =?utf-8?B?aEluWVJMODFMYnM0aGVmMDFxcG9Td0hmUlg5NGErQWp6MC9nbzMwaEhpb3ho?= =?utf-8?B?RVpFcUpuempvYThDemhZWUNEUXVSanBIR2NSMmZNTVZzQzg3RXl1ZmxYYUxh?= =?utf-8?B?SUwvRWpRQmJiQjEzNU5xb2JQN3JEdzgyQzBFWnFneEpqMmJUdlVwbWxZcEU0?= =?utf-8?B?eUEyNEVvVjFERHNSTUhYdHNRdWtLNkJ0OG5nTjNBT0xUR0lUTEltTEdEUHlo?= =?utf-8?B?QWZ5Wk9FU0gxakU4ZW16NGdzM1lPN3hPcnVpS2lvV0tjWTJZK3A2UmVDOC9r?= =?utf-8?B?VjBHQU5tWmUrWTIvL3REZDlIRjFyWDY0ZFA5S0N1MWZjSkZDYk5wa08yMUZI?= =?utf-8?B?WVcwWGdtNmFtTzQ5TThRNFl1VWtBMHFGQm82eU81MUFRbHNYVWVJY1RVTW1j?= =?utf-8?B?TWlTc3Z6bHdGSUpySy95L2pDaHdDTVczWHZwemdXKzJQSDNsQTRwaEZLZ0xR?= =?utf-8?B?aGdNWVJsTzl5czJzSkp3UDQva3g3OWlPNHZMbmlSVU9DMS9VWnlYdU85YWsx?= =?utf-8?B?SDM2L0JMN1IvUzNSSmFRL3NyWkJMWFcrWXlvcVRZU1pFa1hUN3I1VFg1aHJV?= =?utf-8?B?TkRCTDNhQk1sbVk3azV4M2N4TUk3UUUrRzR4RTdwSUlwTVg5TWNKN1F5YlRo?= =?utf-8?B?TzJFUURDT01QYVpNaXJ5RlhrejA1VWdMczdSWnZ0c0htdURiY0lpS1N3R2FS?= =?utf-8?B?WVlZUGV3WkpndFZoVTVMWEVjNEZCSWQyVjFTRnVlWGNWd3NTY24wMmdXODVZ?= =?utf-8?B?a01nR3BJWFQzcDl5YStJVlFVa1pPTjJ1NjZOcUJEY1RyL01Ja1VxVXlKaGRi?= =?utf-8?B?OUR0RGl2aWlHOTBCZEVnekhoUmxYeDRVdU5KWCtaRE84UzFmVkVUTlR0V05u?= =?utf-8?B?WUlKZUFubUxnMnQwR01CNzhMSUVtMkY1RlRhaWZ6UDVPdzMvM0p1R3JxWVpU?= =?utf-8?B?TlVkZ0lOdFR1cURjekR0U3BneXR6YUlTUVY2SVhXWjhwclRNM3RBREZubzEy?= =?utf-8?B?VnIxdTVha1BMazQ5OGpMSzlXL3owY243d3J2bWN4L2VHMzZQck1GN0puRkpN?= =?utf-8?Q?pEP3sKhjMTyCk4JVGY=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DU0PR04MB9251.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(7416014)(376014)(366016)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?VmFvOTRDanlUVlhGQmlvWWQ4dlNibTBlM3pJbXJFK295RGxpbDFsWERzVXdG?= =?utf-8?B?THJjaFpYRWtCZXVsZDArVUVmalRiTHR3QTZSWDVLUFp5djBVYTZsMVkrNnFN?= =?utf-8?B?S3paMUUrR05rNEV1SEN2ZmpWbEZpRlJIY0Mrcys0T3lwdnBVL21CdFpXckZu?= =?utf-8?B?NFRLbnFFc1lpWkFSakhKN2J0cmRPZklrTS91N3dpOGNrMHN1NXN1TnhxODN6?= =?utf-8?B?ZkJlblYxTHV2TU1LQXBxdTJhcUdaSWYyLzAxRmhmVVpWRzAzdEpDZ29QbHN3?= =?utf-8?B?MDJpNE8rS3NEalMrOFZYVEY1MzBNNTNXNXpjQWN0bkNHdVh1N0pVekQ2Y1Rl?= =?utf-8?B?OFRuNTloMVFDNDRVdU80QlBscHluaU8vclhNQW5lc095YnlEaEJkblZrZU9M?= =?utf-8?B?MkxmZGUwWk5qdERaOFY2UTl0bzVzZXA4M1V1RTROT1RmYlBpbUtvK2tQVXZF?= =?utf-8?B?R0tIVThIcVBCVmY0UG1aenVKdkZiS0JZdHZXeTVxTEtQR282SXlmQk8wWWxr?= =?utf-8?B?eFdEN1lhNlEwcVg1cTJ4dU15bzBIUTBuK0dseWRjSHBhMW40VHR5UWRkaW5m?= =?utf-8?B?a1I0aFZoMXp4NUZWM3hnVmF6b042M2FYdUxHVkwvM3FuYUdHYnF2eURFelpl?= =?utf-8?B?WjdLdlIxL1YxdnhGZDV3c0YwbTNhTGd1UWIxNkczQUZhYUNnYTFqOHBTZVpu?= =?utf-8?B?QVg1WEFHQTFJNzlhK3FtTWNMYysvSzJyVHNmWTdzMVZsZ1hCMGRTSVhOeW42?= =?utf-8?B?cDhkVGFUK05jY3lQbmNpUCszNkVIKzhEV2g1dnRrdzc1WWtPVkx2eEsydGpp?= =?utf-8?B?M1BsYnJ6UUZZZ0JzMkxZQndqS01ZRC8vN3VRamMrNFdxbWNqdkdQaGxwSEw2?= =?utf-8?B?U1JkNlZ6MGJ6VCtXbCtYNHo3d2MxOWpBdUY2VGNLektFZnZuc0I4VmVBY0Jq?= =?utf-8?B?TUU4UVpHbWhIWVIxejY1SDhJdUIwcTVaVTQ4YXdPRGViQzc2Y3MvTW1QZWNF?= =?utf-8?B?ZXdaVXZ1S1dzOUNXQkY5d2drdHNFWTFkYUd6bG9GZU11Sy9jSEFLTVNPMjZH?= =?utf-8?B?N1A0YkFhSTFhNVdZZlBuR3pJdjRMd1Erc0FiWXBsVnduVUEvSGdlaDBDOUJQ?= =?utf-8?B?UEpxaHo4UVZ6OHIxVGlIUFYzYmRWb3JqVWpBTTM1SklZYWJwdmRyWnZVOXky?= =?utf-8?B?dkg3N0JIL29tY1RSMTBCODRKdE9GcEVMWHp5eWtjU0Z2d1hkaG5SNDBXWHdE?= =?utf-8?B?YXNMRUl2eDRHWDBzRkYramEvZ3l3L0JLOHJOVkFKZTg3ZGtrMGNKV3NLWndP?= =?utf-8?B?bHlDRUtIRi9BcW82NmEzbElSY08xUkMrK08yRTBjNk5MSk1rSU9LK2c4MWRl?= =?utf-8?B?TURWVjRCUERCMk8rTGJ6ZGFyWWZRWWU3T3N4Zkl2Y0k0ZWN2WSticUVqc0g1?= =?utf-8?B?UHdDZmZPRVFXSHNnQWhacGREdi93YjgwRCs2RWlCazNTcVRLSUNnYXlzODNu?= =?utf-8?B?dGlBWU8rTThCaVpkdFQxVGR1VVNlKzVJTW5mcy80eFlEY0lyalRRL3RaN3Iz?= =?utf-8?B?Mzl5NU94STRBYXBudFNKY2l0cUg2bGRYU0NnUkp0dFFBL28xQmkycjlqS1pq?= =?utf-8?B?Z2t0d09TV1ZhbnBjRStKdkowL09uQWI2eWIrdHlMNDE5aVozeXVZelR3WDNQ?= =?utf-8?B?YVR2T0tSVFdIblBqRWIvdVdkZUEyM3IzNXdxY1lJSXNMcmg0am13QmU4Qmoz?= =?utf-8?B?SVMxM3B1R0QwZm1tbDByV1ZPL2lKdjVFQ0REcm5qTmsraExNK1p2bG5kQWFG?= =?utf-8?B?U1hoanRRZ1FnWlFNY2xaVi9GZWwxMUJMbjcrOWpGWXdtb1NHdXVwMC9vbUxB?= =?utf-8?B?dTUrOHNsWUpOa0RiSHhXYm5kUGpxYi8vZVR1aFB6QWp0dUxEUklvYkFiWlUx?= =?utf-8?B?dW5IaTBZd3pTaVYyaWZVbGJQL3hWZjJDR0pnWnNEcG9FbTFsZ3JIcHBnK0Fm?= =?utf-8?B?eG1id1ZSOTZrS2xRWGh6M2RlVElFM1Rqdm9tTUc3aSt4NHg4Wk9QeUFpS1ho?= =?utf-8?B?YmIyaGZUTXJER20wZUNNRm1NZi9FRkhYYnBZbFBpVXNvS0d3bS9VZUEvUmRz?= =?utf-8?B?UHBmOEpzWHBodDJNeElRanZzenl4VFZrYitpUXJuZnJFWlBqSlRCTTUvQ2Zi?= =?utf-8?B?NFE9PQ==?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7dd8dd6c-1c09-4344-c419-08dcf9870eed X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9251.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2024 08:36:04.8160 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: T+JqzI+LqDyScBYMivivW9wxvwdWk3jvu2NtmHDCfHnjVrtHo3DDllBLr7KAq2W2DSimIYEaOSCSXKPRdni5HBf833tTJC+YHF2kqsyK0Ak= X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB7199 Content-Type: text/plain; charset="utf-8" From: Ciprian Marian Costea Add a RTC driver for NXP S32G2/S32G3 SoCs. The RTC module is used to enable Suspend to RAM (STR) support on NXP S32G2/S32G3 SoC based boards. RTC tracks clock time during system suspend. RTC from S32G2/S32G3 is not battery-powered and it is not kept alive during system reset. Co-developed-by: Bogdan Hamciuc Signed-off-by: Bogdan Hamciuc Co-developed-by: Ghennadi Procopciuc Signed-off-by: Ghennadi Procopciuc Signed-off-by: Ciprian Marian Costea --- drivers/rtc/Kconfig | 11 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-s32g.c | 803 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 815 insertions(+) create mode 100644 drivers/rtc/rtc-s32g.c diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index e87c3d74565c..18fc3577f6cd 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -2054,4 +2054,15 @@ config RTC_DRV_SSD202D This driver can also be built as a module, if so, the module will be called "rtc-ssd20xd". =20 +config RTC_DRV_S32G + tristate "RTC driver for S32G2/S32G3 SoCs" + depends on ARCH_S32 || COMPILE_TEST + depends on COMMON_CLK + help + Say yes to enable RTC driver for platforms based on the + S32G2/S32G3 SoC family. + + This RTC module can be used as a wakeup source. + Please note that it is not battery-powered. + endif # RTC_CLASS diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 8ee79cb18322..a63d010a753c 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -158,6 +158,7 @@ obj-$(CONFIG_RTC_DRV_RX8025) +=3D rtc-rx8025.o obj-$(CONFIG_RTC_DRV_RX8111) +=3D rtc-rx8111.o obj-$(CONFIG_RTC_DRV_RX8581) +=3D rtc-rx8581.o obj-$(CONFIG_RTC_DRV_RZN1) +=3D rtc-rzn1.o +obj-$(CONFIG_RTC_DRV_S32G) +=3D rtc-s32g.o obj-$(CONFIG_RTC_DRV_S35390A) +=3D rtc-s35390a.o obj-$(CONFIG_RTC_DRV_S3C) +=3D rtc-s3c.o obj-$(CONFIG_RTC_DRV_S5M) +=3D rtc-s5m.o diff --git a/drivers/rtc/rtc-s32g.c b/drivers/rtc/rtc-s32g.c new file mode 100644 index 000000000000..a05e23ece72a --- /dev/null +++ b/drivers/rtc/rtc-s32g.c @@ -0,0 +1,803 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define RTCC_OFFSET 0x4ul +#define RTCS_OFFSET 0x8ul +#define RTCCNT_OFFSET 0xCul +#define APIVAL_OFFSET 0x10ul +#define RTCVAL_OFFSET 0x14ul + +/* RTCC fields */ +#define RTCC_CNTEN BIT(31) +#define RTCC_RTCIE_SHIFT 30 +#define RTCC_RTCIE BIT(RTCC_RTCIE_SHIFT) +#define RTCC_ROVREN BIT(28) +#define RTCC_APIEN BIT(15) +#define RTCC_APIIE BIT(14) +#define RTCC_CLKSEL_OFFSET 12 +#define RTCC_CLKSEL_MASK GENMASK(13, 12) +#define RTCC_CLKSEL(n) (((n) << 12) & RTCC_CLKSEL_MASK) +#define RTCC_DIV512EN BIT(11) +#define RTCC_DIV32EN BIT(10) + +/* RTCS fields */ +#define RTCS_RTCF BIT(29) +#define RTCS_INV_RTC BIT(18) +#define RTCS_APIF BIT(13) +#define RTCS_ROVRF BIT(10) + +#define ROLLOVER_VAL GENMASK(31, 0) +#define RTC_SYNCH_TIMEOUT (100 * USEC_PER_MSEC) + +#define RTC_CLK_MUX_SIZE 4 + +/* + * S32G2 and S32G3 SoCs have RTC clock source 1 reserved and + * should not be used. + */ +#define RTC_QUIRK_SRC1_RESERVED BIT(2) + +#define to_rtcpriv(_hw) container_of(_hw, struct rtc_priv, clk) + +enum { + RTC_CLK_SRC0 =3D 0, + RTC_CLK_SRC1, + RTC_CLK_SRC2, + RTC_CLK_SRC3 +}; + +enum { + DIV1 =3D 1, + DIV32 =3D 32, + DIV512 =3D 512, + DIV512_32 =3D 16384 +}; + +struct rtc_time_base { + s64 sec; + u64 cycles; + u64 rollovers; + struct rtc_time tm; +}; + +struct rtc_priv { + struct rtc_device *rdev; + u8 __iomem *rtc_base; + struct clk_hw clk; + struct clk *ipg; + const struct rtc_soc_data *rtc_data; + struct rtc_time_base base; + u64 rtc_hz; + u64 rollovers; + int dt_irq_id; + int runtime_src_idx; + int suspend_src_idx; + u32 runtime_div; + u32 suspend_div; +}; + +struct rtc_soc_data { + int default_runtime_src_idx; + int default_suspend_src_idx; + u32 default_runtime_div; + u32 default_suspend_div; + u32 quirks; +}; + +static const struct rtc_soc_data rtc_s32g2_data =3D { + .default_runtime_src_idx =3D RTC_CLK_SRC2, + .default_suspend_src_idx =3D RTC_CLK_MUX_SIZE + RTC_CLK_SRC0, + .default_runtime_div =3D DIV512, + .default_suspend_div =3D DIV512, + .quirks =3D RTC_QUIRK_SRC1_RESERVED, +}; + +static int is_src1_reserved(struct rtc_priv *priv) +{ + return priv->rtc_data->quirks & RTC_QUIRK_SRC1_RESERVED; +} + +static u64 cycles_to_sec(u64 hz, u64 cycles) +{ + return div_u64(cycles, hz); +} + +/* + * Convert a number of seconds to a value suitable for RTCVAL in our clock= 's + * current configuration. + * @rtcval: The value to go into RTCVAL[RTCVAL] + * Returns: 0 for success, -EINVAL if @seconds push the counter at least + * twice the rollover interval + */ +static int sec_to_rtcval(const struct rtc_priv *priv, + unsigned long seconds, u32 *rtcval) +{ + u32 rtccnt, delta_cnt; + u32 target_cnt =3D 0; + + /* For now, support at most one rollover of the counter */ + if (!seconds || seconds > cycles_to_sec(priv->rtc_hz, ROLLOVER_VAL)) + return -EINVAL; + + /* + * RTCCNT is read-only; we must return a value relative to the + * current value of the counter (and hope we don't linger around + * too much before we get to enable the interrupt) + */ + delta_cnt =3D seconds * priv->rtc_hz; + rtccnt =3D ioread32(priv->rtc_base + RTCCNT_OFFSET); + + if (~rtccnt < delta_cnt) + target_cnt =3D (delta_cnt - ~rtccnt); + else + target_cnt =3D rtccnt + delta_cnt; + + /* + * According to RTCVAL register description, + * its minimum value should be 4. + */ + if (unlikely(target_cnt < 4)) + target_cnt =3D 4; + + *rtcval =3D target_cnt; + + return 0; +} + +static irqreturn_t rtc_handler(int irq, void *dev) +{ + struct rtc_priv *priv =3D platform_get_drvdata(dev); + u32 status; + + status =3D ioread32(priv->rtc_base + RTCS_OFFSET); + if (status & RTCS_ROVRF) { + if (priv->rollovers =3D=3D ULONG_MAX) + priv->rollovers =3D 0; + else + priv->rollovers++; + } + + if (status & RTCS_RTCF) { + iowrite32(0x0, priv->rtc_base + RTCVAL_OFFSET); + rtc_update_irq(priv->rdev, 1, RTC_AF); + } + + if (status & RTCS_APIF) + rtc_update_irq(priv->rdev, 1, RTC_PF); + + iowrite32(status, priv->rtc_base + RTCS_OFFSET); + + return IRQ_HANDLED; +} + +static int get_time_left(struct device *dev, struct rtc_priv *priv, + u32 *sec) +{ + u32 rtccnt =3D ioread32(priv->rtc_base + RTCCNT_OFFSET); + u32 rtcval =3D ioread32(priv->rtc_base + RTCVAL_OFFSET); + + if (rtcval < rtccnt) { + dev_err(dev, "RTC timer expired before entering suspend\n"); + return -EIO; + } + + *sec =3D cycles_to_sec(priv->rtc_hz, rtcval - rtccnt); + + return 0; +} + +static s64 s32g_rtc_get_time_or_alrm(struct rtc_priv *priv, + u32 offset) +{ + u64 cycles, base_cycles; + u32 counter; + s64 sec; + + counter =3D ioread32(priv->rtc_base + offset); + cycles =3D priv->rollovers * ROLLOVER_VAL + counter; + base_cycles =3D priv->base.cycles + priv->base.rollovers * ROLLOVER_VAL; + + if (cycles < base_cycles) + return -EINVAL; + + cycles -=3D base_cycles; + sec =3D priv->base.sec + cycles_to_sec(priv->rtc_hz, cycles); + + return sec; +} + +static int s32g_rtc_read_time(struct device *dev, + struct rtc_time *tm) +{ + struct rtc_priv *priv =3D dev_get_drvdata(dev); + s64 sec; + + if (!tm) + return -EINVAL; + + sec =3D s32g_rtc_get_time_or_alrm(priv, RTCCNT_OFFSET); + if (sec < 0) + return -EINVAL; + + rtc_time64_to_tm(sec, tm); + + return 0; +} + +static int s32g_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct rtc_priv *priv =3D dev_get_drvdata(dev); + u32 rtcc, sec_left; + s64 sec; + + if (!alrm) + return -EINVAL; + + sec =3D s32g_rtc_get_time_or_alrm(priv, RTCVAL_OFFSET); + if (sec < 0) + return -EINVAL; + + rtc_time64_to_tm(sec, &alrm->time); + + rtcc =3D ioread32(priv->rtc_base + RTCC_OFFSET); + alrm->enabled =3D sec && (rtcc & RTCC_RTCIE); + + alrm->pending =3D 0; + if (alrm->enabled && !get_time_left(dev, priv, &sec_left)) + alrm->pending =3D !!sec_left; + + return 0; +} + +static int s32g_rtc_alarm_irq_enable(struct device *dev, unsigned int enab= led) +{ + struct rtc_priv *priv =3D dev_get_drvdata(dev); + u32 rtcc; + + if (!priv->dt_irq_id) + return -EIO; + + /* + * RTCIE cannot be deasserted because it will also disable the + * rollover interrupt. + */ + rtcc =3D ioread32(priv->rtc_base + RTCC_OFFSET); + if (enabled) + rtcc |=3D RTCC_RTCIE; + + iowrite32(rtcc, priv->rtc_base + RTCC_OFFSET); + + return 0; +} + +static int s32g_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct rtc_priv *priv =3D dev_get_drvdata(dev); + struct rtc_time time_crt; + long long t_crt, t_alrm; + u32 rtcval, rtcs; + int ret =3D 0; + + iowrite32(0x0, priv->rtc_base + RTCVAL_OFFSET); + + t_alrm =3D rtc_tm_to_time64(&alrm->time); + + /* + * Assuming the alarm is being set relative to the same time + * returned by our s32g_rtc_read_time callback + */ + ret =3D s32g_rtc_read_time(dev, &time_crt); + if (ret) + return ret; + + t_crt =3D rtc_tm_to_time64(&time_crt); + if (t_alrm <=3D t_crt) { + dev_warn(dev, "Alarm is set in the past\n"); + return -EINVAL; + } + + ret =3D sec_to_rtcval(priv, t_alrm - t_crt, &rtcval); + if (ret) { + /* + * Rollover support enables RTC alarm + * for a maximum timespan of ~3 months. + */ + dev_warn(dev, "Alarm is set too far in the future\n"); + return ret; + } + + ret =3D read_poll_timeout(ioread32, rtcs, !(rtcs & RTCS_INV_RTC), + 0, RTC_SYNCH_TIMEOUT, false, priv->rtc_base + RTCS_OFFSET); + if (ret) { + dev_err(dev, "Synchronization failed\n"); + return ret; + } + + iowrite32(rtcval, priv->rtc_base + RTCVAL_OFFSET); + + return 0; +} + +static int s32g_rtc_set_time(struct device *dev, + struct rtc_time *time) +{ + struct rtc_priv *priv =3D dev_get_drvdata(dev); + + if (!time) + return -EINVAL; + + priv->base.rollovers =3D priv->rollovers; + priv->base.cycles =3D ioread32(priv->rtc_base + RTCCNT_OFFSET); + priv->base.sec =3D rtc_tm_to_time64(time); + + return 0; +} + +/* + * Disable the 32-bit free running counter. + * This allows Clock Source and Divisors selection + * to be performed without causing synchronization issues. + */ +static void s32g_rtc_disable(struct rtc_priv *priv) +{ + u32 rtcc =3D ioread32(priv->rtc_base + RTCC_OFFSET); + + rtcc &=3D ~RTCC_CNTEN; + iowrite32(rtcc, priv->rtc_base + RTCC_OFFSET); +} + +static void s32g_rtc_enable(struct rtc_priv *priv) +{ + u32 rtcc =3D ioread32(priv->rtc_base + RTCC_OFFSET); + + rtcc |=3D RTCC_CNTEN; + iowrite32(rtcc, priv->rtc_base + RTCC_OFFSET); +} + +static int get_div_config(unsigned long req_rate, + unsigned long prate) +{ + if (req_rate =3D=3D prate) + return DIV1; + else if (req_rate =3D=3D prate / (DIV512 * DIV32)) + return DIV512_32; + else if (req_rate =3D=3D prate / DIV512) + return DIV512; + else if (req_rate =3D=3D prate / DIV32) + return DIV32; + + return 0; +} + +static void adjust_dividers(struct rtc_priv *priv, + u32 div_val, u32 *reg) +{ + switch (div_val) { + case DIV512_32: + *reg |=3D RTCC_DIV512EN; + *reg |=3D RTCC_DIV32EN; + break; + case DIV512: + *reg |=3D RTCC_DIV512EN; + break; + case DIV32: + *reg |=3D RTCC_DIV32EN; + break; + default: + return; + } + + priv->rtc_hz /=3D div_val; +} + +static unsigned long get_prate_by_index(struct clk_hw *hw, + u8 index) +{ + struct clk_hw *parent; + + parent =3D clk_hw_get_parent_by_index(hw, index); + if (!parent) + return -EINVAL; + + return clk_hw_get_rate(parent); +} + +static int rtc_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct rtc_priv *priv =3D to_rtcpriv(hw); + struct device *dev =3D priv->rdev->dev.parent; + int i, num_parents =3D clk_hw_get_num_parents(hw); + u32 config; + + for (i =3D 0; i < num_parents; i++) { + config =3D get_div_config(req->rate, get_prate_by_index(hw, i)); + if (config) { + if (i < RTC_CLK_MUX_SIZE) + /* Runtime clk source divisors */ + priv->runtime_div =3D config; + else + /* Suspend clk source divisors */ + priv->suspend_div =3D config; + + return 0; + } + } + + dev_err(dev, "Failed to determine RTC clock rate\n"); + return -EINVAL; +} + +static u8 rtc_clk_get_parent(struct clk_hw *hw) +{ + struct rtc_priv *priv =3D to_rtcpriv(hw); + + return (ioread32(priv->rtc_base + RTCC_OFFSET) & + RTCC_CLKSEL_MASK) >> RTCC_CLKSEL_OFFSET; +} + +static int rtc_clk_src_switch(struct clk_hw *hw, u8 src) +{ + struct rtc_priv *priv =3D to_rtcpriv(hw); + struct device *dev =3D priv->rdev->dev.parent; + u32 rtcc =3D 0; + + switch (src % RTC_CLK_MUX_SIZE) { + case RTC_CLK_SRC0: + rtcc |=3D RTCC_CLKSEL(RTC_CLK_SRC0); + break; + case RTC_CLK_SRC1: + if (is_src1_reserved(priv)) + return -EOPNOTSUPP; + rtcc |=3D RTCC_CLKSEL(RTC_CLK_SRC1); + break; + case RTC_CLK_SRC2: + rtcc |=3D RTCC_CLKSEL(RTC_CLK_SRC2); + break; + case RTC_CLK_SRC3: + rtcc |=3D RTCC_CLKSEL(RTC_CLK_SRC3); + break; + default: + dev_err(dev, "Invalid clock mux parent: %d\n", src); + return -EINVAL; + } + + priv->rtc_hz =3D get_prate_by_index(hw, src); + if (!priv->rtc_hz) { + dev_err(dev, "Failed to get RTC frequency\n"); + return -EINVAL; + } + + if (src < RTC_CLK_MUX_SIZE) + adjust_dividers(priv, priv->runtime_div, &rtcc); + else + adjust_dividers(priv, priv->suspend_div, &rtcc); + + rtcc |=3D RTCC_RTCIE | RTCC_ROVREN; + /* + * Make sure the CNTEN is 0 before we configure + * the clock source and dividers. + */ + s32g_rtc_disable(priv); + iowrite32(rtcc, priv->rtc_base + RTCC_OFFSET); + s32g_rtc_enable(priv); + + return 0; +} + +static int rtc_clk_set_parent(struct clk_hw *hw, u8 index) +{ + struct rtc_priv *priv =3D to_rtcpriv(hw); + + /* + * 0-3 IDs are Runtime clk sources + * 4-7 IDs are Suspend clk sources + */ + if (index < RTC_CLK_MUX_SIZE) { + /* Runtime clk source */ + priv->runtime_src_idx =3D index; + return 0; + } else if (index < RTC_CLK_MUX_SIZE * 2) { + /* Suspend clk source */ + priv->suspend_src_idx =3D index; + return 0; + } + + return -EINVAL; +} + +static const struct rtc_class_ops rtc_ops =3D { + .read_time =3D s32g_rtc_read_time, + .set_time =3D s32g_rtc_set_time, + .read_alarm =3D s32g_rtc_read_alarm, + .set_alarm =3D s32g_rtc_set_alarm, + .alarm_irq_enable =3D s32g_rtc_alarm_irq_enable, +}; + +static const struct clk_ops rtc_clk_ops =3D { + .determine_rate =3D rtc_clk_determine_rate, + .get_parent =3D rtc_clk_get_parent, + .set_parent =3D rtc_clk_set_parent, +}; + +static int priv_dts_init(struct rtc_priv *priv, struct device *dev) +{ + struct platform_device *pdev =3D to_platform_device(dev); + + priv->ipg =3D devm_clk_get(dev, "ipg"); + if (IS_ERR(priv->ipg)) { + dev_err(dev, "Failed to get 'ipg' clock\n"); + return PTR_ERR(priv->ipg); + } + + priv->dt_irq_id =3D platform_get_irq(pdev, 0); + if (priv->dt_irq_id < 0) { + dev_err(dev, "Error reading interrupt # from dts\n"); + return priv->dt_irq_id; + } + + return 0; +} + +static int rtc_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct rtc_priv *priv; + static const char *parents[RTC_CLK_MUX_SIZE * 2] =3D { + "rtc_runtime_s0", + "rtc_runtime_s1", + "rtc_runtime_s2", + "rtc_runtime_s3", + "rtc_standby_s0", + "rtc_standby_s1", + "rtc_standby_s2", + "rtc_standby_s3" + }; + struct clk_init_data clk_init =3D { + .name =3D "rtc_clk", + .ops =3D &rtc_clk_ops, + .flags =3D 0, + .parent_names =3D parents, + .num_parents =3D ARRAY_SIZE(parents), + }; + int ret =3D 0; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->rtc_data =3D of_device_get_match_data(dev); + if (!priv->rtc_data) + return -ENODEV; + + priv->rtc_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->rtc_base)) + return dev_err_probe(dev, PTR_ERR(priv->rtc_base), + "Failed to map registers\n"); + + device_init_wakeup(dev, true); + + ret =3D priv_dts_init(priv, dev); + if (ret) + return ret; + + ret =3D clk_prepare_enable(priv->ipg); + if (ret) { + dev_err(dev, "Cannot enable 'ipg' clock, error: %d\n", ret); + return ret; + } + + priv->rdev =3D devm_rtc_allocate_device(dev); + if (IS_ERR(priv->rdev)) { + dev_err(dev, "Failed to allocate RTC device\n"); + ret =3D PTR_ERR(priv->rdev); + goto disable_rtc; + } + + if (!of_property_present(dev->of_node, + "assigned-clock-parents")) { + /* + * If parent clocks are not specified via DT + * use SoC specific defaults for clock source mux + * and divisors. + */ + priv->runtime_src_idx =3D priv->rtc_data->default_runtime_src_idx; + priv->suspend_src_idx =3D priv->rtc_data->default_suspend_src_idx; + priv->runtime_div =3D priv->rtc_data->default_runtime_div; + priv->suspend_div =3D priv->rtc_data->default_suspend_div; + } else { + priv->runtime_src_idx =3D -EINVAL; + priv->suspend_src_idx =3D -EINVAL; + } + + priv->clk.init =3D &clk_init; + ret =3D devm_clk_hw_register(dev, &priv->clk); + if (ret) { + dev_err(dev, "Failed to register rtc_clk clk\n"); + goto disable_ipg_clk; + } + + ret =3D of_clk_add_hw_provider(dev->of_node, + of_clk_hw_simple_get, priv->clk.clk); + if (ret) { + dev_err(dev, "Failed to add rtc_clk clk provider\n"); + goto disable_ipg_clk; + } + + if (priv->runtime_src_idx < 0) { + ret =3D priv->runtime_src_idx; + dev_err(dev, "RTC runtime clock source is not specified\n"); + goto disable_ipg_clk; + } + + ret =3D rtc_clk_src_switch(&priv->clk, priv->runtime_src_idx); + if (ret) { + dev_err(dev, "Failed clk source switch, err: %d\n", ret); + goto disable_ipg_clk; + } + + platform_set_drvdata(pdev, priv); + priv->rdev->ops =3D &rtc_ops; + + ret =3D devm_rtc_register_device(priv->rdev); + if (ret) { + dev_err(dev, "Failed to register RTC device\n"); + goto disable_rtc; + } + + ret =3D devm_request_irq(dev, priv->dt_irq_id, + rtc_handler, 0, dev_name(dev), pdev); + if (ret) { + dev_err(dev, "Request interrupt %d failed, error: %d\n", + priv->dt_irq_id, ret); + goto disable_rtc; + } + + return 0; + +disable_ipg_clk: + clk_disable_unprepare(priv->ipg); +disable_rtc: + s32g_rtc_disable(priv); + return ret; +} + +static void rtc_remove(struct platform_device *pdev) +{ + struct rtc_priv *priv =3D platform_get_drvdata(pdev); + + s32g_rtc_disable(priv); +} + +static void __maybe_unused enable_api_irq(struct device *dev, unsigned in= t enabled) +{ + struct rtc_priv *priv =3D dev_get_drvdata(dev); + u32 api_irq =3D RTCC_APIEN | RTCC_APIIE; + u32 rtcc; + + rtcc =3D ioread32(priv->rtc_base + RTCC_OFFSET); + if (enabled) + rtcc |=3D api_irq; + else + rtcc &=3D ~api_irq; + iowrite32(rtcc, priv->rtc_base + RTCC_OFFSET); +} + +static int __maybe_unused rtc_suspend(struct device *dev) +{ + struct rtc_priv *init_priv =3D dev_get_drvdata(dev); + struct rtc_priv priv; + long long base_sec; + int ret =3D 0; + u32 rtcval; + u32 sec; + + if (!device_may_wakeup(dev)) + return 0; + + if (init_priv->suspend_src_idx < 0) + return 0; + + if (rtc_clk_get_parent(&init_priv->clk) =3D=3D init_priv->suspend_src_idx) + return 0; + + /* Save last known timestamp before we switch clocks and reinit RTC */ + ret =3D s32g_rtc_read_time(dev, &init_priv->base.tm); + if (ret) + return ret; + + /* + * Use a local copy of the RTC control block to + * avoid restoring it on resume path. + */ + memcpy(&priv, init_priv, sizeof(priv)); + + ret =3D get_time_left(dev, init_priv, &sec); + if (ret) + return ret; + + /* Adjust for the number of seconds we'll be asleep */ + base_sec =3D rtc_tm_to_time64(&init_priv->base.tm); + base_sec +=3D sec; + rtc_time64_to_tm(base_sec, &init_priv->base.tm); + + ret =3D rtc_clk_src_switch(&priv.clk, priv.suspend_src_idx); + if (ret) { + dev_err(dev, "Failed clk source switch, err: %d\n", ret); + return ret; + } + + ret =3D sec_to_rtcval(&priv, sec, &rtcval); + if (ret) { + dev_warn(dev, "Alarm is too far in the future\n"); + return ret; + } + + s32g_rtc_alarm_irq_enable(dev, 0); + enable_api_irq(dev, 1); + iowrite32(rtcval, priv.rtc_base + APIVAL_OFFSET); + iowrite32(0, priv.rtc_base + RTCVAL_OFFSET); + + return ret; +} + +static int __maybe_unused rtc_resume(struct device *dev) +{ + struct rtc_priv *priv =3D dev_get_drvdata(dev); + int ret; + + if (!device_may_wakeup(dev)) + return 0; + + if (rtc_clk_get_parent(&priv->clk) =3D=3D priv->runtime_src_idx) + return 0; + + /* Disable wake-up interrupts */ + enable_api_irq(dev, 0); + + ret =3D rtc_clk_src_switch(&priv->clk, priv->runtime_src_idx); + if (ret) { + dev_err(dev, "Failed clk source switch, err: %d\n", ret); + return ret; + } + + /* + * Now RTCCNT has just been reset, and is out of sync with priv->base; + * reapply the saved time settings + */ + return s32g_rtc_set_time(dev, &priv->base.tm); +} + +static const struct of_device_id rtc_dt_ids[] =3D { + { .compatible =3D "nxp,s32g2-rtc", .data =3D &rtc_s32g2_data}, + { /* sentinel */ }, +}; + +static SIMPLE_DEV_PM_OPS(rtc_pm_ops, + rtc_suspend, rtc_resume); + +static struct platform_driver rtc_driver =3D { + .driver =3D { + .name =3D "s32g-rtc", + .pm =3D &rtc_pm_ops, + .of_match_table =3D rtc_dt_ids, + }, + .probe =3D rtc_probe, + .remove =3D rtc_remove, +}; +module_platform_driver(rtc_driver); + +MODULE_AUTHOR("NXP"); +MODULE_DESCRIPTION("NXP RTC driver for S32G2/S32G3"); +MODULE_LICENSE("GPL"); --=20 2.45.2 From nobody Mon Dec 2 14:50:23 2024 Received: from EUR02-DB5-obe.outbound.protection.outlook.com (mail-db5eur02on2049.outbound.protection.outlook.com [40.107.249.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2272189B8E; Thu, 31 Oct 2024 08:36:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.249.49 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730363779; cv=fail; b=HqeGj3a0AOnZJzfkDR2ciuTvDU9/npz4A5uws4TzFsshmuuLcYJS4DN4t/ztY7sOtFEQQ3fjLXsI28IdNQ2XRqfPR8XKzWBD/Erx6WztuBJArVo+1gRKpZSwybdfd686dghIzjZ/soEcySNnppmRb8z8qpSd0HBlSvdLflIVEEk= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730363779; c=relaxed/simple; bh=bL3NkImcly2cuAHYW4cMEdSXW4vh9dDqAo2Dbi22W/k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=otX//sOuMh12Z7+B/iCZ7ZoWvPgPu9bot+kpTj+wl2y/10bpJ05xtI7R3WKs2gn4WqGzjcggDNOsPFGoKmxXeXBhDwTi4z5OKoCWx3stHqQEC8T46985n0+nx4iZTidY8IanGrgC9uJ35yktIImPzEV/5xLwdWW16UUbSMM4mEc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com; spf=pass smtp.mailfrom=oss.nxp.com; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b=nG2lFSIs; arc=fail smtp.client-ip=40.107.249.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b="nG2lFSIs" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=J4Az4qsONsBPtWAJUagUs8MV/vrkX8Afg8ablfiDapdsLvOPJeumvoMhCTZKV5H1h0ZpnScBDzQndrW9zalvUGl/sjff5Z/LKxBhTubb7tuZwObp/NfqbwTkZVyt9jPYnvNdcw1j4Je6+z1NnbjTYKxFoU+xn3dzD2CsqSBdwlJ7OpxjS9yIdTTDrXTJcq4HNg2a/3v0z45mSAwPLr8nqiMWUfkZbBhK6mvAsulQxrkAKp2a5bOefi2xtS1rF0YmgR9JvTTz4Kr7tXEPTTZfjIP9qyWHucA9kI9SW7TibRw9gkYeXzT1/B80i9GUSHLq1StvITmmGM3yvoJhBWIPIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=RiuOkCfpsNxZrkFZMYxjLbzR4TnUVZDDLO1KoGr8M6Y=; b=K0ACngsGzsb4q/EDOEdS+TkHpcwSIKpd9HycBDwAOe6+87Yv2F3686FJCcsFg6WAiub3svMapDOQAA6ooLKUAquv0nnrvsF1s1beaNa+8x4eSAv1zU3eFd1bF0YmqgRsgzy5RMEpDK5l2xd2G1/EG+6kyoK6TQAsOPpSnvDziasitIPik9JvjC7cZgrZudDFxaPkQPm4SZwNxTNcL5tCX+h4ona7w/zbAE/HRGKf2qkZqTc39ktLQgd8Sw9opMosfed14RNgGucWZcI1Yj3BGaVQ3c6yNVKnj60jr3k7fsha63iJvb1JOweTSBKYDW27XcJqxVnAlzmj4LYy37oahA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector1-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=RiuOkCfpsNxZrkFZMYxjLbzR4TnUVZDDLO1KoGr8M6Y=; b=nG2lFSIstQB9zNFUL6amZp52/3ySTcnES31Zw69OEhaT9n9xRb/T0lYWtgVZh7xgXpUZgvM8Eyg0IxA4NA71cTLbR8iIEX4N5rKUXIxBM8creCDq2DboDd6RwexsOwql06WSdvZAz9gHeTLFSO5RaSYpd4yyyltfihNdtDOQgAWqxeA5h/xavuq7GBr0BTOYmPQV9GxGd1e54VKg5ZV2nkAWevDbRTMrZeSTtD2eYT/cN74EcNAaOatNzO4iJ9DfJtNyi8AB4qevb9joWVezBKg9nTg5HrGUxDyEhA+8z3Z5krIs8rQiQ0ZIFEf9sLbP1KLUy2cd6rLX+mKvuFn2IA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from DU0PR04MB9251.eurprd04.prod.outlook.com (2603:10a6:10:352::15) by VI1PR04MB7199.eurprd04.prod.outlook.com (2603:10a6:800:11d::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.32; Thu, 31 Oct 2024 08:36:06 +0000 Received: from DU0PR04MB9251.eurprd04.prod.outlook.com ([fe80::708f:69ee:15df:6ebd]) by DU0PR04MB9251.eurprd04.prod.outlook.com ([fe80::708f:69ee:15df:6ebd%6]) with mapi id 15.20.8093.025; Thu, 31 Oct 2024 08:36:06 +0000 From: Ciprian Costea To: Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP S32 Linux Team , Christophe Lizzi , Alberto Ruiz , Enric Balletbo , Ciprian Marian Costea Subject: [PATCH v3 3/4] arm64: defconfig: add S32G RTC module support Date: Thu, 31 Oct 2024 10:35:56 +0200 Message-ID: <20241031083557.2156751-4-ciprianmarian.costea@oss.nxp.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241031083557.2156751-1-ciprianmarian.costea@oss.nxp.com> References: <20241031083557.2156751-1-ciprianmarian.costea@oss.nxp.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: AM0PR04CA0144.eurprd04.prod.outlook.com (2603:10a6:208:55::49) To DU0PR04MB9251.eurprd04.prod.outlook.com (2603:10a6:10:352::15) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9251:EE_|VI1PR04MB7199:EE_ X-MS-Office365-Filtering-Correlation-Id: 6cdda8a9-7cd1-4f58-5766-08dcf9871007 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|366016|1800799024; X-Microsoft-Antispam-Message-Info: =?utf-8?B?YkVNTlpka20rVFBhaW9aNkNicEJIVS9QVVRXYmtBeUJRd09PVHo0QXVWRk1H?= =?utf-8?B?dWdOTkJQeS9mNXMwcTdTdXhrcEJVeUZZY0xYbFVxM20rank4c1RDRXBZUUdQ?= =?utf-8?B?eExNQVd1SjZwWks0Tnp6bzBqZE01b3VyekYvZVp2dEFPa2ptMnFObHJOYTdS?= =?utf-8?B?VzJ6Yk8ybGJVVFM5WkFkWUlyU2h4R2tMYUJWSnpmWm1XbTNuUExlc2ZaZCt1?= =?utf-8?B?emhUb1BvSkZna0lTVUxVdDNkV1ZaWjhaVTZwNmpOVjYyUEhYZ3dmUTNmczgz?= =?utf-8?B?M2dmZFFsWlNoVG1WR0dYelgzYUtSUGNxQU9PNk5TT1FGcVlKWWJ2eUdKTk1t?= =?utf-8?B?L2o1YmViRmJ3LzBYei85ZkZDNUZKUmQ4Rkd6SGlIbUhWSmRuM1MyNW5LczhO?= =?utf-8?B?Sk5mSVNHVnlncDd2UDUwUTZKUGZLM0h1dWI0MzBZWGpnR3VEK1NHL0hlQ0tP?= =?utf-8?B?Q0VhSk54ZXJEdjQ3MTRzRUNQRG9iRDd6Wkc4RktvK2xiU1U1aVM3TGsreHps?= =?utf-8?B?alMyRk5WNmRYZnF4UEpVWHBBYzhLVDluNFlFc0xiYzcyNWt3djdoaTVnN0Z3?= =?utf-8?B?TG1JU1NNOFlrOHNMdXhiRGRjRUVkdlRkOVlSYnAveFJRRXlMb3FpUkdCSVVX?= =?utf-8?B?TzRkYW11NFAzSkFXbW9vUnppczBzS3Rqc1hvSnpqN25ZNW5GTGRNcEE3UVNu?= =?utf-8?B?VTlVeXg4TS93YmVDR0RYR1pESlJvbUZTOGtPdG9zbkhlQTZ0eXlNUnowc050?= =?utf-8?B?cVUwVEVXSk96aEM4Q1d3ZFZCeGpCcWZFRGI0Vm01cEt2dlMzcmliUlhtUmtX?= =?utf-8?B?S1Z0bHJKNkp1U1NHRGRCOXZ6dkFUYXJlR0p5Q0F2TEVpbVRuSExrRkxNeXll?= =?utf-8?B?YUVhdHY3bFBEOUNnQnRvR29SWjNETTlsdFFJRy9IOHN4VVM5NjNxMWNHUkRv?= =?utf-8?B?VDRVR3lUNnN5bGo5cEh3UkYxWkFjQkptcURmclF3VFNYdG1icEh2WEs1dW8w?= =?utf-8?B?QzRvZ2pTNENyVkhVVTVFbjZWTU90R21SckwvZzJ5WTN2MlBwV2E4cnZRMmRI?= =?utf-8?B?ZGlUc0RyQjl6VVJjcUxIb3R6YlpFQ0JEMjR1ZG1wQWFpYWRibXVvRjBQZmZM?= =?utf-8?B?VHZSUkNCMy9NcVB2dURLQllUK28rdzVGdTVhMkJsV09LZ2toNmlnQitIRm5Y?= =?utf-8?B?RUt5SWV4Y1VkYmd2cnVJaXhyNDlYOGd6bzFrMkZzWVR0NnFCOXR4UEc4OGJ1?= =?utf-8?B?U1psV0xtWFdvS3dKSVFWR2RaMHJMYjRaMDBaUjdTaVpBNmM2RHl6RForeTh1?= =?utf-8?B?VlhoMjYxaVBOb2xZVVpJWmpmNUkxc0lDSmJHbXI3akI3RGx4VStpeFF4ZERB?= =?utf-8?B?R0xpckxBSmZyb1h2SElzdkFNK3hSRC9MUURrdXRPalZtUnJJUWovZm9NT2RR?= =?utf-8?B?ckpmSmNWWExleWFsNzZkWUp4ZVpEcWlTZXRLUjJQKy9lQXBtMkhIWFV2WTMz?= =?utf-8?B?YjVlMjcwZHdSN1BOS0tYVWo1L2NYZEtxbnRQakN1clZTc1FBSStKRlU3SUVt?= =?utf-8?B?cDBtNy9RY1JDZ3FPR3pQV01BNnI4eVg3ZktiNG5VZXRLQmhKd3lZU2w5VENU?= =?utf-8?B?c1RGaDdaK29wT1J2MnFiZkVNbittOXA2UFlmWkgzalhWdmwwdWJrZ29WRDRZ?= =?utf-8?B?V0hZNysrNTN5Wmt1a3dSVXg3YkwxbmVSMklOSDNpanVKWjR6S0ovUFV0dUZW?= =?utf-8?Q?rpP/nn/C+yQuD3ncKfka+ljVxGQuA2vV6K9q5WT?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DU0PR04MB9251.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(7416014)(376014)(366016)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?djNZYXpmNVVMOFkzWjY0Q1pKVFlhay9hOW04bUtPUW1TcmEwQllCbzgrZE5O?= =?utf-8?B?UjZHYzRWMUhLTTVsQWNPUThNKzlvZCtkb0MwYjBMYnIxZkQza0EvdEdjaXJ1?= =?utf-8?B?a0kvTm4yWlpmbFB1Q1hxTHdsd3YyZVY1RHZaRmJwV0ZEaDdvR1d1cG8zSi9U?= =?utf-8?B?U0hNLzhLTnBFZGxhRVNnMkRadSsxb2lXQlVIbzBiMTF4VFNVZ1RHQ3ZxcWs5?= =?utf-8?B?aXpGeDlkRzdZbUZxQ0oweXJ2NGRBK3cxYmFwREV4VCs0MG1ZYUhqYnFncmdz?= =?utf-8?B?MmJ2SnFPZW1wZEQ3bmFNMm9pSE9DR0p3VXBwVzExODB3TkVTUTkrRnNxWjlC?= =?utf-8?B?blFqMUpjVjhtbGE0U2RUeURGemxKVDByQjVWUDJrdzVJN2h6S1VjcUNFL0hu?= =?utf-8?B?cWNPOU9xM29sNzUrMFcvMzgrZnVjYVI1c2plWjJ5WHpndDdsMlZNc1JLcm9w?= =?utf-8?B?ajJkSTg1WTFiVVZ1bmwyVWl6emNCZ2RqaUQ3bERaZVBTZm9pVnp6M0NRdHVD?= =?utf-8?B?RWdhRDZ5SlVpQzl0RE15SEZUQmlUWHhxUXJTR0NUbFBqS3d2R21xT1JrRkls?= =?utf-8?B?d1l3amM0aDUzbG5sWEpFRkRyQWplQmVzZlNzZmt2U0ZMblo0K1dJaU1NYUcy?= =?utf-8?B?bGMzTThvSGdzbmNWZUFLUSs2cjNmWmozd0lBcXBUYVV6WEdlbGswUjhHWTRT?= =?utf-8?B?M0FKRWo2RFNjYzE0NUJMY3lLekthTVk5bllxaU03MWlBc3VJeEl6TjE2S0FB?= =?utf-8?B?QzBqNlR4d3A1ajA2T2RrWURvL2sxQkh6UThsdmJjWGhNT2d5dnI0YXdTbU1Z?= =?utf-8?B?emlPT3lNV1B2YUdKbzR0TmQ2YU1HTEYrbmh3U1VXUlZhNGlCUXhNcUoycnRr?= =?utf-8?B?Ymlic0c1bTdEdFI1TDBQREx3Y2Nwcmw4TEU0eHE1MHRHeHNrTHVadU8vNmRr?= =?utf-8?B?Q2N6YmFtSFlKKzVBbXdJMTZzQ2M5S1dud3IrZmkyM1JxbmtGQ0F0TjRya05y?= =?utf-8?B?SlBTa3VkS2pwNEZwdXRjcTNOWUlEbkVHdzF2RUF0RGk3MEh5aHlNaEpBRSsr?= =?utf-8?B?RGMxSDBkcUp5cHBybDhRMnpKT2VDT0o1TmFIeCswYjRnZ3V0RmVCU1FIZW1n?= =?utf-8?B?dUY5VGE4QldwRUE3dzlKVDFnQ3cwMHVneTRNTWh1OWtmRUVheUtqa3djVWZ4?= =?utf-8?B?TC84TUlaZEllRHEvME1Zbnc3T1J0eFExVGIwR0RQaFRjNGhPd1Y5OUxwZkcy?= =?utf-8?B?c1FmQVBMZFlFV1NhOWQ5b0JPZlZ0S0RWaUM3dS9DQm1MNnRZZy84K24zdFJt?= =?utf-8?B?RVFranBoMFMyb3NCWGFpMlJ4RWttRy80dWZMbTNVM1cwMVRPTEh3Z1YyY3Nv?= =?utf-8?B?NjhxRGF5M0VaT0hhZGdIMzJzSHU1RklIanY4bldXbGN2Qks1N1l4anFXOUMz?= =?utf-8?B?bDExdk4wR1NsRExTYWFwSVlJbVMzV0pOVTMyY2RKRzlJck8zS2MvMGZNcllz?= =?utf-8?B?d1BoRldyM3l5YmN5clZ5R0dpS290RzVnSDlLSlRsVkl1ZnkxcG81V25hWVcr?= =?utf-8?B?dUVBTEJ2TG1tenZ1VTdDSndIc0g0NmlpUGhTMS8rSzBnWmFMOGhWWXFFQStS?= =?utf-8?B?aHlUaVB4UHlZekluVVVhQkxrbkEzbUtGN2cweFhja3BLeElFN0VWQlJZcUIy?= =?utf-8?B?ZEFoWDZWK0J6M1Y0UXhsejAvcTFhcWxzZ01xQmhrbytrNExCQ1J1cWkzNy9p?= =?utf-8?B?OWt5elc2ejc2WXRhLzdBWGhQSHN5Ukt1bkRqY2pMQ294QTdJL2RXQkhNRUVF?= =?utf-8?B?dno3RmkrV3hzUWlIZnk2Y2tDNmpLYWh4OXZsZTY0dDkzNWhBamZKMU1hUlRG?= =?utf-8?B?NEZKVm04bmZtRGRwVE93cDRLRWRBVnJBdHlZZHRqTVVNbEVvcm1lSERWY2pn?= =?utf-8?B?QmxBcFpWeC8yL0dwTE1iR1Z4cmRGb2ZqSW4ra0xORmZTeWR4Nmw3algvTzRJ?= =?utf-8?B?cVlYZHZDenpxKzRJQ0hQUjc1THV2anlOMzJSS05XY3cyTUdncjE1elJicDJ0?= =?utf-8?B?RHUyZUJPVDlTYlJ4Q1pLc3orOFd2dzRxalU1Q3FzTzNFOGFzeXRjTFNiZG16?= =?utf-8?B?YkRhNC9kMDB0THh5aDdzdEU2NXhrbDJIRWtncmw0ZXpEV0tnanFwWG9BaEVP?= =?utf-8?B?MVE9PQ==?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6cdda8a9-7cd1-4f58-5766-08dcf9871007 X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9251.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2024 08:36:06.5851 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: kgT0EeCrkP6DtDxYo1F3Zu6A0efHI2ASqvfqWslSj19Mvnr27eZ3O+J4Sq/9k70fKGrcldXf97yBAJeapq3ARsAbQahZhce5JeJuXAgQXfA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB7199 Content-Type: text/plain; charset="utf-8" From: Ciprian Marian Costea The RTC module enables Suspend to RAM (STR) support on NXP S32G2/S32G3 SoC based boards. Signed-off-by: Ciprian Marian Costea --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5fdbfea7a5b2..584cef78c984 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1209,6 +1209,7 @@ CONFIG_RTC_DRV_DA9063=3Dm CONFIG_RTC_DRV_EFI=3Dy CONFIG_RTC_DRV_CROS_EC=3Dy CONFIG_RTC_DRV_FSL_FTM_ALARM=3Dm +CONFIG_RTC_DRV_S32G=3Dm CONFIG_RTC_DRV_S3C=3Dy CONFIG_RTC_DRV_PL031=3Dy CONFIG_RTC_DRV_SUN6I=3Dy --=20 2.45.2 From nobody Mon Dec 2 14:50:23 2024 Received: from EUR02-DB5-obe.outbound.protection.outlook.com (mail-db5eur02on2049.outbound.protection.outlook.com [40.107.249.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 79739190684; Thu, 31 Oct 2024 08:36:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.249.49 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730363781; cv=fail; b=Lle6r+sp3hMkJ4NW06FwjGgJf5LoKhKK0p/W7jWJ11yh/iyqWSyvrQUA8PWRVJ0K+lbr2o1vTdhnWIXM1os5RptBHTN8DWnPQmUq7zKUOb78fCGJN7Kt0fU0MECALmmOdbVVPAgsqYTXFReobqwLuVUGABUDfU47UDaQHlICHC4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730363781; c=relaxed/simple; bh=gPWrcsX0yNgOrxniFUUIpd4R/Sf/rzujv/lnBO6E3Vc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=WD5sX3aW4GUwqcVhRsYLZtJlhpKPhO12q+1KqfXPPbQRDN3+ItXsIP6tGexh/yzGdRj2kwi6Km2Y5cTzdxr6+9mE31IGRO1bzjcjmH7aAnXR3Fw9YnOt0qLgELICmzhAGEMMTlXT+uPhHB4ISUveKvkmjYVQB+T3CeXTCi+2qYU= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com; spf=pass smtp.mailfrom=oss.nxp.com; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b=PdE6dwuN; arc=fail smtp.client-ip=40.107.249.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b="PdE6dwuN" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=FrfDMrG5nc+OEP6gVlImGvjh7r2z+Ty0anrI9LbjvQXcezwrb3wqJ3YHU7S7tqnRB3/NSSZKJ1mEiVEEjc4HhgC6GckoG/tb71LrJ7VI6or5mXWkL81ozQ+ltk1K0/PKG/nADTTF0+5iro0SDi9gyfsK0WkNspuFXA2704SkPp9rD5z0vXVoLOH4mZV1mGooHu+HkmIerNGs/1XYQTouLLVOEUKkV/znj/M4a17BqbuhnXu/18Xyj/1kzp8qnpAedP7humeCfk23QZIYzffxEWKcIyoJcwJYl0whI+6RcrDH3KfAgvls4yo1I1j3EzgIsId9rQPC13XQVLmO/4vV2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Wh3dxdiFnnlVrzcHjBrhgCcglC+z8h3oypiIHqgl9ZY=; b=wQ5cTdMUGMg9Qy/ePdxwF1K8KC+2VkkefMbIwRA1uSI1zVdpumqqaNsL+KD2ELVS2lP2IBipvx+YHnWGbG9VyyFuqbHqWcYJn4M2TTw1M3PaO+5YxVPO9BVhmc2KEYoYw+nQBrCQoFq5cfrXQrjz+slVHUfhy5kSG7DnBB3EatTrpBn32qxukw2aE6OXasUMBaB4LkOvEGmFEKrzhkccHOEXSQjiYAwvQftHM8d4r9nd7WYukxyjOyUSWkev9pzYPKIth6IZm2pgbnkmLh8VhwLFbBd133Xh3qqB7Ko/5MtX3zfd8r1HE3c/ywLSG+RdjzKUnKP45t7JraTOV6M1Ow== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector1-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Wh3dxdiFnnlVrzcHjBrhgCcglC+z8h3oypiIHqgl9ZY=; b=PdE6dwuNfYrH/LufA/7Un+FGTuubreq0Y43u3FU6A+2TA9P8P/gVL6Ej4EcDG3FX6bOFU0Cll1v3RTUW0yQgIeqVol2l4G327AmP4cCDDcPg96IJ9s7/0IP0MP8RYTN+iZhL22E7+ROdbgRUmD/dgXWl/AUuz3L/RITvQFTyy9v0/XvBGgBEtucJwWCzLD4BlR5r/CxYJtJAaNyuLx8eNblcjSe7thu+JWMkg9Nr7lG2R5LbvNpQ7nF1FYCBAO3mH+A6Rl0dyPIrVNOPB0M31Wnr43SyPFtFpHylBmsDSOETz/g4gQGS3o+e2sKpbqImqm8k94OEvg6OQFt/WByVPg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from DU0PR04MB9251.eurprd04.prod.outlook.com (2603:10a6:10:352::15) by VI1PR04MB7199.eurprd04.prod.outlook.com (2603:10a6:800:11d::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.32; Thu, 31 Oct 2024 08:36:09 +0000 Received: from DU0PR04MB9251.eurprd04.prod.outlook.com ([fe80::708f:69ee:15df:6ebd]) by DU0PR04MB9251.eurprd04.prod.outlook.com ([fe80::708f:69ee:15df:6ebd%6]) with mapi id 15.20.8093.025; Thu, 31 Oct 2024 08:36:08 +0000 From: Ciprian Costea To: Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP S32 Linux Team , Christophe Lizzi , Alberto Ruiz , Enric Balletbo , Ciprian Marian Costea Subject: [PATCH v3 4/4] MAINTAINERS: add NXP S32G RTC driver Date: Thu, 31 Oct 2024 10:35:57 +0200 Message-ID: <20241031083557.2156751-5-ciprianmarian.costea@oss.nxp.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241031083557.2156751-1-ciprianmarian.costea@oss.nxp.com> References: <20241031083557.2156751-1-ciprianmarian.costea@oss.nxp.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: AM0PR04CA0132.eurprd04.prod.outlook.com (2603:10a6:208:55::37) To DU0PR04MB9251.eurprd04.prod.outlook.com (2603:10a6:10:352::15) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9251:EE_|VI1PR04MB7199:EE_ X-MS-Office365-Filtering-Correlation-Id: f685d535-b702-4696-76e6-08dcf9871102 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|366016|1800799024; X-Microsoft-Antispam-Message-Info: =?utf-8?B?bUVGeC9TRXY5Zk45TGxyQVBIZnJGcFFvcXpXWXRJUDB1K0xDOWFMTGNyWmN3?= =?utf-8?B?OWpIRVBMa0lsS2oyZWhKc3VKUitxamkrdTlyWWI2enl2YlF1SnVBQ2RnS2Jq?= =?utf-8?B?cU1JY1M5ejBOUjJTdFJWeEEybWZpU29GZ1M0OTRqUk16SWpFM2o0ZEpJVVFM?= =?utf-8?B?QVpqOCtWN1J0WlArQlk3bXFJRzlRdHVOK2lYYVdmSVV1WmZ2T1NPUzJNNytW?= =?utf-8?B?UDZIb2JuTVhxSWx6R1JXd3RPMXlYOFVSS1Z6MVV3NS9HdXlmOHpRZFRDRjh1?= =?utf-8?B?ZWhHOHFlVXB0azFraU9ncng3ekdha0tRdTliUjBjVVZiWWY3MnVxazFueXVB?= =?utf-8?B?MXpmSnpLazd1Z0ZHS0NYN0k4azJueUhhNXJxZ1l3NnI5cm1MTHJwNjk2VklK?= =?utf-8?B?WTZ0a2lNWjR0Ymk3QkdSTGp1c25VaVdleHFuc1ZDYWpURmFuaG1Qb3BFd0RR?= =?utf-8?B?U1ZsNEljaENlWXV6U0ttUGNrcUZlYWdCV3I0dFRiWXd3dU14VHQzbGZ6M0JL?= =?utf-8?B?RlBiL1JiNlpIQXNyejNOdGphRitIYXMvR2Foa1dPRENiTmdmTEh0VkpPWHhU?= =?utf-8?B?MnFkMFNYcyt5TDJRbGdTVk5FQVV1ZlZPTTV4U2VITmREbHU1S3M1U3E0ZTNv?= =?utf-8?B?STFOWjFDV3IybVlOV3V0clJhdjZWeStHSTh6QWVXQ2gvWEREeXY2bnh0VHRr?= =?utf-8?B?TDJ4cGxGaTRZSGtwU28yVjdvQzNFT3NYa25XcnQxc3g1aWwzWjU1eXFaNVdL?= =?utf-8?B?ZlVGKzhocFo0U3ZpbElyRHBXejl4UGM2UWFDbkVVT3VTUHBLdXFpaHE4ZC9h?= =?utf-8?B?VEk0ZzF3NlZONzllQ1UyYnNLeTVoY0dETkpjaVBUcWoxZHhUQTExWVdMY2dY?= =?utf-8?B?K2x0NksyTzh6eS9JNjRuL2R4VjNWYVpGRkQrSGd2QUtmRXhDVkg5VGl6TTJW?= =?utf-8?B?Z0U5b1gxK1BUVWdjOTNEUUw0bzlKY0Q3enNFcFo4WmdEWHc3RXBqeUhoUU43?= =?utf-8?B?elhIMStZbGpuNHpqNDRlK25LR3k0c0xIaSt2cllVeWluR0ZiaVFIb2dmRysr?= =?utf-8?B?ejVwcytJZFd1NGhrT2RjWmcvd2xBNHA5WjVJSUFiNmZwVUFBbzI3OGxrYVhR?= =?utf-8?B?M0lOcFVoSmRVVElMYUlIeFZlQXc0bTZJdEgxc3I1V1AzeXBVKzdDcTRTYWxx?= =?utf-8?B?dm5xM05aL3FmSGRmVkhId05IMGJ0OFU3NzFVa01JUktCTGhqT1VGMG1hVXpw?= =?utf-8?B?OG1UMnBnUzVxOVV0dTM4SjRoaFYyUGVrV3RxQmVzdWR6NzYveTJNcllPTDVh?= =?utf-8?B?U2JWWkVxVkppM2RXQzZFcXBDVS9tdDZ2bmZFL240eWw4dFp1STBMSUpoWFh5?= =?utf-8?B?eHpCTVRYN1RuNWR0clN0QzBRZUhmcGllNXFUaElZSG5kUU1sS1NQOFl6Zzhh?= =?utf-8?B?S1lKdTFvQTNVbERaUFhlaFVObWFUNEVieUFXeGpVQ1RzblZ3K1NNWHBjakp0?= =?utf-8?B?ZXRsdHUvYnQ4K0hUQnNxWk13eXkxTDhWekZsN3huZ0R6WnZDdU1EUHovV1VK?= =?utf-8?B?N01iWFQ0Mmt5VERWeGYxN3NZSnhQSXhZeno5L2o5UkhPa3NMYU1za2VoT2tC?= =?utf-8?B?ZWdza09ucGpJdEljdmFYRFBuNzY4K2o5aVUrejVWVldFVjl4RFdaaXlrK3k3?= =?utf-8?B?TlFJcTZ0SXJXSFFFNHQrYW53TlQzYnNRaEp2NVRKM0FrSlhwdVdyM0tBYzhC?= =?utf-8?Q?J5cWXoNKCBnlj3KjUU+PN2mCx9lkaYPULPsezTD?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DU0PR04MB9251.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(7416014)(376014)(366016)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?LzFPeXBqSy9mUWNaVTE2RXVNYjBpREZtZlUxRGcyNDRBTDNabzJBWnE2K3di?= =?utf-8?B?dExOd3BtTG1vWEZXeFlPV3NQb2FRaHZ2ZkErZGpOeHM0Vm1HSzhBbXlEdHVr?= =?utf-8?B?UjBobnBWMTA2dUtKeVJEc3VXL2NMTURsZnk1V283T0owbUZlZzNnTkl0R0s3?= =?utf-8?B?YzlrR3htOXh4bmowTFJjNDB1Q3lVeW1FSXVaek1DdkVzMytRclhUVkordkdI?= =?utf-8?B?dUcxMjBSTEVmQ1pVV0xZbU5IS1daUWx0ZVprSEloVjduamtBa0lhVDBMM2E4?= =?utf-8?B?UHR5c09MRlpFcjluU1ZJYlNqUHVjcDZMcUNNemJOTXVDL0dOMGxYU25rRDR1?= =?utf-8?B?UGVrTnJPUlBxTkNZdnRNU3UwSUhocyt3Um1SSHpzUWg4akFFNEJLTkFXR3VB?= =?utf-8?B?bUFOWXkwTmp3UGdodW9RNFZycnh6VXJpak52ZHRPMjBnbHB2L0Fud1pocFUx?= =?utf-8?B?TWFqWkt5TTZuUWdGaENqelVjVGcrZjZDb08wNnFqaFkvSHFXTy9LNmxadWpF?= =?utf-8?B?YmVmb1U2STVZbk9Ub0FHYXl2WVFVdWlZT0lhMzFhUlhHTU5KNlZMUkdGVSsx?= =?utf-8?B?WVFWa2lWalpWU1hhVnlVU21Lc2dHKzlkSTd5b09PZGwwdktpQStLQWJiaCtC?= =?utf-8?B?Q05oWGJ5K2s5MDlVWjMrbXNvZ2RncUdlOFg5dUwyR2lnTFN1YVVXaE1DcTRu?= =?utf-8?B?K2V5Y0t3b2RNWitVZksvMGNiZVdhOU9HMXZodEMwdXp4TndFQ3Ryb0doVEc2?= =?utf-8?B?S3BrZ0dpVXRibUhJYUc3VURINGsweHkxSzU0WGViUW5ITWFYYVRGb3NUSE5z?= =?utf-8?B?THZyQWFZWlpZL1lqZ05WZDRHQWxNcGZFSjMyL0xvSVJlUXlUMTNRTTM0VnBN?= =?utf-8?B?VC9wNlFUQ21QMkhDQ1RBRktaczlXMFNDcUYvSW96bVBPalJ2ajhVMEhtV0NK?= =?utf-8?B?NDNwOXhRdnJJdllsRWlPd2ZpNU0veHd5VTI3M3lPN0tqc1NYRVJvS3VtS2xZ?= =?utf-8?B?NGs5aXo4OW1BTmxrK05mb3plam9DMzFhN3VwTTFzS0dwcFRpRWEzdHBHWjJH?= =?utf-8?B?NTU1ZTIxb21IOENuQWZkNlRuN1F2d25Tbk02QnRvbzdVR2F2UjV3Slh3TVYx?= =?utf-8?B?NE5QRThuL3FkVDF3UlNycE9iUnZaMWNaa0xFeU91eXFLV0VRT3ozUmFweXB5?= =?utf-8?B?OGcrRk9KdzlQejJ3dFdqc25SQUx1akVob3U3TmdCR1prWGFHWWt1N2wvTS8y?= =?utf-8?B?anlRa2V4bS8vT0RGenFVOUhnaWJTeEEybldCQnlGWUhXMkJBN0hncEYvbFhH?= =?utf-8?B?a3I3WW1GMzVZR3o3YW1Wd0MxS0M0amNKYjVmTnNMN0IvVWsrY1JhVTRzT2Z1?= =?utf-8?B?R2FpdVhUVDBGMkhDUVBZOTEzN0VpaGpEVlhGSlZqZGpWVDR2bjlkZFI1ZVlj?= =?utf-8?B?OUtSQVlCTU9oeVNGRDNrZnVjZ04rcjNxRXF3UFF1Qk9NdDJKMDZ4eW1DRmNm?= =?utf-8?B?RXMzVzNXVi9XdmE2RmI5Nzl1T0FVc1cybEZiYmw5QlBHTFllQmFLZjBrRmIy?= =?utf-8?B?azh5WW5hV1pneVcvUE5YL21LcVB3VEVWQUwzTkR4d0FjbUZhQzJtKzNNelUw?= =?utf-8?B?eG1Sb3lPeUsxUXN3U05TaHplcmJvQUVFbE5XQXFCY1NwNkpxdjZhSDJ6dFUx?= =?utf-8?B?d096SU1ja096U094TnZldkprQ2tXa1p2SEdHdUNiZG8rSzJrZ0VHVlJYU21B?= =?utf-8?B?OHpXcnRBcUFFTkpHd1kwMmFwdGlWRldPbXRmSFpGR2dRT29WdW9mbEtJWUI0?= =?utf-8?B?S2RKQ2JTa2pxUWtXVHdpODdqaHdBS1FDYm5DT3hib2tpQ2VqOHBpZmplUXZM?= =?utf-8?B?MEErSExaZ0VLdTNjTCtJYmZOL0JBWVh3SWdTZE1iOVY4YWhNbjBoS0JJTW1T?= =?utf-8?B?T1NHcTQzeG13L3dpdng4UkZ2dDdCRlJNQnVyUHcrVFV2VjYzeURZZkJleCs5?= =?utf-8?B?TjhUMlIyRWQwbVIzUWJCbzVYNnZxTWt1ZWVSL1B0cTZIa1lvUkpDYUVDOE5a?= =?utf-8?B?TXJJWkRaVzh0R280Vks3OFMva2xiT0xCdjJudDl6L3A4b3RNbjZIUVJSWEpq?= =?utf-8?B?aDh0SWpCQTVadFNDRlFIQ3hmNnRSQllWN0h1Y2pKNXR6NzNvTUVjSlBzakRO?= =?utf-8?B?R2c9PQ==?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: f685d535-b702-4696-76e6-08dcf9871102 X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9251.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2024 08:36:08.2679 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: JV/sNlW0gJLaGObf1ysfPyoRsvvuioBFOXx5pQhdrAWXj4rkTRggjTd+sSB82qRgE6SPn6yC8Avy0JgSmbg2zg+20zUDsw9i6zX2/vcWIDc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB7199 Content-Type: text/plain; charset="utf-8" From: Ciprian Marian Costea Add the NXP S32G RTC driver as maintained so further patches on this driver can be reviewed under this architecture. Signed-off-by: Ciprian Marian Costea --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7bfef98226d9..991a9df6819d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2763,8 +2763,10 @@ R: Ghennadi Procopciuc L: NXP S32 Linux Team L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: Documentation/devicetree/bindings/rtc/nxp,s32g-rtc.yaml F: arch/arm64/boot/dts/freescale/s32g*.dts* F: drivers/pinctrl/nxp/ +F: drivers/rtc/rtc-s32g.c =20 ARM/Orion SoC/Technologic Systems TS-78xx platform support M: Alexander Clouter --=20 2.45.2