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charset="utf-8" Add ref clock for i.MX95 PCIe here, when the internal PLL is used as PCIe reference clock. Signed-off-by: Richard Zhu Reviewed-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95.dtsi | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts= /freescale/imx95.dtsi index 03661e76550f..5cb504b5f851 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -1473,6 +1473,14 @@ smmu: iommu@490d0000 { }; }; =20 + hsio_blk_ctl: syscon@4c0100c0 { + compatible =3D "nxp,imx95-hsio-blk-ctl", "syscon"; + reg =3D <0x0 0x4c0100c0 0x0 0x4>; + #clock-cells =3D <1>; + clocks =3D <&dummy>; + power-domains =3D <&scmi_devpd IMX95_PD_HSIO_TOP>; + }; + pcie0: pcie@4c300000 { compatible =3D "fsl,imx95-pcie"; reg =3D <0 0x4c300000 0 0x10000>, @@ -1500,8 +1508,9 @@ pcie0: pcie@4c300000 { clocks =3D <&scmi_clk IMX95_CLK_HSIO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; - clock-names =3D "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>; + clock-names =3D "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; assigned-clocks =3D<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; @@ -1528,8 +1537,9 @@ pcie0_ep: pcie-ep@4c300000 { clocks =3D <&scmi_clk IMX95_CLK_HSIO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; - clock-names =3D "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>; + clock-names =3D "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; assigned-clocks =3D<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; --=20 2.37.1