From nobody Mon Nov 25 02:57:36 2024 Received: from thales.epochal.quest (thales.epochal.quest [51.222.15.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F62A1531F2; Thu, 31 Oct 2024 07:03:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=51.222.15.28 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730358217; cv=none; b=J6LjLT5P/o/WykZomBiNX8Q2PXKelnrlIOICCwVjZKawXbrRBkbugcV7CO0S1LhigZCyI3SmputKET9APwnIyHQTmvUI16cRClhOk8fciN6OxQazTLVEFSFdkR3t1JkbEpp27OYKDJwZ7C0E86oUkPUZUkDhS6bZuWI9Qbj5JXY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730358217; c=relaxed/simple; bh=GAI+JxmxQAyxNiN5ndHrGW83jif5+/YkLkstTry27TU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=k/pX8+XbfkXB8Px0arFmOPZzFyk1Pfkt4XkCON8410SbiI1XGBciIozDYp4IFylbR1UHxmVUFvLobitpwFXCyQXDY7kWhLZ97ApbTxlchCb9EhjFf++9AZ2rcXKY5Kk65bj1AZdy3t/uSGWm5Vfe3f6IgQm7VHukUELFxiDAlPY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=epochal.quest; spf=pass smtp.mailfrom=epochal.quest; dkim=pass (2048-bit key) header.d=epochal.quest header.i=@epochal.quest header.b=YtMGcXQ1; arc=none smtp.client-ip=51.222.15.28 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=epochal.quest Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=epochal.quest Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=epochal.quest header.i=@epochal.quest header.b="YtMGcXQ1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=epochal.quest; s=default; t=1730358209; bh=GAI+JxmxQAyxNiN5ndHrGW83jif5+/YkLkstTry27TU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YtMGcXQ1SID1v4pgdcEhkufRJU5/wJrIL+RPeDknvJHDNbNSCg10hAmPea+B/COhW hNTRGGOCwQlISoewvbOqC5k7zQoOYNM7Xyc2PxoaKo7eDa6yNnZpoMX5iBTvUmFJHW WWws924uIjCzjCdc/8NdWnOwcMcCRtg92jjtPYpqlgBXmor3uvD1Shzs0egMApqFQi fJ/KMAM0h3Jw36XHCAOlD7HUWMuGiVD88CbsyXyC+jwwpsMRdk6e47Ls17qhL6u2zQ S/5ldj9z9iX05LrBJfrBfolRrZwRUFKC3k0ur650DmGIzHn7OdDI75k/7SR+XA/Qrr l/9NYcMCxWE6g== X-Virus-Scanned: by epochal.quest From: Cody Eksal To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Greg Kroah-Hartman , Kishon Vijay Abraham I , Maxime Ripard , Michael Turquette , Nishanth Menon , "Rafael J. Wysocki" , Stephen Boyd , Vinod Koul , Viresh Kumar , Viresh Kumar , Yangtao Li , Parthiban , Andre Przywara , Cody Eksal , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 13/13] arm64: dts: allwinner: a100: Add CPU Operating Performance Points table Date: Thu, 31 Oct 2024 04:02:26 -0300 Message-ID: <20241031070232.1793078-14-masterr3c0rd@epochal.quest> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241031070232.1793078-1-masterr3c0rd@epochal.quest> References: <20241031070232.1793078-1-masterr3c0rd@epochal.quest> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Shuosheng Huang Add an Operating Performance Points table for the CPU cores to enable Dynamic Voltage & Frequency Scaling on the A100. Signed-off-by: Shuosheng Huang [masterr3c0rd@epochal.quest: fix typos in -cpu-opp, use compatible] Signed-off-by: Cody Eksal --- Changes in V2: - Rename cpu-opp-table to opp-table-cpu - Use single cell version of opp-microvolt-speedX .../allwinner/sun50i-a100-allwinner-perf1.dts | 5 ++ .../dts/allwinner/sun50i-a100-cpu-opp.dtsi | 90 +++++++++++++++++++ .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 8 ++ 3 files changed, 103 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts = b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts index d418fc272b3c..1fb629df9f1d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts @@ -6,6 +6,7 @@ /dts-v1/; =20 #include "sun50i-a100.dtsi" +#include "sun50i-a100-cpu-opp.dtsi" =20 #include =20 @@ -68,6 +69,10 @@ &usb_otg { status =3D "okay"; }; =20 +&cpu0 { + cpu-supply =3D <®_dcdc2>; +}; + &pio { vcc-pb-supply =3D <®_dcdc1>; vcc-pc-supply =3D <®_eldo1>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi b/arch/= arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi new file mode 100644 index 000000000000..c6a2efa037dc --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2020 Yangtao Li +// Copyright (c) 2020 ShuoSheng Huang + +/ { + cpu_opp_table: opp-table-cpu { + compatible =3D "allwinner,sun50i-a100-operating-points"; + nvmem-cells =3D <&cpu_speed_grade>; + opp-shared; + + opp-408000000 { + clock-latency-ns =3D <244144>; /* 8 32k periods */ + opp-hz =3D /bits/ 64 <408000000>; + + opp-microvolt-speed0 =3D <900000>; + opp-microvolt-speed1 =3D <900000>; + opp-microvolt-speed2 =3D <900000>; + }; + + opp-600000000 { + clock-latency-ns =3D <244144>; /* 8 32k periods */ + opp-hz =3D /bits/ 64 <600000000>; + + opp-microvolt-speed0 =3D <900000>; + opp-microvolt-speed1 =3D <900000>; + opp-microvolt-speed2 =3D <900000>; + }; + + opp-816000000 { + clock-latency-ns =3D <244144>; /* 8 32k periods */ + opp-hz =3D /bits/ 64 <816000000>; + + opp-microvolt-speed0 =3D <940000>; + opp-microvolt-speed1 =3D <900000>; + opp-microvolt-speed2 =3D <900000>; + }; + + opp-1080000000 { + clock-latency-ns =3D <244144>; /* 8 32k periods */ + opp-hz =3D /bits/ 64 <1080000000>; + + opp-microvolt-speed0 =3D <1020000>; + opp-microvolt-speed1 =3D <980000>; + opp-microvolt-speed2 =3D <950000>; + }; + + opp-1200000000 { + clock-latency-ns =3D <244144>; /* 8 32k periods */ + opp-hz =3D /bits/ 64 <1200000000>; + + opp-microvolt-speed0 =3D <1100000>; + opp-microvolt-speed1 =3D <1020000>; + opp-microvolt-speed2 =3D <1000000>; + }; + + opp-1320000000 { + clock-latency-ns =3D <244144>; /* 8 32k periods */ + opp-hz =3D /bits/ 64 <1320000000>; + + opp-microvolt-speed0 =3D <1160000>; + opp-microvolt-speed1 =3D <1060000>; + opp-microvolt-speed2 =3D <1030000>; + }; + + opp-1464000000 { + clock-latency-ns =3D <244144>; /* 8 32k periods */ + opp-hz =3D /bits/ 64 <1464000000>; + + opp-microvolt-speed0 =3D <1180000>; + opp-microvolt-speed1 =3D <1180000>; + opp-microvolt-speed2 =3D <1130000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 =3D <&cpu_opp_table>; +}; + +&cpu1 { + operating-points-v2 =3D <&cpu_opp_table>; +}; + +&cpu2 { + operating-points-v2 =3D <&cpu_opp_table>; +}; + +&cpu3 { + operating-points-v2 =3D <&cpu_opp_table>; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun50i-a100.dtsi index 29ac7716c7a5..6a76858b654a 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi @@ -23,6 +23,7 @@ cpu0: cpu@0 { device_type =3D "cpu"; reg =3D <0x0>; enable-method =3D "psci"; + clocks =3D <&ccu CLK_CPUX>; }; =20 cpu1: cpu@1 { @@ -30,6 +31,7 @@ cpu1: cpu@1 { device_type =3D "cpu"; reg =3D <0x1>; enable-method =3D "psci"; + clocks =3D <&ccu CLK_CPUX>; }; =20 cpu2: cpu@2 { @@ -37,6 +39,7 @@ cpu2: cpu@2 { device_type =3D "cpu"; reg =3D <0x2>; enable-method =3D "psci"; + clocks =3D <&ccu CLK_CPUX>; }; =20 cpu3: cpu@3 { @@ -44,6 +47,7 @@ cpu3: cpu@3 { device_type =3D "cpu"; reg =3D <0x3>; enable-method =3D "psci"; + clocks =3D <&ccu CLK_CPUX>; }; }; =20 @@ -142,6 +146,10 @@ efuse@3006000 { ths_calibration: calib@14 { reg =3D <0x14 8>; }; + + cpu_speed_grade: cpu-speed-grade@1c { + reg =3D <0x1c 0x2>; + }; }; =20 watchdog@30090a0 { --=20 2.47.0