From nobody Mon Nov 25 02:55:48 2024 Received: from thales.epochal.quest (thales.epochal.quest [51.222.15.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1783D150981; Thu, 31 Oct 2024 07:03:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=51.222.15.28 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730358217; cv=none; b=IRFXagBrweSulfcFTylsgh4wXCUsalCzXedkhVi5y3kaP6cK/ikcf0qD9HXqsPSHEg7Nf09KbZ85MymduRqjsij/9nffxhql2TyB3HwhhY80tzVV2ddFyc2Jy1u6iYI8y7wTVbKGOwSf+xGOP2SiYIpnCheRKrZdxjtlKNwVopA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730358217; c=relaxed/simple; bh=uG2apc/l46v55IsDCKvsKsBsQ3G+4vM+sV5vj2eVN7Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=a+jo5oO6VD7FWUX3sj994VWkmiK/mdM2VZHS1D7LM/8fqrQN49eLthXhRisepnbbdgdEd/5nZocXuzm7QSzFrw1/09u/n7YWAtc+JwqDUqDPDITdq8YK4mhF4ThHHZbsd2uOkFLzWFZOmZs76FiXoEUtVty5v6NVnioD3/7OY0A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=epochal.quest; spf=pass smtp.mailfrom=epochal.quest; dkim=pass (2048-bit key) header.d=epochal.quest header.i=@epochal.quest header.b=fm+gozSy; arc=none smtp.client-ip=51.222.15.28 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=epochal.quest Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=epochal.quest Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=epochal.quest header.i=@epochal.quest header.b="fm+gozSy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=epochal.quest; s=default; t=1730358205; bh=uG2apc/l46v55IsDCKvsKsBsQ3G+4vM+sV5vj2eVN7Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fm+gozSyaRIJon1mAHV2EYtzITXTjiBBwxHmNkcZGiuhJiQiyWT4zD90JbMpUDE0d S04ooXRzJo52QdbCtL62mgyXMJJXkSE9VzTG4ZGtaOreeZWv8vV0B/ArJcOJjl9/76 RTHrGnMksj+1bEtALdhPNhUEMYcRiAqdQoQi5LQXC3BTMXCAfPjajHgsABMMfVtcMP 85d7BJ3e+Fx9MJpeIecwdabc6G/ejJz0UJN0xMhGgAn1xHqkMFJTQb1XyUNsg9xumy kRonWaNviblBc7rHjJzmlGidcT21mG2Tz0GdkBEqqy6WxXwbEd6S/KUzYBPj9vjGu5 GOJVi+JvbMg6w== X-Virus-Scanned: by epochal.quest From: Cody Eksal To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Greg Kroah-Hartman , Kishon Vijay Abraham I , Maxime Ripard , Michael Turquette , Nishanth Menon , "Rafael J. Wysocki" , Stephen Boyd , Vinod Koul , Viresh Kumar , Viresh Kumar , Yangtao Li , Parthiban , Andre Przywara , Cody Eksal , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 09/13] arm64: allwinner: a100: Add MMC related nodes Date: Thu, 31 Oct 2024 04:02:22 -0300 Message-ID: <20241031070232.1793078-10-masterr3c0rd@epochal.quest> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241031070232.1793078-1-masterr3c0rd@epochal.quest> References: <20241031070232.1793078-1-masterr3c0rd@epochal.quest> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yangtao Li The A100 has 3 MMC controllers, one of them being especially targeted to eMMC. Let's add nodes on dts. Signed-off-by: Yangtao Li Reviewed-by: Andre Przywara Signed-off-by: Cody Eksal --- .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun50i-a100.dtsi index f6162a107641..29ac7716c7a5 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi @@ -169,12 +169,83 @@ pio: pinctrl@300b000 { interrupt-controller; #interrupt-cells =3D <3>; =20 + mmc0_pins: mmc0-pins { + pins =3D "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; + function =3D "mmc0"; + drive-strength =3D <30>; + bias-pull-up; + }; + + /omit-if-no-ref/ + mmc1_pins: mmc1-pins { + pins =3D "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; + function =3D "mmc1"; + drive-strength =3D <30>; + bias-pull-up; + }; + + mmc2_pins: mmc2-pins { + pins =3D "PC0", "PC1", "PC5", "PC6", + "PC8", "PC9", "PC10", "PC11", + "PC13", "PC14", "PC15", "PC16"; + function =3D "mmc2"; + drive-strength =3D <30>; + bias-pull-up; + }; + uart0_pb_pins: uart0-pb-pins { pins =3D "PB9", "PB10"; function =3D "uart0"; }; }; =20 + mmc0: mmc@4020000 { + compatible =3D "allwinner,sun50i-a100-mmc"; + reg =3D <0x04020000 0x1000>; + clocks =3D <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC0>; + reset-names =3D "ahb"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc0_pins>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mmc1: mmc@4021000 { + compatible =3D "allwinner,sun50i-a100-mmc"; + reg =3D <0x04021000 0x1000>; + clocks =3D <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC1>; + reset-names =3D "ahb"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc1_pins>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mmc2: mmc@4022000 { + compatible =3D "allwinner,sun50i-a100-emmc"; + reg =3D <0x04022000 0x1000>; + clocks =3D <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC2>; + reset-names =3D "ahb"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc2_pins>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + uart0: serial@5000000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x05000000 0x400>; --=20 2.47.0