From nobody Mon Nov 25 03:30:49 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67FC81BBBF8; Thu, 31 Oct 2024 15:53:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389992; cv=none; b=XAYWHLDXOIKnecoKzQkGYE1og+GlsWT+wef5pErwn5o9p5bfC32Bmbk6siZDZPJVCj7XuKvt7HDRetXIhw+KlJtg3haISVb9lnzv0zQXGdBOvB+byGGbOvAnT33FvVfRv+2W2gCET7B/QLd1Zhx8F/Mtjjkt51zluq89OmTbsrI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389992; c=relaxed/simple; bh=dpx86UKWHmQob1x1Y9dZoFYGDcYgFQTexwF3Pl4RVJg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=H/IHYPXW0HUld6vq10Kf6013vn2oMYpLoQo6zpfT93G/14iKjLlCJmDqk4A+Bd2ayxiH8AtWXHdKZWNxGk8kg83eV0iOwtSpNfpCN30n8K2+29BW9Ps6JS+f8lmRLRW2I4+lF9rtP7pWprVIBQXYnEr/rGZwKssKmY7y2QPLEOI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=AfwfZfKV; arc=none smtp.client-ip=217.70.183.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="AfwfZfKV" Received: by mail.gandi.net (Postfix) with ESMTPSA id CEAAE1C0015; Thu, 31 Oct 2024 15:53:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730389984; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vBvALQBz6nzlJoEhBr0vnmX8yOjbMQW6G7cmJmWOtDo=; b=AfwfZfKV+IE3wQL2HZvOVFbJNo8j3ZNamNUpRWTmIXZNvsFNDfG06H6x4gbSOPKq9nJrLi roNGgwJegeryDpY82DprD9sJc2jYYQs6ONSVdRCuj58qQwHJlLaI15fo3x+32bymftoQgP pY/kqaAooFobedTDO2LVm9aHwUMZRmfB0HBy8tTOCqfgXpkaaaDoSDfJKUGKHh+u9qCcWQ oo3dZXfA37XDBjB42Vp1YNW/SWqWjML3qAoJqmZBRlcQxpk5IsFUu4nPDV3Mx3Ct16vdmT zJ4sCAwYcBEo9RIDb4lq783+Ghz04Aw1VeusISASxIKkncGCsEJD7cF8KCoKdg== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Thu, 31 Oct 2024 16:53:02 +0100 Subject: [PATCH 12/13] MIPS: mobileye: eyeq5: use OLB as provider for fixed factor clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241031-mbly-clk-v1-12-89d8b28e3006@bootlin.com> References: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> In-Reply-To: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Change the structure of the clock tree: rather than individual devicetree nodes registering each fixed factor clock derived from OLB PLLs, have the OLB node provide the necessary clocks. Remove eyeq5-clocks.dtsi and move the three remaining "fixed-clock"s to the main eyeq5.dtsi file. Signed-off-by: Th=C3=A9o Lebrun --- arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi | 270 ----------------------= ---- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 30 ++- 2 files changed, 24 insertions(+), 276 deletions(-) diff --git a/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi b/arch/mips/boot= /dts/mobileye/eyeq5-clocks.dtsi deleted file mode 100644 index 17a342cc744e57dc1f21262abdbfa97d4e4d58f3..000000000000000000000000000= 0000000000000 --- a/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi +++ /dev/null @@ -1,270 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Copyright 2023 Mobileye Vision Technologies Ltd. - */ - -#include - -/ { - /* Fixed clock */ - xtal: xtal { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <30000000>; - }; - -/* PLL_CPU derivatives */ - occ_cpu: occ-cpu { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_CPU>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - si_css0_ref_clk: si-css0-ref-clk { /* gate ClkRstGen_si_css0_ref */ - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_cpu>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - cpc_clk: cpc-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&si_css0_ref_clk>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - core0_clk: core0-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&si_css0_ref_clk>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - core1_clk: core1-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&si_css0_ref_clk>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - core2_clk: core2-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&si_css0_ref_clk>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - core3_clk: core3-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&si_css0_ref_clk>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - cm_clk: cm-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&si_css0_ref_clk>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - mem_clk: mem-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&si_css0_ref_clk>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - occ_isram: occ-isram { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_CPU>; - #clock-cells =3D <0>; - clock-div =3D <2>; - clock-mult =3D <1>; - }; - isram_clk: isram-clk { /* gate ClkRstGen_isram */ - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_isram>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - occ_dbu: occ-dbu { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_CPU>; - #clock-cells =3D <0>; - clock-div =3D <10>; - clock-mult =3D <1>; - }; - si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */ - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_dbu>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; -/* PLL_VDI derivatives */ - occ_vdi: occ-vdi { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_VDI>; - #clock-cells =3D <0>; - clock-div =3D <2>; - clock-mult =3D <1>; - }; - vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */ - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_vdi>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - occ_can_ser: occ-can-ser { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_VDI>; - #clock-cells =3D <0>; - clock-div =3D <16>; - clock-mult =3D <1>; - }; - can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */ - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_can_ser>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - i2c_ser_clk: i2c-ser-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_VDI>; - #clock-cells =3D <0>; - clock-div =3D <20>; - clock-mult =3D <1>; - }; -/* PLL_PER derivatives */ - occ_periph: occ-periph { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_PER>; - #clock-cells =3D <0>; - clock-div =3D <16>; - clock-mult =3D <1>; - }; - periph_clk: periph-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_periph>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - can_clk: can-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_periph>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - spi_clk: spi-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_periph>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - uart_clk: uart-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_periph>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - i2c_clk: i2c-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_periph>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - clock-output-names =3D "i2c_clk"; - }; - timer_clk: timer-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_periph>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - clock-output-names =3D "timer_clk"; - }; - gpio_clk: gpio-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_periph>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - clock-output-names =3D "gpio_clk"; - }; - emmc_sys_clk: emmc-sys-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_PER>; - #clock-cells =3D <0>; - clock-div =3D <10>; - clock-mult =3D <1>; - clock-output-names =3D "emmc_sys_clk"; - }; - ccf_ctrl_clk: ccf-ctrl-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_PER>; - #clock-cells =3D <0>; - clock-div =3D <4>; - clock-mult =3D <1>; - clock-output-names =3D "ccf_ctrl_clk"; - }; - occ_mjpeg_core: occ-mjpeg-core { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_PER>; - #clock-cells =3D <0>; - clock-div =3D <2>; - clock-mult =3D <1>; - clock-output-names =3D "occ_mjpeg_core"; - }; - hsm_clk: hsm-clk { /* gate ClkRstGen_hsm */ - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_mjpeg_core>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - clock-output-names =3D "hsm_clk"; - }; - mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */ - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_mjpeg_core>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - clock-output-names =3D "mjpeg_core_clk"; - }; - fcmu_a_clk: fcmu-a-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_PER>; - #clock-cells =3D <0>; - clock-div =3D <20>; - clock-mult =3D <1>; - clock-output-names =3D "fcmu_a_clk"; - }; - occ_pci_sys: occ-pci-sys { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_PER>; - #clock-cells =3D <0>; - clock-div =3D <8>; - clock-mult =3D <1>; - clock-output-names =3D "occ_pci_sys"; - }; - pclk: pclk { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <250000000>; /* 250MHz */ - }; - tsu_clk: tsu-clk { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <125000000>; /* 125MHz */ - }; -}; diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mo= bileye/eyeq5.dtsi index 0708771c193d064fa56be2c7f6115672b5c24d8d..5d73e8320b8efc1b4f68923482b= f188c4345f1cb 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -5,7 +5,7 @@ =20 #include =20 -#include "eyeq5-clocks.dtsi" +#include =20 / { #address-cells =3D <2>; @@ -17,7 +17,7 @@ cpu@0 { device_type =3D "cpu"; compatible =3D "img,i6500"; reg =3D <0>; - clocks =3D <&core0_clk>; + clocks =3D <&olb EQ5C_CPU_CORE0>; }; }; =20 @@ -64,6 +64,24 @@ cpu_intc: interrupt-controller { #interrupt-cells =3D <1>; }; =20 + xtal: xtal { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <30000000>; + }; + + pclk: pclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <250000000>; /* 250MHz */ + }; + + tsu_clk: tsu-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; /* 125MHz */ + }; + soc: soc { #address-cells =3D <2>; #size-cells =3D <2>; @@ -76,7 +94,7 @@ uart0: serial@800000 { reg-io-width =3D <4>; interrupt-parent =3D <&gic>; interrupts =3D ; - clocks =3D <&uart_clk>, <&occ_periph>; + clocks =3D <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>; clock-names =3D "uartclk", "apb_pclk"; resets =3D <&olb 0 10>; pinctrl-names =3D "default"; @@ -89,7 +107,7 @@ uart1: serial@900000 { reg-io-width =3D <4>; interrupt-parent =3D <&gic>; interrupts =3D ; - clocks =3D <&uart_clk>, <&occ_periph>; + clocks =3D <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>; clock-names =3D "uartclk", "apb_pclk"; resets =3D <&olb 0 11>; pinctrl-names =3D "default"; @@ -102,7 +120,7 @@ uart2: serial@a00000 { reg-io-width =3D <4>; interrupt-parent =3D <&gic>; interrupts =3D ; - clocks =3D <&uart_clk>, <&occ_periph>; + clocks =3D <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>; clock-names =3D "uartclk", "apb_pclk"; resets =3D <&olb 0 12>; pinctrl-names =3D "default"; @@ -135,7 +153,7 @@ gic: interrupt-controller@140000 { timer { compatible =3D "mti,gic-timer"; interrupts =3D ; - clocks =3D <&core0_clk>; + clocks =3D <&olb EQ5C_CPU_CORE0>; }; }; }; --=20 2.47.0