From nobody Mon Nov 25 00:26:34 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E09A16BE1C; Thu, 31 Oct 2024 15:53:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389986; cv=none; b=E6n1ml74cE/FAGQO3WQcl/HTMVeSgNH5p+vuZP0LzAWpYDr7JLmfkV4zbt8SG1NMdsk2gBb5e/O5Ak/6Cs84WiUOzJiVR38X8T2E2f0IHUdPyS3RbAvG8F5+ZZ5QZhImJRBYrOWhuPSBCGsNVyTguIVDT6zt0tt9DniX7hkyNvI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389986; c=relaxed/simple; bh=UQOZleKN0I47pFewlLdn4eNH5eyQYywz80j7YTDBrs4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=okn39Kp4MAwHzrgSXlQLjwx/a6ibIvD/3alGZnIbP9Ku0gVsiBnGl1M1gtbhkDBQyHFXijFBA/HQQ/+2Rq7bfQdQDAv+gJhdaBhhNQsbB1+JEBRzpmHCozfRGhqc9FxGPTOWQsLx3YIyBGJYM4XMUj26SWSSoXRsALAm8Sq4Um8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=LRc8xeRq; arc=none smtp.client-ip=217.70.183.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="LRc8xeRq" Received: by mail.gandi.net (Postfix) with ESMTPSA id 0B7891C0002; Thu, 31 Oct 2024 15:52:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730389976; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=w3qxyX3xIUtfm2MBeQ9m7antb8YArMnqEhCwuO3QGyQ=; b=LRc8xeRqGEg4/VRLFYNNMBGnGUO12SjJXBqznuAmBTJ1t5N0eIZawgubIXOBVGgnleOmHs gzYnhs0GJIDhhuUXEXOIOy0cg/SHPbBgiMk9W/oNlWwzvx21vPwB1Nm8kzpQ88Qs3ZiSHW kt57tM3as3Sw7gaQLVLZCYNjjm3A8HSUECweQnL3il96x5kABOeU1iEqiZU8/e1c6FB0+8 z7QbjD7VoAKhDrWSh9494Nk07QLKLnKLjV1MfL8E5veLtAcERfkoXwunU4jRw1P39e+T4h M4l5FUozOvkcXkGQEUWdhmkW95BhErGUZJRyyD+EcnqFS2tjJlgp97tGlcucKg== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Thu, 31 Oct 2024 16:52:51 +0100 Subject: [PATCH 01/13] dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241031-mbly-clk-v1-1-89d8b28e3006@bootlin.com> References: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> In-Reply-To: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Some compatibles expose a single clock. For those, we used to let them using `#clock-cells =3D <0>` (ie <&olb> reference rather than <&olb 0>). Switch away from that: enforce a cell for all compatibles. This is more straight forward, and avoids devicetree changes whenever a compatible goes from exposing a single clock to multiple ones. Side benefit: dt-bindings is simpler. Signed-off-by: Th=C3=A9o Lebrun --- .../bindings/soc/mobileye/mobileye,eyeq5-olb.yaml | 24 +-----------------= ---- 1 file changed, 1 insertion(+), 23 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-= olb.yaml b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-ol= b.yaml index f7e606d45ebcfc46ffe076e23a2ed514bfff9b8f..6d11472ba5a704d5d20f43776e5= 867f507a39242 100644 --- a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml +++ b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml @@ -41,9 +41,7 @@ properties: enum: [ 1, 2 ] =20 '#clock-cells': - description: - Cell is clock index. Optional if compatible has a single clock. - enum: [ 0, 1 ] + const: 1 =20 clocks: maxItems: 1 @@ -312,26 +310,6 @@ allOf: properties: '#reset-cells': false =20 - # Compatibles exposing a single clock. - - if: - properties: - compatible: - contains: - enum: - - mobileye,eyeq6h-central-olb - - mobileye,eyeq6h-east-olb - - mobileye,eyeq6h-west-olb - - mobileye,eyeq6h-ddr0-olb - - mobileye,eyeq6h-ddr1-olb - then: - properties: - '#clock-cells': - const: 0 - else: - properties: - '#clock-cells': - const: 1 - # Only EyeQ5 has pinctrl in OLB. - if: not: --=20 2.47.0 From nobody Mon Nov 25 00:26:34 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56D41136664; Thu, 31 Oct 2024 15:53:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389987; cv=none; b=usz8g5n/8oC/gyFEXzjPiltqEdiZLfDWKkIuLym4XpQWAb+5mwx2HXPGIFTt1ERsOK4Kd57gQ4Qdjcg/8Wxx71KC+JGoH+5014/2qcIaUk6ye3zRLT7Y4n+JeJ9Ooxco2fhDmoQ5ssyRRT7HW89aKmZCOPVhHlUlcZu0amg6rNU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389987; c=relaxed/simple; bh=NQyYaIjAovNh/+tjBANCN0ydFdN7FSPnUoW0X/BqvLg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=f1ybWOkm5GV/Sz0ZqSQ/HcATsALkTSTzO69SFkyN8Mr9RLBVaV92zsUrIwzQFR6UDsz2Cv/kiXAixgL+qA3lB1tQcUFd6OLNN17t4SRlLok9VlT41aW/mjEkh9O+ui+aMxNterMc/zEppXLjKLxZI1eNfpmTDAVakXqDC8Y6cuM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=JfwVkLBU; arc=none smtp.client-ip=217.70.183.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="JfwVkLBU" Received: by mail.gandi.net (Postfix) with ESMTPSA id AC90E1C0004; Thu, 31 Oct 2024 15:52:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730389977; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oJJl+SCCXVek7yuMPvftSNZQjg3UbRGAzz3320vEENM=; b=JfwVkLBUs+QGumSJjM8FQxLeQghqyBnmEAbsMdftmAQJ+/RyCITPQfJO4g/R/Q+lDTuBU/ 2Gi0r3sIoQyfa01HzFBePh5CZIuoSPgK3S50Cuv0zZkOR2jffcOLxwMKSNs8vg+Pv546aZ PoPM8YdwYX9TbWzQTSyIWXv36++nnAfkbLVUOowsrTQ4iUEO+Mz74NwXZukYC2AeOT4NyS E/sV3CedJsRmwzILc+noRWprud65IFtou+74CxR8cbrpoH/YZ6XIwN+OdiHUBAfs8BEChu PfLgLw++DCTExsceRYLCJNQLiV3j8cGDyeWfSOfx/ACyilslT/p2EoCg5QJgFA== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Thu, 31 Oct 2024 16:52:52 +0100 Subject: [PATCH 02/13] dt-bindings: clock: eyeq: add Mobileye EyeQ5 core clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241031-mbly-clk-v1-2-89d8b28e3006@bootlin.com> References: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> In-Reply-To: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Add #defines for Mobileye EyeQ5 core 0 thru 3 inclusive. Internally, those derive from EQ5C_PLL_CPU. Signed-off-by: Th=C3=A9o Lebrun --- include/dt-bindings/clock/mobileye,eyeq5-clk.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bi= ndings/clock/mobileye,eyeq5-clk.h index b433c1772c28fae818b3a6ba428d1f89000f9206..359f7cceaadb368998db7143445= 95f0449963536 100644 --- a/include/dt-bindings/clock/mobileye,eyeq5-clk.h +++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h @@ -19,6 +19,12 @@ =20 #define EQ5C_DIV_OSPI 10 =20 +/* EQ5C_PLL_CPU children */ +#define EQ5C_CPU_CORE0 11 +#define EQ5C_CPU_CORE1 12 +#define EQ5C_CPU_CORE2 13 +#define EQ5C_CPU_CORE3 14 + #define EQ6LC_PLL_DDR 0 #define EQ6LC_PLL_CPU 1 #define EQ6LC_PLL_PER 2 --=20 2.47.0 From nobody Mon Nov 25 00:26:34 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69D5719E99C; Thu, 31 Oct 2024 15:53:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389988; cv=none; b=QgWNbbHvTlTSRdQwyHbeQjXlOrp9RiBM3m1xPia7STMqEhwFR1gdU3lBoSJHsWThFA8NUTiPrn2nd7NA5D3a5tGX2zXY13133DM9l3H3owYUAWhPKZvWDHDLo/sVjuTGSb+szO3P1cxvOb9f5Y//0ZMOOGCFYoLFDUkMHySf4oo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389988; c=relaxed/simple; bh=PkYmJSqGkFyq+J9VjbWR4RGNmdoD4abq2oGTEVhGWeY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UfHJeBTc1lWLG72hAWNmbgkZJ7PX46BNk27g0vFZb8JkUbwdhc3oWfkkwJbSKPilTH0/7+VHXmkSahqtfE+6I+78FBHjuoCwS4O7gX4kNZ3vBAd0IRFimSiHIjQFmBSVj3tkq2cn3AYuFprx9Z4FXHFgTA7dlRHvXV3ATJgDZHE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=Vc9fnRgK; arc=none smtp.client-ip=217.70.183.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Vc9fnRgK" Received: by mail.gandi.net (Postfix) with ESMTPSA id 5E5ED1C0005; Thu, 31 Oct 2024 15:52:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730389978; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QBvTtImYlxXqwUMA99jcUs5VY9iyrwJHK1o1kNXV6w4=; b=Vc9fnRgKDS7EoIhinn4okK1ZTylvYIrkFznGWMCERKaQ7ttruauh7Fi4FElCXhsvcwevwj 6/VVWAkwkIEaH86CnrL890HEi2Pb/Fmt4EjRI87gihuXdJ/3RzBRXqO7p026yyi38TEJp9 lVLkbn/CWN0GXb2n3CMzaNqBm8Zb1yKeBaG7DdNop6zFynQ9dHInLtqt3D+I0fdGSUfQHM xlNU4u5KsatM/WFzM9hn/RFRIT5rdDeCij7Uo9r/VCgLM60JYyREIDuzo6Z+M9smy4zJCj QWkIFATE7eKzzHfX22d5x7PDiNeT0ecB8JhZ0YPN7wPVD9PkG10qZ308xitHsg== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Thu, 31 Oct 2024 16:52:53 +0100 Subject: [PATCH 03/13] dt-bindings: clock: eyeq: add Mobileye EyeQ5 peripheral clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241031-mbly-clk-v1-3-89d8b28e3006@bootlin.com> References: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> In-Reply-To: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Add #defines for Mobileye EyeQ5 slow-speed peripheral bus clock (OCC) and UART clock. Internally, those derive from EQ5C_PLL_PER. OCC is standard naming convention on this platform. Its exact meaning is unknown. Signed-off-by: Th=C3=A9o Lebrun --- include/dt-bindings/clock/mobileye,eyeq5-clk.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bi= ndings/clock/mobileye,eyeq5-clk.h index 359f7cceaadb368998db714344595f0449963536..7d9e700b5e59573c45919865d9c= 68a9e8cf6a9eb 100644 --- a/include/dt-bindings/clock/mobileye,eyeq5-clk.h +++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h @@ -25,6 +25,10 @@ #define EQ5C_CPU_CORE2 13 #define EQ5C_CPU_CORE3 14 =20 +/* EQ5C_PLL_PER children */ +#define EQ5C_PER_OCC 15 +#define EQ5C_PER_UART 16 + #define EQ6LC_PLL_DDR 0 #define EQ6LC_PLL_CPU 1 #define EQ6LC_PLL_PER 2 --=20 2.47.0 From nobody Mon Nov 25 00:26:34 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41C691A254F; Thu, 31 Oct 2024 15:53:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389988; cv=none; b=Np2IcRkabBOKpVZK6UFYDcqUHGe6lNT50YNCQxG139N/7WbcO0NQ0ZB17t4zh+/AvPzycVegedq1/FEiNoM0Vz41iB+XLwiRX84a0kB7pqLvJHz2ZKWHWjV/swy3xH/l+DSJKMM4UT0LGxKCnbl6mnAYhHX/KGbBy74TBsOifbw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389988; c=relaxed/simple; bh=TYPPcgAEVgmZNxDqH4msGR2AzYupIiZeXAnNVnKGLd0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bGe7beWEr/Rs/DMfiTRMVPqYnOKSxtD5qPwusBIoHvTBkbh/V48kM3LdX9/CRg26YGlRhcwxLTM2yM3F5ATh18eAl95O5OXzx9ZRRs6DNPkZAUmmdhsLCaL83XfMhIaVr9fHTHunyrXM40BBPgAR1eL9a58xTv9SZqpXFJVAves= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=VzskqY1x; arc=none smtp.client-ip=217.70.183.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="VzskqY1x" Received: by mail.gandi.net (Postfix) with ESMTPSA id 29DDA1C0006; Thu, 31 Oct 2024 15:52:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730389978; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YbogFrPuS1mbsrk3psEaApAX2/Cxw1n8kdmMlJcjLVk=; b=VzskqY1xDgxqfH7vk5a8oitglYo+yD/HFQkY/5KbgwrFfOKg16wsIk4hZFe3pXE22Uee+L Zwi8cjLZlhyGatNZ8B1oFtVar/znDbbu0sP9aE3hEj6+lVN8DJysStDmhe4kcqr99Bc502 LLWmcXA7upszRTfUB4zx0hU27jsaDQmyUjnbIE2nC4r0p4vUKcmEmxp5+RAxu1fOnsZkLD jdq9XjuntB1sRYHBGyN2UANhQeGoB4+HK3bdezYsCesgXbI856avhroYB9dRVLRObGFwvA 0iJzCZPA25fMgNvd0ONXXNsiqjNzHxrE51YgBBydskt00eRA0wp8u+IWKD7wRQ== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Thu, 31 Oct 2024 16:52:54 +0100 Subject: [PATCH 04/13] dt-bindings: clock: eyeq: add Mobileye EyeQ6H central clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241031-mbly-clk-v1-4-89d8b28e3006@bootlin.com> References: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> In-Reply-To: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Add clock indexes for EyeQ6H central OLB. Signed-off-by: Th=C3=A9o Lebrun --- include/dt-bindings/clock/mobileye,eyeq5-clk.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bi= ndings/clock/mobileye,eyeq5-clk.h index 7d9e700b5e59573c45919865d9c68a9e8cf6a9eb..2356bc52646df9cfeb93df8120e= b8f0bf80d97e9 100644 --- a/include/dt-bindings/clock/mobileye,eyeq5-clk.h +++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h @@ -34,6 +34,9 @@ #define EQ6LC_PLL_PER 2 #define EQ6LC_PLL_VDI 3 =20 +#define EQ6HC_CENTRAL_PLL_CPU 0 +#define EQ6HC_CENTRAL_CPU_OCC 1 + #define EQ6HC_SOUTH_PLL_VDI 0 #define EQ6HC_SOUTH_PLL_PCIE 1 #define EQ6HC_SOUTH_PLL_PER 2 --=20 2.47.0 From nobody Mon Nov 25 00:26:34 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41CC11A255C; Thu, 31 Oct 2024 15:53:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389988; cv=none; b=f4av9hzpuHvgaUXMNIUmiXhaTZK/5GGC/Xdn2TshAy/r0Wx1JHUqVn8c1nSSPuPPrUbxpkWYGG8vcLueF/YfnGbPscnmRKX1aWoiF0Ta43ebeiG2CKpIglx8FYAK2QHe9zddpSzbS+h/gDrFm/RT8fQGQZjQEhmXsWEA+UyckF8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389988; c=relaxed/simple; bh=6l0qZSHDsQnkRceIi1yCN9qKhJDbQDK/liFSP7R8KZU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=U2TrHnX0rrjlmG5MsCaToQQqJ6SzDO41qoxy0lNGjAezKv26k7Azo2epa9TA1YZbuVDJfQYPM+9GYOMd2tr7U9rkPnpc1vrdMCnEwgRdgMdoYMzgluvlG68zzEf3Tm3nmPyNkZwC7BvA1UwcmxBzRldRoYoYtd0cBPl60HAlhD0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=WYgN5rUC; arc=none smtp.client-ip=217.70.183.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="WYgN5rUC" Received: by mail.gandi.net (Postfix) with ESMTPSA id D05B41C000C; Thu, 31 Oct 2024 15:52:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730389979; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=duc7FXGhBJ2LaONO5SFmALxLdfb+2+axaT7TzFowjXs=; b=WYgN5rUCriEr7fSdHWBQAI/55MHYLnGXwMiSDtv+FgIc/WXQYQfyjYQgGt0Tdd41zGOS0/ X6xBDGngGefQItDFx23isoWJ4LSIHg1ZRw0mo2mom4s49XieiFExlpIMKf4IG1uAkSHpwE nYBFRBqMvbt321SgmO2fzS43MUg3gPv/RmTLEW/KP6mqRWHi5Xq+/y/0WxrwXmHw0YJD8n lOBTrxGg1Kb/8hfAPmlqwDKYs2Li4Nig4+8xHX60Zc3qr15kgO0tV6GdHQM1yoE/RwWPBc senhRJXpNcPBs1MjbXxFGGjWHsGbzNeSIogGJq6h1W9tHvY4fZcxKGVMxVRqZg== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Thu, 31 Oct 2024 16:52:55 +0100 Subject: [PATCH 05/13] dt-bindings: clock: eyeq: add Mobileye EyeQ6H west clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241031-mbly-clk-v1-5-89d8b28e3006@bootlin.com> References: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> In-Reply-To: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Add clock indexes for EyeQ6H west OLB. Internal hierarchy is: PLL_PER =E2=94=94=E2=94=80=E2=94=80 PER_OCC =E2=94=94=E2=94=80=E2=94=80 PER_UART Signed-off-by: Th=C3=A9o Lebrun --- include/dt-bindings/clock/mobileye,eyeq5-clk.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bi= ndings/clock/mobileye,eyeq5-clk.h index 2356bc52646df9cfeb93df8120eb8f0bf80d97e9..8efdf0feae8e43e7b84ff9ca12b= 8b90c3116240d 100644 --- a/include/dt-bindings/clock/mobileye,eyeq5-clk.h +++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h @@ -37,6 +37,10 @@ #define EQ6HC_CENTRAL_PLL_CPU 0 #define EQ6HC_CENTRAL_CPU_OCC 1 =20 +#define EQ6HC_WEST_PLL_PER 0 +#define EQ6HC_WEST_PER_OCC 1 +#define EQ6HC_WEST_PER_UART 2 + #define EQ6HC_SOUTH_PLL_VDI 0 #define EQ6HC_SOUTH_PLL_PCIE 1 #define EQ6HC_SOUTH_PLL_PER 2 --=20 2.47.0 From nobody Mon Nov 25 00:26:34 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 573B41B0105; Thu, 31 Oct 2024 15:53:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389990; cv=none; b=a3OrDP4lqUgiqF8q8XJppJSR+iAWf1fYFBDR1/kep0xZuw5vR/NxzYSajdHPNmlZA+VOsixLHffpr7HaGqqrfEvU0tvkYhnCLfoRMU6uQXW1t0y3cnXiZh33ELJAmGPF7AQcvNYRWO7lKv3I170zfH1GxdYuzKTWZvh75bByvmk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389990; c=relaxed/simple; bh=IbL1dIsMDKSWk+juOOze/+/g65R93/+X2wY8wHACvmo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gOSa/0QKdPy93Ievttk5DnTYwJVuaF9oLD778vbDgwYlM9h3R7VMgDKqpfZeINIIUsJbP76XhhJrYpx0nMBCQiIcAL+GSqTU/RaRhNiVqyWy7hZeWlye/gIAbK5dIkLzpBiIIBw5ISYtI7Fco/k9Tp8Z8zeR92VYBIMvz7yKQNE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=CJxvlrt8; arc=none smtp.client-ip=217.70.183.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="CJxvlrt8" Received: by mail.gandi.net (Postfix) with ESMTPSA id 87FA41C0010; Thu, 31 Oct 2024 15:52:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730389980; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8kmyA2fOJCwI24a+4je8+bVYsLftxYiEpbBDgDU16Vo=; b=CJxvlrt8Z654I7Xpw0/3qx96DIpeL9MEhmDRSu3L8fvWl+8ABaBPZu4NnCZbeO39RmILVD tvff+1uHmpuRWW+8LF0YTnoNeWYnakcNSIEZJaTZ+wfbkvE1Pt54t8+oU3x7vmSFSgYfA5 zGyXw+2miiUu8Ah8cN5+yZuka3b4PKBhaJ9ZF0v88vYYncBYBThePQlKAPAATIZXHFmNiw Qe8WUjl0RPn3rbMzTKXZzXI3IjWFmb0UM9mhdH0ZzNKceCHpVLGsN4krJtogA44+6Sl5JP sF/mL5ViuTk43f2aJlOffF49LaC4iWwbcXk+t7LhOebcn1ocxqEMgqxXkbU7ig== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Thu, 31 Oct 2024 16:52:56 +0100 Subject: [PATCH 06/13] clk: fixed-factor: add clk_hw_register_fixed_factor_index() function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241031-mbly-clk-v1-6-89d8b28e3006@bootlin.com> References: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> In-Reply-To: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Add non-devres version of clk_hw_register_fixed_factor(), with parent targeted using its index. Signed-off-by: Th=C3=A9o Lebrun --- drivers/clk/clk-fixed-factor.c | 11 +++++++++++ include/linux/clk-provider.h | 3 +++ 2 files changed, 14 insertions(+) diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index 8fba63fc70c554df0d646dba75c5d70d0b184319..e62ae8794d445f685156276d513= 5448f340fca3f 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -241,6 +241,17 @@ struct clk_hw *clk_hw_register_fixed_factor_with_accur= acy_fwname(struct device * } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_with_accuracy_fwname); =20 +struct clk_hw *clk_hw_register_fixed_factor_index(struct device *dev, + const char *name, unsigned int index, unsigned long flags, + unsigned int mult, unsigned int div) +{ + const struct clk_parent_data pdata =3D { .index =3D index }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL, &pdata, + flags, mult, div, 0, 0, false); +} +EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_index); + struct clk *clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 75444e250a7875a4fa90c9dea7a90b198f6be2b8..99ae3ffb94bc5ce2b8493509cf3= 548b03209852b 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -1142,6 +1142,9 @@ struct clk_hw *clk_hw_register_fixed_factor_with_accu= racy_fwname(struct device * struct device_node *np, const char *name, const char *fw_name, unsigned long flags, unsigned int mult, unsigned int div, unsigned long acc); +struct clk_hw *clk_hw_register_fixed_factor_index(struct device *dev, + const char *name, unsigned int index, unsigned long flags, + unsigned int mult, unsigned int div); void clk_hw_unregister_fixed_factor(struct clk_hw *hw); struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, --=20 2.47.0 From nobody Mon Nov 25 00:26:34 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CC0D1BC061; Thu, 31 Oct 2024 15:53:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389991; cv=none; b=gccVxH2UHfPjRmtxV4vbGGyJoU1h4uDW2+PBgscEvmHwScW5VIf5knag87U+qSN+GQd5Fk3bz358I/bTgUEIVB2J4iBKEXDQskB2Um+Yqc8QcpQkIRUBUFyoSNggfnCJW4MT1byA5yKCWNHTwhNd0mLX5WY/CTBdwrj3lJpg0jQ= ARC-Message-Signature: i=1; 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Thu, 31 Oct 2024 15:53:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730389981; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iKhRzgiEUNdm1NA9uvOtWIMNNDJizhjx+IFpddS8/Og=; b=kRAQeOcIWRGHq5nIUyXifU4JrfAHkrgWUGMJ/NaGezTX03Mhpz1LYmY8CLcrfSJncnppUF H/LtCjQQ5nmtMtcFHkiuZf3FNbP4q96Vdm5GSSQc2ejUBbFvyQn5T0oRZhmABVIfPPACFs nCmYP+o0UDdTT4BDpIfBKrXJ6A8UwMwDDlwkk+GN6+WUV/LrIrKeN1znvefaRKyFKa5TMg 2sY4sHql5u+lkH+yeM2uP3jazwMRvnc8teW7e/8+Achk1KrWYZuxAlGzthFjjKpYz5P27e ClPVwrg27SVaa0P56GWCmDuj01MK/3OYT/lCccQbtVNq7NdGRpYfzS5v/sqyWA== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Thu, 31 Oct 2024 16:52:57 +0100 Subject: [PATCH 07/13] clk: eyeq: require clock index with phandle in all cases Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241031-mbly-clk-v1-7-89d8b28e3006@bootlin.com> References: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> In-Reply-To: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com We used to let compatibles with a single clock exposed to not have a cell. Switch away from that and enforce a cell in all cases. This is done at the same time as some compatibles (mobileye,eyeq6h-{central,west}-olb) go from one to more clocks exposed. Let's do the same switch and avoid future devicetree work if/when others follow. Signed-off-by: Th=C3=A9o Lebrun --- drivers/clk/clk-eyeq.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index 77f1afb020a0247b9d73b59a88845b21a0d83b5e..ed4dab303d9121cd8bf453448b4= c86547ea9244c 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -367,11 +367,7 @@ static int eqc_probe(struct platform_device *pdev) =20 eqc_probe_init_divs(dev, data, base, cells); =20 - /* When providing a single clock, require no cell. */ - if (clk_count =3D=3D 1) - return of_clk_add_hw_provider(np, of_clk_hw_simple_get, cells->hws[0]); - else - return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells); + return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells); } =20 /* Required early for GIC timer (pll-cpu) and UARTs (pll-per). */ @@ -637,11 +633,7 @@ static void __init eqc_early_init(struct device_node *= np, } } =20 - /* When providing a single clock, require no cell. */ - if (clk_count =3D=3D 1) - ret =3D of_clk_add_hw_provider(np, of_clk_hw_simple_get, cells->hws[0]); - else - ret =3D of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells); + ret =3D of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells); if (ret) { pr_err("failed registering clk provider: %d\n", ret); goto err; --=20 2.47.0 From nobody Mon Nov 25 00:26:34 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E8541BBBE5; Thu, 31 Oct 2024 15:53:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389991; cv=none; b=sqJFFScX5kQkMqaY2hbtKJEsVhG6KJo+jPGloyWRFnhKVuOV16uaLBJnbvvgI4ApWw5EPHywt1QFtyAPp6ZcuVJRJfIyZ99oW3+djejHbo0O6rBit5+aof7LUC3h4tcKKUG87XOzn8r/W56JlYaxBAl60os9kjP49/Vh7os6sWc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389991; c=relaxed/simple; bh=D6YiasuUdXolLDdfIbpCPcpZZypNlcg3gn0qVUQ+fA4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MRI1ZBvxxFGwAxkiDausi7yp0EjqE4D3fKq/d4YnCGSSfIjAPWCKm7CQf3Sq+wG0sJzfE8O3d0Am+a9fQhPzVbp1O9AW0RCmR/JmdAiXpWmNCCc3bGwKNf6VhSKeNBqQemkZd3fXyN2GXa0aRIYiLTQSXUTx8QLRiGuNZdtbYMw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=j3dDhg6A; arc=none smtp.client-ip=217.70.183.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="j3dDhg6A" Received: by mail.gandi.net (Postfix) with ESMTPSA id 119DF1C000B; Thu, 31 Oct 2024 15:53:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730389981; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=G518BfRB+SDjVWzkdrr74EZK8dQU+mBfUeQH9gtkcWs=; b=j3dDhg6AN1+BOWCX2cKiYnOgVLpxzw9POFt+P0Vyuwv3sqXPYURKFd9f8TouCNTsYiqgMx 0kFDa/Y2r26IeY18/2QPoXcqXGqdoWTWp0WhVwJBqfh+K9shXuVinDrG1sSxNrwr9IGzhS GN0OWxlgJra4qW8Kos1sZbFQ2bWE+sbkfpUlU3G+sc6msK99Y/f5ADl/CuG7K5TOKA50RM Bl8kicnGo4jJ5b6IlX5o6O8rsqCTFelE6DAygMr3mvxylpXzpzFP9l61RKvWpRS8pnJo4R k/BueSPIqJb8E1La1+6oWpa/DadPyXYqwZZiyUgtpg6u4OBXFplQLZbKs4gx3Q== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Thu, 31 Oct 2024 16:52:58 +0100 Subject: [PATCH 08/13] clk: eyeq: add fixed factor clocks infrastructure Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241031-mbly-clk-v1-8-89d8b28e3006@bootlin.com> References: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> In-Reply-To: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Driver can currently host two types of clocks: - PLLs derived directly from the main crystal (taken using a fwhandle). - Divider clocks derived from those PLLs. PLLs can be instantiated from of_clk_init() or platform device probe, using two separate clock providers. Divider clocks are all instantiated at platform device probe. Add a third type of clocks: fixed factors. Those can be instantiated at both stages. They can be parented to any clock from the driver. Early match data and match data store the list of fixed factor clocks. Signed-off-by: Th=C3=A9o Lebrun --- drivers/clk/clk-eyeq.c | 81 +++++++++++++++++++++++++++++++++++++++++++++-= ---- 1 file changed, 73 insertions(+), 8 deletions(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index ed4dab303d9121cd8bf453448b4c86547ea9244c..dcd1d996255fc97449ac1bccb6a= 7c810d6e4c9db 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -2,11 +2,14 @@ /* * PLL clock driver for the Mobileye EyeQ5, EyeQ6L and EyeQ6H platforms. * - * This controller handles read-only PLLs, all derived from the same main - * crystal clock. It also exposes divider clocks, those are children to PL= Ls. - * Parent clock is expected to be constant. This driver's registers live in - * a shared region called OLB. Some PLLs are initialised early by of_clk_i= nit(); - * if so, two clk providers are registered. + * This controller handles: + * - Read-only PLLs, all derived from the same main crystal clock. + * - It also exposes divider clocks, those are children to PLLs. + * - Fixed factor clocks, children to PLLs. + * + * Parent clock is expected to be constant. This driver's registers live i= n a + * shared region called OLB. Some PLLs and fixed-factors are initialised e= arly + * by of_clk_init(); if so, two clk providers are registered. * * We use eqc_ as prefix, as-in "EyeQ Clock", but way shorter. * @@ -86,6 +89,14 @@ struct eqc_div { u8 width; }; =20 +struct eqc_fixed_factor { + unsigned int index; + const char *name; + unsigned int mult; + unsigned int div; + unsigned int parent; +}; + struct eqc_match_data { unsigned int pll_count; const struct eqc_pll *plls; @@ -93,6 +104,9 @@ struct eqc_match_data { unsigned int div_count; const struct eqc_div *divs; =20 + unsigned int fixed_factor_count; + const struct eqc_fixed_factor *fixed_factors; + const char *reset_auxdev_name; const char *pinctrl_auxdev_name; =20 @@ -103,6 +117,9 @@ struct eqc_early_match_data { unsigned int early_pll_count; const struct eqc_pll *early_plls; =20 + unsigned int early_fixed_factor_count; + const struct eqc_fixed_factor *early_fixed_factors; + /* * We want our of_xlate callback to EPROBE_DEFER instead of dev_err() * and EINVAL. For that, we must know the total clock count. @@ -276,6 +293,35 @@ static void eqc_probe_init_divs(struct device *dev, co= nst struct eqc_match_data } } =20 +static void eqc_probe_init_fixed_factors(struct device *dev, + const struct eqc_match_data *data, + struct clk_hw_onecell_data *cells) +{ + const struct eqc_fixed_factor *ff; + struct clk_hw *hw, *parent_hw; + unsigned int i; + + for (i =3D 0; i < data->fixed_factor_count; i++) { + ff =3D &data->fixed_factors[i]; + parent_hw =3D cells->hws[ff->parent]; + + if (IS_ERR(parent_hw)) { + /* Parent is in early clk provider. */ + hw =3D clk_hw_register_fixed_factor_index(dev, ff->name, + ff->parent, 0, ff->mult, ff->div); + } else { + /* Avoid clock lookup when we already have the hw reference. */ + hw =3D clk_hw_register_fixed_factor_parent_hw(dev, ff->name, + parent_hw, 0, ff->mult, ff->div); + } + + cells->hws[ff->index] =3D hw; + if (IS_ERR(hw)) + dev_warn(dev, "failed registering %s: %pe\n", + ff->name, hw); + } +} + static void eqc_auxdev_release(struct device *dev) { struct auxiliary_device *adev =3D to_auxiliary_dev(dev); @@ -349,10 +395,11 @@ static int eqc_probe(struct platform_device *pdev) KBUILD_MODNAME, data->pinctrl_auxdev_name, ret); } =20 - if (data->pll_count + data->div_count =3D=3D 0) + if (data->pll_count + data->div_count + data->fixed_factor_count =3D=3D 0) return 0; /* Zero clocks, we are done. */ =20 - clk_count =3D data->pll_count + data->div_count + data->early_clk_count; + clk_count =3D data->pll_count + data->div_count + + data->fixed_factor_count + data->early_clk_count; cells =3D kzalloc(struct_size(cells, hws, clk_count), GFP_KERNEL); if (!cells) return -ENOMEM; @@ -367,6 +414,8 @@ static int eqc_probe(struct platform_device *pdev) =20 eqc_probe_init_divs(dev, data, base, cells); =20 + eqc_probe_init_fixed_factors(dev, data, cells); + return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells); } =20 @@ -580,7 +629,8 @@ static void __init eqc_early_init(struct device_node *n= p, void __iomem *base; int ret; =20 - clk_count =3D early_data->early_pll_count + early_data->late_clk_count; + clk_count =3D early_data->early_pll_count + early_data->early_fixed_facto= r_count + + early_data->late_clk_count; cells =3D kzalloc(struct_size(cells, hws, clk_count), GFP_KERNEL); if (!cells) { ret =3D -ENOMEM; @@ -633,6 +683,21 @@ static void __init eqc_early_init(struct device_node *= np, } } =20 + for (i =3D 0; i < early_data->early_fixed_factor_count; i++) { + const struct eqc_fixed_factor *ff =3D &early_data->early_fixed_factors[i= ]; + struct clk_hw *parent_hw =3D cells->hws[ff->parent]; + struct clk_hw *hw; + + hw =3D clk_hw_register_fixed_factor_parent_hw(NULL, + ff->name, parent_hw, 0, ff->mult, ff->div); + cells->hws[ff->index] =3D hw; + if (IS_ERR(hw)) { + pr_err("failed registering %s: %pe\n", ff->name, hw); + ret =3D PTR_ERR(hw); + goto err; + } + } + ret =3D of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells); if (ret) { pr_err("failed registering clk provider: %d\n", ret); --=20 2.47.0 From nobody Mon Nov 25 00:26:34 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE57713AA5F; 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arc=none smtp.client-ip=217.70.183.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="bHaux5D4" Received: by mail.gandi.net (Postfix) with ESMTPSA id BF0C51C000E; Thu, 31 Oct 2024 15:53:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730389982; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sSwt+cxcfS7jbQKfYXSNlyiiZCMiLyAs/aVWPNKz9/A=; b=bHaux5D4f9ssnE+NEuS4PwONADFJuJiRO9RQsdOX5mZwtv0RqGUACgE0Bmcp+okEI7p0Su IlvaGbFQ3y+BEVP0YSqom7/lTbf+l2gRGhX/sul4dAvcHN1r9TThv76LNHi+HVbgOLoWYT MykS2Npbhm2Dy1v/RJ63PQrDnhSE7TbJFnq8F5qopb1w2EO8KX84ASAaIZUx/52XCw3fu8 UHIhVlrqeI5t9fztlL5de7Kf81/fZ7P4es3tyj1vsH2GWrMLQkLtYry5dd4sXD9TDkIt/Z bAemGNrIHrpqso/Ng8K+clDrDGFNkV2X/iTbii9a8h07EHTTnMVUvMyDyDIg1w== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Thu, 31 Oct 2024 16:52:59 +0100 Subject: [PATCH 09/13] clk: eyeq: add EyeQ5 fixed factor clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241031-mbly-clk-v1-9-89d8b28e3006@bootlin.com> References: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> In-Reply-To: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Expose additional clocks on EyeQ5. Some indexes come from dt-bindings headers, others are private to the driver. Few clocks are early (of_clk_init() stage: core clocks and UART clock), others can wait until platform device probe. The source for this list is downstream Mobileye kernel and some internal documentation. Signed-off-by: Th=C3=A9o Lebrun --- drivers/clk/clk-eyeq.c | 92 ++++++++++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 90 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index dcd1d996255fc97449ac1bccb6a7c810d6e4c9db..6337736ef0ccb963fc16f66b1c7= 8c33fdff0f99f 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -436,6 +436,86 @@ static const struct eqc_pll eqc_eyeq5_plls[] =3D { { .index =3D EQ5C_PLL_DDR1, .name =3D "pll-ddr1", .reg64 =3D 0x074 }, }; =20 +/* EQ5C_PLL_CPU children */ +#define EQ5C_CPU_OCC 17 +#define EQ5C_CPU_SI_CSS0 18 +#define EQ5C_CPU_CPC 19 +#define EQ5C_CPU_CM 20 +#define EQ5C_CPU_MEM 21 +#define EQ5C_CPU_OCC_ISRAM 22 +#define EQ5C_CPU_ISRAM 23 +#define EQ5C_CPU_OCC_DBU 24 +#define EQ5C_CPU_SI_DBU_TP 25 + +/* EQ5C_PLL_VDI children */ +#define EQ5C_VDI_OCC_VDI 26 +#define EQ5C_VDI_VDI 27 +#define EQ5C_VDI_OCC_CAN_SER 28 +#define EQ5C_VDI_CAN_SER 29 +#define EQ5C_VDI_I2C_SER 30 + +/* EQ5C_PLL_PER children */ +#define EQ5C_PER_PERIPH 31 +#define EQ5C_PER_CAN 32 +#define EQ5C_PER_SPI 33 +#define EQ5C_PER_I2C 34 +#define EQ5C_PER_TIMER 35 +#define EQ5C_PER_GPIO 36 +#define EQ5C_PER_EMMC 37 +#define EQ5C_PER_CCF 38 +#define EQ5C_PER_OCC_MJPEG 39 +#define EQ5C_PER_HSM 40 +#define EQ5C_PER_MJPEG 41 +#define EQ5C_PER_FCMU_A 42 +#define EQ5C_PER_OCC_PCI 43 + +static const struct eqc_fixed_factor eqc_eyeq5_early_fixed_factors[] =3D { + /* EQ5C_PLL_CPU children */ + { EQ5C_CPU_OCC, "occ-cpu", 1, 1, EQ5C_PLL_CPU }, + { EQ5C_CPU_SI_CSS0, "si-css0", 1, 1, EQ5C_CPU_OCC }, + { EQ5C_CPU_CORE0, "core0", 1, 1, EQ5C_CPU_SI_CSS0 }, + { EQ5C_CPU_CORE1, "core1", 1, 1, EQ5C_CPU_SI_CSS0 }, + { EQ5C_CPU_CORE2, "core2", 1, 1, EQ5C_CPU_SI_CSS0 }, + { EQ5C_CPU_CORE3, "core3", 1, 1, EQ5C_CPU_SI_CSS0 }, + + /* EQ5C_PLL_PER children */ + { EQ5C_PER_OCC, "occ-periph", 1, 16, EQ5C_PLL_PER }, + { EQ5C_PER_UART, "uart", 1, 1, EQ5C_PER_OCC }, +}; + +static const struct eqc_fixed_factor eqc_eyeq5_fixed_factors[] =3D { + /* EQ5C_PLL_CPU children */ + { EQ5C_CPU_CPC, "cpc", 1, 1, EQ5C_CPU_SI_CSS0 }, + { EQ5C_CPU_CM, "cm", 1, 1, EQ5C_CPU_SI_CSS0 }, + { EQ5C_CPU_MEM, "mem", 1, 1, EQ5C_CPU_SI_CSS0 }, + { EQ5C_CPU_OCC_ISRAM, "occ-isram", 1, 2, EQ5C_PLL_CPU }, + { EQ5C_CPU_ISRAM, "isram", 1, 1, EQ5C_CPU_OCC_ISRAM }, + { EQ5C_CPU_OCC_DBU, "occ-dbu", 1, 10, EQ5C_PLL_CPU }, + { EQ5C_CPU_SI_DBU_TP, "si-dbu-tp", 1, 1, EQ5C_CPU_OCC_DBU }, + + /* EQ5C_PLL_VDI children */ + { EQ5C_VDI_OCC_VDI, "occ-vdi", 1, 2, EQ5C_PLL_VDI }, + { EQ5C_VDI_VDI, "vdi", 1, 1, EQ5C_VDI_OCC_VDI }, + { EQ5C_VDI_OCC_CAN_SER, "occ-can-ser", 1, 16, EQ5C_PLL_VDI }, + { EQ5C_VDI_CAN_SER, "can-ser", 1, 1, EQ5C_VDI_OCC_CAN_SER }, + { EQ5C_VDI_I2C_SER, "i2c-ser", 1, 20, EQ5C_PLL_VDI }, + + /* EQ5C_PLL_PER children */ + { EQ5C_PER_PERIPH, "periph", 1, 1, EQ5C_PER_OCC }, + { EQ5C_PER_CAN, "can", 1, 1, EQ5C_PER_OCC }, + { EQ5C_PER_SPI, "spi", 1, 1, EQ5C_PER_OCC }, + { EQ5C_PER_I2C, "i2c", 1, 1, EQ5C_PER_OCC }, + { EQ5C_PER_TIMER, "timer", 1, 1, EQ5C_PER_OCC }, + { EQ5C_PER_GPIO, "gpio", 1, 1, EQ5C_PER_OCC }, + { EQ5C_PER_EMMC, "emmc-sys", 1, 10, EQ5C_PLL_PER }, + { EQ5C_PER_CCF, "ccf-ctrl", 1, 4, EQ5C_PLL_PER }, + { EQ5C_PER_OCC_MJPEG, "occ-mjpeg", 1, 2, EQ5C_PLL_PER }, + { EQ5C_PER_HSM, "hsm", 1, 1, EQ5C_PER_OCC_MJPEG }, + { EQ5C_PER_MJPEG, "mjpeg", 1, 1, EQ5C_PER_OCC_MJPEG }, + { EQ5C_PER_FCMU_A, "fcmu-a", 1, 20, EQ5C_PLL_PER }, + { EQ5C_PER_OCC_PCI, "occ-pci-sys", 1, 8, EQ5C_PLL_PER }, +}; + static const struct eqc_div eqc_eyeq5_divs[] =3D { { .index =3D EQ5C_DIV_OSPI, @@ -451,7 +531,11 @@ static const struct eqc_early_match_data eqc_eyeq5_ear= ly_match_data __initconst .early_pll_count =3D ARRAY_SIZE(eqc_eyeq5_early_plls), .early_plls =3D eqc_eyeq5_early_plls, =20 - .late_clk_count =3D ARRAY_SIZE(eqc_eyeq5_plls) + ARRAY_SIZE(eqc_eyeq5_di= vs), + .early_fixed_factor_count =3D ARRAY_SIZE(eqc_eyeq5_early_fixed_factors), + .early_fixed_factors =3D eqc_eyeq5_early_fixed_factors, + + .late_clk_count =3D ARRAY_SIZE(eqc_eyeq5_plls) + ARRAY_SIZE(eqc_eyeq5_di= vs) + + ARRAY_SIZE(eqc_eyeq5_fixed_factors), }; =20 static const struct eqc_match_data eqc_eyeq5_match_data =3D { @@ -461,10 +545,14 @@ static const struct eqc_match_data eqc_eyeq5_match_da= ta =3D { .div_count =3D ARRAY_SIZE(eqc_eyeq5_divs), .divs =3D eqc_eyeq5_divs, =20 + .fixed_factor_count =3D ARRAY_SIZE(eqc_eyeq5_fixed_factors), + .fixed_factors =3D eqc_eyeq5_fixed_factors, + .reset_auxdev_name =3D "reset", .pinctrl_auxdev_name =3D "pinctrl", =20 - .early_clk_count =3D ARRAY_SIZE(eqc_eyeq5_early_plls), + .early_clk_count =3D ARRAY_SIZE(eqc_eyeq5_early_plls) + + ARRAY_SIZE(eqc_eyeq5_early_fixed_factors), }; =20 static const struct eqc_pll eqc_eyeq6l_plls[] =3D { --=20 2.47.0 From nobody Mon Nov 25 00:26:34 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 680631BBBFC; Thu, 31 Oct 2024 15:53:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389991; cv=none; b=YK2T0gybnWPv0H1mIe68rlypAyp/hPJ1/mlHYuyP5s72WphbuVFEUt+OwhnhY/M/KsLSvQxaFuXUvS1k+T2X6FEWu5ri4ImMxtXMVLIz+RN8uqPtpBr9dKeeaOn7IuuhyQZKTt9wISFYpJX3dOdOlEf3rSpZP5MQp+qL4NThn/0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389991; c=relaxed/simple; bh=mubpwWm3QFkqioFijcDhodrfP3j1pOhKigFEYlLfcmw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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bh=J19GmzKLXmjkbRnHLjyLOvsgcp8S/EXdBpiEt0g1I0w=; b=QIZNWRjBWV78EFHS+GkZbyLEb5bmOc92ZgheQim7616vvhlmi3g+tfe4YZy1JwMIwwt8Mm G7BMNS5RXRWSyjuEQdxOmcR8SbXar9fdttJCKzO0e85FOT4BZDf7V3W6DbIJwz0g6oD+uP V74oxsVa0MVQ/2hZyQLOKil4wEhZgaVhrc76HsnbRhNoSjWtSpcx9aBriIsFrJ6iZyksKs e968ERt09gJfn3XOAUc6Nz9+H2sQrLbUaClUypKtRyjVPVxGHEh1ZmfXsokcGJjZZoram6 H4MU1z2a3jsLx4uZmU/635fv8ysnN7UVhrspq3IyQXMa/hinDxK2BJ1Uu/Mffg== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Thu, 31 Oct 2024 16:53:00 +0100 Subject: [PATCH 10/13] clk: eyeq: add EyeQ6H central fixed factor clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241031-mbly-clk-v1-10-89d8b28e3006@bootlin.com> References: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> In-Reply-To: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Previous setup was: - pll-cpu clock registered from driver at of_clk_init(); - occ-cpu clock registered from DT using fixed-factor-clock compatible. Now that drivers/clk/clk-eyeq.c supports registering fixed factors, use that capability to register occ-cpu. Also switch from hard-coded index 0 for pll-cpu to using the EQ6HC_CENTRAL_PLL_CPU constant by exposed dt-bindings headers. occ-cpu is exposed at of_clk_init() because it gets used by both the DT CPU nodes and the GIC timer. Signed-off-by: Th=C3=A9o Lebrun --- drivers/clk/clk-eyeq.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index 6337736ef0ccb963fc16f66b1c78c33fdff0f99f..4f6aa852038cfc4db0fc4473cf5= e50c6c254b9ee 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -691,12 +691,19 @@ builtin_platform_driver(eqc_driver); =20 /* Required early for GIC timer. */ static const struct eqc_pll eqc_eyeq6h_central_early_plls[] =3D { - { .index =3D 0, .name =3D "pll-cpu", .reg64 =3D 0x02C }, + { .index =3D EQ6HC_CENTRAL_PLL_CPU, .name =3D "pll-cpu", .reg64 =3D 0x02C= }, +}; + +static const struct eqc_fixed_factor eqc_eyeq6h_central_early_fixed_factor= s[] =3D { + { EQ6HC_CENTRAL_CPU_OCC, "occ-cpu", 1, 1, EQ6HC_CENTRAL_PLL_CPU }, }; =20 static const struct eqc_early_match_data eqc_eyeq6h_central_early_match_da= ta __initconst =3D { .early_pll_count =3D ARRAY_SIZE(eqc_eyeq6h_central_early_plls), .early_plls =3D eqc_eyeq6h_central_early_plls, + + .early_fixed_factor_count =3D ARRAY_SIZE(eqc_eyeq6h_central_early_fixed_f= actors), + .early_fixed_factors =3D eqc_eyeq6h_central_early_fixed_factors, }; =20 /* Required early for UART. */ --=20 2.47.0 From nobody Mon Nov 25 00:26:34 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3545A1BBBDA; Thu, 31 Oct 2024 15:53:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389991; cv=none; b=oWVaw7AhD0/O4/u8ZIGxpvee39JjP+8/hZ+6oxFuFaw9TqK66ll7ZbMSfgorCtfZWY8Bz50BeZiplBbgIo+KKzFKr7ESSRR7jdBI3eZoj0xUiyq9mKmpM4Uw7+F0nAMNcBStxPHMfOgttesIC75pb79X2JYtKiiRadHoxVuIQ6g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389991; c=relaxed/simple; bh=VamhRTqa9DTI1GQti9bpMRr8+2GVZTOuU6CSWkQMOc8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=a5nG6hWDjhRZiIt6kvd4uq1t+/d4J4JSnPV6GbLF2b2KYuC/jIz/XoN0SZZ9Mp2aSSfjwSq4eCzQZE51tTNUDE7IiueA/aNTtPqMvHecOBG55/tL+e16GvL+rvgaaVA2zht6VwgQCyzuo1jA6LZz4MPXCKFvTrcrBc5beY8LrxU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=cn6HwxMR; arc=none smtp.client-ip=217.70.183.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="cn6HwxMR" Received: by mail.gandi.net (Postfix) with ESMTPSA id 2603C1C000D; Thu, 31 Oct 2024 15:53:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730389983; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AGl0zvxVHy/3JEMiH4QJrzF7cj+Sn8CkYpJlMAQBR0Y=; b=cn6HwxMRMhUXxavs/EVhhPbeC3Xc7mfmkKA+GUF6ub5q3ux8iZDYDBgQDUelLZycopPtXw kLAo7nvdhANGCfH5Z1OvctbhqUVjAHnJPBtub/hb33vPkBidedg0BkN0h5IqFMcOGR8ocf cPdi6ZNisLmM/RPFcgSqrMWjrYWWc+rzFSRuslVsxW24PCeMplSjCPlbHEaZk2uBKR9h6G LFV9kAylwd5WpCQgYjH/THURyttTdXwaBD02kVALUqJFYc4jXDPl/lEWdvirTBIs4QR8VR uOF6shtiOQ6Rte9Ph4kpxWtOp5pAYYPFpkjhM1/y1auX3LdXwbV4+WObB2qVCw== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Thu, 31 Oct 2024 16:53:01 +0100 Subject: [PATCH 11/13] clk: eyeq: add EyeQ6H west fixed factor clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241031-mbly-clk-v1-11-89d8b28e3006@bootlin.com> References: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> In-Reply-To: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Previous setup was: - pll-west clock registered from driver at of_clk_init(); - Both OCC and UART clocks registered from DT using fixed-factor-clock compatible. Now that drivers/clk/clk-eyeq.c supports registering fixed factors, use that capability to register west-per-occ and west-per-uart (giving them proper names at the same time). Also switch from hard-coded index 0 for pll-west to using the EQ6HC_WEST_PLL_PER constant by exposed dt-bindings headers. All get exposed at of_clk_init() because they get used by the AMBA PL011 serial ports. Those are instantiated before platform bus infrastructure. Signed-off-by: Th=C3=A9o Lebrun --- drivers/clk/clk-eyeq.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index 4f6aa852038cfc4db0fc4473cf5e50c6c254b9ee..f3ef4293b97bd553fbfd74b8dac= 4811772729458 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -708,12 +708,20 @@ static const struct eqc_early_match_data eqc_eyeq6h_c= entral_early_match_data __i =20 /* Required early for UART. */ static const struct eqc_pll eqc_eyeq6h_west_early_plls[] =3D { - { .index =3D 0, .name =3D "pll-west", .reg64 =3D 0x074 }, + { .index =3D EQ6HC_WEST_PLL_PER, .name =3D "pll-west", .reg64 =3D 0x074 }, +}; + +static const struct eqc_fixed_factor eqc_eyeq6h_west_early_fixed_factors[]= =3D { + { EQ6HC_WEST_PER_OCC, "west-per-occ", 1, 10, EQ6HC_WEST_PLL_PER }, + { EQ6HC_WEST_PER_UART, "west-per-uart", 1, 1, EQ6HC_WEST_PER_OCC }, }; =20 static const struct eqc_early_match_data eqc_eyeq6h_west_early_match_data = __initconst =3D { .early_pll_count =3D ARRAY_SIZE(eqc_eyeq6h_west_early_plls), .early_plls =3D eqc_eyeq6h_west_early_plls, + + .early_fixed_factor_count =3D ARRAY_SIZE(eqc_eyeq6h_west_early_fixed_fact= ors), + .early_fixed_factors =3D eqc_eyeq6h_west_early_fixed_factors, }; =20 static void __init eqc_early_init(struct device_node *np, --=20 2.47.0 From nobody Mon Nov 25 00:26:34 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67FC81BBBF8; Thu, 31 Oct 2024 15:53:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389992; cv=none; b=XAYWHLDXOIKnecoKzQkGYE1og+GlsWT+wef5pErwn5o9p5bfC32Bmbk6siZDZPJVCj7XuKvt7HDRetXIhw+KlJtg3haISVb9lnzv0zQXGdBOvB+byGGbOvAnT33FvVfRv+2W2gCET7B/QLd1Zhx8F/Mtjjkt51zluq89OmTbsrI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389992; c=relaxed/simple; bh=dpx86UKWHmQob1x1Y9dZoFYGDcYgFQTexwF3Pl4RVJg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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bh=vBvALQBz6nzlJoEhBr0vnmX8yOjbMQW6G7cmJmWOtDo=; b=AfwfZfKV+IE3wQL2HZvOVFbJNo8j3ZNamNUpRWTmIXZNvsFNDfG06H6x4gbSOPKq9nJrLi roNGgwJegeryDpY82DprD9sJc2jYYQs6ONSVdRCuj58qQwHJlLaI15fo3x+32bymftoQgP pY/kqaAooFobedTDO2LVm9aHwUMZRmfB0HBy8tTOCqfgXpkaaaDoSDfJKUGKHh+u9qCcWQ oo3dZXfA37XDBjB42Vp1YNW/SWqWjML3qAoJqmZBRlcQxpk5IsFUu4nPDV3Mx3Ct16vdmT zJ4sCAwYcBEo9RIDb4lq783+Ghz04Aw1VeusISASxIKkncGCsEJD7cF8KCoKdg== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Thu, 31 Oct 2024 16:53:02 +0100 Subject: [PATCH 12/13] MIPS: mobileye: eyeq5: use OLB as provider for fixed factor clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241031-mbly-clk-v1-12-89d8b28e3006@bootlin.com> References: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> In-Reply-To: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Change the structure of the clock tree: rather than individual devicetree nodes registering each fixed factor clock derived from OLB PLLs, have the OLB node provide the necessary clocks. Remove eyeq5-clocks.dtsi and move the three remaining "fixed-clock"s to the main eyeq5.dtsi file. Signed-off-by: Th=C3=A9o Lebrun --- arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi | 270 ----------------------= ---- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 30 ++- 2 files changed, 24 insertions(+), 276 deletions(-) diff --git a/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi b/arch/mips/boot= /dts/mobileye/eyeq5-clocks.dtsi deleted file mode 100644 index 17a342cc744e57dc1f21262abdbfa97d4e4d58f3..000000000000000000000000000= 0000000000000 --- a/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi +++ /dev/null @@ -1,270 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Copyright 2023 Mobileye Vision Technologies Ltd. - */ - -#include - -/ { - /* Fixed clock */ - xtal: xtal { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <30000000>; - }; - -/* PLL_CPU derivatives */ - occ_cpu: occ-cpu { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_CPU>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - si_css0_ref_clk: si-css0-ref-clk { /* gate ClkRstGen_si_css0_ref */ - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_cpu>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - cpc_clk: cpc-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&si_css0_ref_clk>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - core0_clk: core0-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&si_css0_ref_clk>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - core1_clk: core1-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&si_css0_ref_clk>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - core2_clk: core2-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&si_css0_ref_clk>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - core3_clk: core3-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&si_css0_ref_clk>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - cm_clk: cm-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&si_css0_ref_clk>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - mem_clk: mem-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&si_css0_ref_clk>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - occ_isram: occ-isram { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_CPU>; - #clock-cells =3D <0>; - clock-div =3D <2>; - clock-mult =3D <1>; - }; - isram_clk: isram-clk { /* gate ClkRstGen_isram */ - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_isram>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - occ_dbu: occ-dbu { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_CPU>; - #clock-cells =3D <0>; - clock-div =3D <10>; - clock-mult =3D <1>; - }; - si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */ - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_dbu>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; -/* PLL_VDI derivatives */ - occ_vdi: occ-vdi { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_VDI>; - #clock-cells =3D <0>; - clock-div =3D <2>; - clock-mult =3D <1>; - }; - vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */ - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_vdi>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - occ_can_ser: occ-can-ser { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_VDI>; - #clock-cells =3D <0>; - clock-div =3D <16>; - clock-mult =3D <1>; - }; - can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */ - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_can_ser>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - i2c_ser_clk: i2c-ser-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_VDI>; - #clock-cells =3D <0>; - clock-div =3D <20>; - clock-mult =3D <1>; - }; -/* PLL_PER derivatives */ - occ_periph: occ-periph { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_PER>; - #clock-cells =3D <0>; - clock-div =3D <16>; - clock-mult =3D <1>; - }; - periph_clk: periph-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_periph>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - can_clk: can-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_periph>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - spi_clk: spi-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_periph>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - uart_clk: uart-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_periph>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - i2c_clk: i2c-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_periph>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - clock-output-names =3D "i2c_clk"; - }; - timer_clk: timer-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_periph>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - clock-output-names =3D "timer_clk"; - }; - gpio_clk: gpio-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_periph>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - clock-output-names =3D "gpio_clk"; - }; - emmc_sys_clk: emmc-sys-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_PER>; - #clock-cells =3D <0>; - clock-div =3D <10>; - clock-mult =3D <1>; - clock-output-names =3D "emmc_sys_clk"; - }; - ccf_ctrl_clk: ccf-ctrl-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_PER>; - #clock-cells =3D <0>; - clock-div =3D <4>; - clock-mult =3D <1>; - clock-output-names =3D "ccf_ctrl_clk"; - }; - occ_mjpeg_core: occ-mjpeg-core { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_PER>; - #clock-cells =3D <0>; - clock-div =3D <2>; - clock-mult =3D <1>; - clock-output-names =3D "occ_mjpeg_core"; - }; - hsm_clk: hsm-clk { /* gate ClkRstGen_hsm */ - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_mjpeg_core>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - clock-output-names =3D "hsm_clk"; - }; - mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */ - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_mjpeg_core>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - clock-output-names =3D "mjpeg_core_clk"; - }; - fcmu_a_clk: fcmu-a-clk { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_PER>; - #clock-cells =3D <0>; - clock-div =3D <20>; - clock-mult =3D <1>; - clock-output-names =3D "fcmu_a_clk"; - }; - occ_pci_sys: occ-pci-sys { - compatible =3D "fixed-factor-clock"; - clocks =3D <&olb EQ5C_PLL_PER>; - #clock-cells =3D <0>; - clock-div =3D <8>; - clock-mult =3D <1>; - clock-output-names =3D "occ_pci_sys"; - }; - pclk: pclk { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <250000000>; /* 250MHz */ - }; - tsu_clk: tsu-clk { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <125000000>; /* 125MHz */ - }; -}; diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mo= bileye/eyeq5.dtsi index 0708771c193d064fa56be2c7f6115672b5c24d8d..5d73e8320b8efc1b4f68923482b= f188c4345f1cb 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -5,7 +5,7 @@ =20 #include =20 -#include "eyeq5-clocks.dtsi" +#include =20 / { #address-cells =3D <2>; @@ -17,7 +17,7 @@ cpu@0 { device_type =3D "cpu"; compatible =3D "img,i6500"; reg =3D <0>; - clocks =3D <&core0_clk>; + clocks =3D <&olb EQ5C_CPU_CORE0>; }; }; =20 @@ -64,6 +64,24 @@ cpu_intc: interrupt-controller { #interrupt-cells =3D <1>; }; =20 + xtal: xtal { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <30000000>; + }; + + pclk: pclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <250000000>; /* 250MHz */ + }; + + tsu_clk: tsu-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; /* 125MHz */ + }; + soc: soc { #address-cells =3D <2>; #size-cells =3D <2>; @@ -76,7 +94,7 @@ uart0: serial@800000 { reg-io-width =3D <4>; interrupt-parent =3D <&gic>; interrupts =3D ; - clocks =3D <&uart_clk>, <&occ_periph>; + clocks =3D <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>; clock-names =3D "uartclk", "apb_pclk"; resets =3D <&olb 0 10>; pinctrl-names =3D "default"; @@ -89,7 +107,7 @@ uart1: serial@900000 { reg-io-width =3D <4>; interrupt-parent =3D <&gic>; interrupts =3D ; - clocks =3D <&uart_clk>, <&occ_periph>; + clocks =3D <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>; clock-names =3D "uartclk", "apb_pclk"; resets =3D <&olb 0 11>; pinctrl-names =3D "default"; @@ -102,7 +120,7 @@ uart2: serial@a00000 { reg-io-width =3D <4>; interrupt-parent =3D <&gic>; interrupts =3D ; - clocks =3D <&uart_clk>, <&occ_periph>; + clocks =3D <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>; clock-names =3D "uartclk", "apb_pclk"; resets =3D <&olb 0 12>; pinctrl-names =3D "default"; @@ -135,7 +153,7 @@ gic: interrupt-controller@140000 { timer { compatible =3D "mti,gic-timer"; interrupts =3D ; - clocks =3D <&core0_clk>; + clocks =3D <&olb EQ5C_CPU_CORE0>; }; }; }; --=20 2.47.0 From nobody Mon Nov 25 00:26:34 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B4B41BBBFE; Thu, 31 Oct 2024 15:53:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389992; cv=none; b=OO9j16r/jYInLI4y7nIEnKeDNWLtN+jWPXrmLwR2kzQMpMHuTqNLBDYMep+Gs3XTOS/fraW64bgUH7E3xfZKy+/Ho0feD77gMpLqU/FdGoIEp/zfwiheaD+2OcVKfJUSPZw/DQRvVWSsuz5NUYStDrI7r9HfbyLKe/PlLX9REww= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730389992; c=relaxed/simple; bh=164AvxpBW24lmZ5bza1gILy+9Z0x/iue+c4IgUxIOFc=; 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730389985; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dNYxA9PoraKNMZJ+/mQFXcEzKQ9APotFg7LB3yegiRc=; b=WatHdMoGNqWDyT/YrFtn7rOlSUilSNy5U+dCRtVlZRDIbiPA4b7hUWRI/86ILF5JCnoNMo gJ4VINXBS2wQkX25w5B5QInCoVztSEM5hwATAPXy6pS6UvT9Nw2dtE0yWOX3wDQl7dXnZL lA+R7fddw/Zwv80mJntbVLeU/X8HfgiJ91vB9X9lO8oVBD1fQ6cndjBqJMeuwhaiL317S6 L0BK2fF9yKHJk/K+GGfrWm/H+WGssUJ/KTt0aqmj4VWm0ia0vJqBAGl6dtQR+BPrPdH8x4 mSWtZmz7QnLQ9k2/MzS2KG7xApWFiuB4rSBcbAsqMMiWqjCCYzcPdWoxxFM6eA== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Thu, 31 Oct 2024 16:53:03 +0100 Subject: [PATCH 13/13] MIPS: mobileye: eyeq6h: add OLB nodes OLB and remove fixed clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241031-mbly-clk-v1-13-89d8b28e3006@bootlin.com> References: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> In-Reply-To: <20241031-mbly-clk-v1-0-89d8b28e3006@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Change the declaration of clocks: remove all fixed clocks and declare system-controllers (OLB) as clock providers. Remove eyeq6h-fixed-clocks.dtsi and move the crystal clock to the main eyeq6h.dtsi file. Signed-off-by: Th=C3=A9o Lebrun --- .../boot/dts/mobileye/eyeq6h-fixed-clocks.dtsi | 52 --------------- arch/mips/boot/dts/mobileye/eyeq6h.dtsi | 73 ++++++++++++++++++= ++-- 2 files changed, 69 insertions(+), 56 deletions(-) diff --git a/arch/mips/boot/dts/mobileye/eyeq6h-fixed-clocks.dtsi b/arch/mi= ps/boot/dts/mobileye/eyeq6h-fixed-clocks.dtsi deleted file mode 100644 index 5fa99e06fde7e8f4942aafe5f6064e2c6f7d83fd..000000000000000000000000000= 0000000000000 --- a/arch/mips/boot/dts/mobileye/eyeq6h-fixed-clocks.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Copyright 2023 Mobileye Vision Technologies Ltd. - */ - -#include - -/ { - xtal: clock-30000000 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <30000000>; - }; - - pll_west: clock-2000000000-west { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <2000000000>; - }; - - pll_cpu: clock-2000000000-cpu { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <2000000000>; - }; - - /* pll-cpu derivatives */ - occ_cpu: clock-2000000000-occ-cpu { - compatible =3D "fixed-factor-clock"; - clocks =3D <&pll_cpu>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - - /* pll-west derivatives */ - occ_periph_w: clock-200000000 { - compatible =3D "fixed-factor-clock"; - clocks =3D <&pll_west>; - #clock-cells =3D <0>; - clock-div =3D <10>; - clock-mult =3D <1>; - }; - uart_clk: clock-200000000-uart { - compatible =3D "fixed-factor-clock"; - clocks =3D <&occ_periph_w>; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - }; - -}; diff --git a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi b/arch/mips/boot/dts/m= obileye/eyeq6h.dtsi index 1db3c3cda2e395025075387bcb66ea0737fd37f6..4a1a43f351d39625b520a16d035= cacd2e29d157c 100644 --- a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi @@ -5,7 +5,7 @@ =20 #include =20 -#include "eyeq6h-fixed-clocks.dtsi" +#include =20 / { #address-cells =3D <2>; @@ -17,7 +17,7 @@ cpu@0 { device_type =3D "cpu"; compatible =3D "img,i6500"; reg =3D <0>; - clocks =3D <&occ_cpu>; + clocks =3D <&olb_central EQ6HC_CENTRAL_CPU_OCC>; }; }; =20 @@ -32,19 +32,42 @@ cpu_intc: interrupt-controller { #interrupt-cells =3D <1>; }; =20 + xtal: clock-30000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <30000000>; + }; + soc: soc { compatible =3D "simple-bus"; #address-cells =3D <2>; #size-cells =3D <2>; ranges; =20 + olb_acc: system-controller@d2003000 { + compatible =3D "mobileye,eyeq6h-acc-olb", "syscon"; + reg =3D <0x0 0xd2003000 0x0 0x1000>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + clocks =3D <&xtal>; + clock-names =3D "ref"; + }; + + olb_central: system-controller@d3100000 { + compatible =3D "mobileye,eyeq6h-central-olb", "syscon"; + reg =3D <0x0 0xd3100000 0x0 0x1000>; + #clock-cells =3D <1>; + clocks =3D <&xtal>; + clock-names =3D "ref"; + }; + uart0: serial@d3331000 { compatible =3D "arm,pl011", "arm,primecell"; reg =3D <0 0xd3331000 0x0 0x1000>; reg-io-width =3D <4>; interrupt-parent =3D <&gic>; interrupts =3D ; - clocks =3D <&occ_periph_w>, <&occ_periph_w>; + clocks =3D <&olb_west EQ6HC_WEST_PER_UART>, <&olb_west EQ6HC_WEST_PER_O= CC>; clock-names =3D "uartclk", "apb_pclk"; }; =20 @@ -56,6 +79,15 @@ pinctrl_west: pinctrl@d3337000 { pinctrl-single,function-mask =3D <0xffff>; }; =20 + olb_west: system-controller@d3338000 { + compatible =3D "mobileye,eyeq6h-west-olb", "syscon"; + reg =3D <0x0 0xd3338000 0x0 0x1000>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + clocks =3D <&xtal>; + clock-names =3D "ref"; + }; + pinctrl_east: pinctrl@d3357000 { compatible =3D "pinctrl-single"; reg =3D <0x0 0xd3357000 0x0 0xb0>; @@ -64,6 +96,23 @@ pinctrl_east: pinctrl@d3357000 { pinctrl-single,function-mask =3D <0xffff>; }; =20 + olb_east: system-controller@d3358000 { + compatible =3D "mobileye,eyeq6h-east-olb", "syscon"; + reg =3D <0x0 0xd3358000 0x0 0x1000>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + clocks =3D <&xtal>; + clock-names =3D "ref"; + }; + + olb_south: system-controller@d8013000 { + compatible =3D "mobileye,eyeq6h-south-olb", "syscon"; + reg =3D <0x0 0xd8013000 0x0 0x1000>; + #clock-cells =3D <1>; + clocks =3D <&xtal>; + clock-names =3D "ref"; + }; + pinctrl_south: pinctrl@d8014000 { compatible =3D "pinctrl-single"; reg =3D <0x0 0xd8014000 0x0 0xf8>; @@ -72,6 +121,22 @@ pinctrl_south: pinctrl@d8014000 { pinctrl-single,function-mask =3D <0xffff>; }; =20 + olb_ddr0: system-controller@e4080000 { + compatible =3D "mobileye,eyeq6h-ddr0-olb", "syscon"; + reg =3D <0x0 0xe4080000 0x0 0x1000>; + #clock-cells =3D <1>; + clocks =3D <&xtal>; + clock-names =3D "ref"; + }; + + olb_ddr1: system-controller@e4081000 { + compatible =3D "mobileye,eyeq6h-ddr1-olb", "syscon"; + reg =3D <0x0 0xe4081000 0x0 0x1000>; + #clock-cells =3D <1>; + clocks =3D <&xtal>; + clock-names =3D "ref"; + }; + gic: interrupt-controller@f0920000 { compatible =3D "mti,gic"; reg =3D <0x0 0xf0920000 0x0 0x20000>; @@ -89,7 +154,7 @@ gic: interrupt-controller@f0920000 { timer { compatible =3D "mti,gic-timer"; interrupts =3D ; - clocks =3D <&occ_cpu>; + clocks =3D <&olb_central EQ6HC_CENTRAL_CPU_OCC>; }; }; }; --=20 2.47.0