From nobody Mon Nov 25 03:50:39 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83553219CA1 for ; Wed, 30 Oct 2024 21:33:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730324008; cv=none; b=lNwnLR1Ple0U8KN6Vb3TM9d7l2MHB+vq1xoz7NezrwHtPJZgrofs3MiVD0wO+hGD7guk+vA+X6nr1YIT2q1JYM9qD+gYSutEYFPpNnUcXrmPFSQJ+EGSIUtZT++otPb/Q1r+HNaEHZQRAeD2bqfSRJTeNzQC2uy6MkPmLVYuL5E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730324008; c=relaxed/simple; bh=tzCoA4Ftaa60Y4uWBgOHGUJtOBHfSgNUhRZfF/Qx16g=; h=Subject:To:Cc:From:Date:References:In-Reply-To:Message-Id; b=cMNgQ9OgQ7iB0TeRt1b/Gd/tcDMqWGKywEZp1oqX/G0uXtICnPKywuF3fpVV1cgHb3CZ090ljeKx2E0wkwIGgV61dQlDkaWxdDRtyFSL62j2uZCT36h+bH9CbpiPYGEloxwUhE7sdXR0yi+1FnGiDSkA0tuBW6r/66j+IlV3NWI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=S2AOmhte; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="S2AOmhte" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730324007; x=1761860007; h=subject:to:cc:from:date:references:in-reply-to: message-id; bh=tzCoA4Ftaa60Y4uWBgOHGUJtOBHfSgNUhRZfF/Qx16g=; b=S2AOmhtes8/JxsFYmAlVdlb32c5XkqV/RphFOF37zwMlb338shH7XDIq HmN4jGdLfbHveI3N5fppf0PP1smZOfVUiGu5hVHVK6Y4Jdk9CBvcTuBo+ /YIX71fg1Lfrz2FGGIxfJZjUwtHyTmiD8AzdmNoYHpD5jSwT3vXuqN3uY 8XYfrfH3F6ip0mfXvjqbmxFjgTny+yaTaw1xVbYGFP3lavGKbYssTtaYC iTnlFOgs2gj8q37Xgq1JiK73HtlhnsYGKUF6IUfoLKHnNRkmd+ttBlLAP FNxnrh8WPUFsbF2gwtv8jn5MmaSTQV7l8smSsj0FoL3kjltwxUe7OMQJd g==; X-CSE-ConnectionGUID: HJLsveW9SdaQJ+qD1p+z8w== X-CSE-MsgGUID: Ec8dQhFBThWr4Ahqu1xTMA== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="33741633" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="33741633" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2024 14:33:27 -0700 X-CSE-ConnectionGUID: DxljJrihQl+SP56IQus5nw== X-CSE-MsgGUID: +K7e5/+wSBuzrKJpqZxQvA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="83257716" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by orviesa008.jf.intel.com with ESMTP; 30 Oct 2024 14:33:27 -0700 Subject: [PATCH 09/11] x86/fpu: Move CPUID leaf definitions to common code To: linux-kernel@vger.kernel.org Cc: x86@kernel.org,tglx@linutronix.de,bp@alien8.de,rafael@kernel.org,lenb@kernel.org,Dave Hansen From: Dave Hansen Date: Wed, 30 Oct 2024 14:33:26 -0700 References: <20241030213310.C4861EC0@davehans-spike.ostc.intel.com> In-Reply-To: <20241030213310.C4861EC0@davehans-spike.ostc.intel.com> Message-Id: <20241030213326.DDC9A7A1@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen Move the XSAVE-related CPUID leaf definitions to common code. Then, use the new definition to remove the last magic number from the CPUID level dependency table. Signed-off-by: Dave Hansen --- b/arch/x86/include/asm/cpuid.h | 2 ++ b/arch/x86/include/asm/fpu/xstate.h | 4 ---- b/arch/x86/kernel/cpu/common.c | 2 +- b/arch/x86/kernel/fpu/xstate.c | 1 + 4 files changed, 4 insertions(+), 5 deletions(-) diff -puN arch/x86/include/asm/cpuid.h~xsave-leaf-checks-1 arch/x86/include= /asm/cpuid.h --- a/arch/x86/include/asm/cpuid.h~xsave-leaf-checks-1 2024-10-30 12:26:58.= 406214724 -0700 +++ b/arch/x86/include/asm/cpuid.h 2024-10-30 12:26:58.414214739 -0700 @@ -21,8 +21,10 @@ enum cpuid_regs_idx { =20 #define CPUID_MWAIT_LEAF 0x5 #define CPUID_DCA_LEAF 0x9 +#define XSTATE_CPUID 0x0d #define CPUID_TSC_LEAF 0x15 #define CPUID_FREQ_LEAF 0x16 +#define TILE_CPUID 0x1d =20 #ifdef CONFIG_X86_32 extern int have_cpuid_p(void); diff -puN arch/x86/include/asm/fpu/xstate.h~xsave-leaf-checks-1 arch/x86/in= clude/asm/fpu/xstate.h --- a/arch/x86/include/asm/fpu/xstate.h~xsave-leaf-checks-1 2024-10-30 12:2= 6:58.410214731 -0700 +++ b/arch/x86/include/asm/fpu/xstate.h 2024-10-30 12:26:58.414214739 -0700 @@ -12,10 +12,6 @@ /* Bit 63 of XCR0 is reserved for future expansion */ #define XFEATURE_MASK_EXTEND (~(XFEATURE_MASK_FPSSE | (1ULL << 63))) =20 -#define XSTATE_CPUID 0x0000000d - -#define TILE_CPUID 0x0000001d - #define FXSAVE_SIZE 512 =20 #define XSAVE_HDR_SIZE 64 diff -puN arch/x86/kernel/cpu/common.c~xsave-leaf-checks-1 arch/x86/kernel/= cpu/common.c --- a/arch/x86/kernel/cpu/common.c~xsave-leaf-checks-1 2024-10-30 12:26:58.= 410214731 -0700 +++ b/arch/x86/kernel/cpu/common.c 2024-10-30 12:26:58.414214739 -0700 @@ -639,7 +639,7 @@ static const struct cpuid_dependent_feat cpuid_dependent_features[] =3D { { X86_FEATURE_MWAIT, CPUID_MWAIT_LEAF }, { X86_FEATURE_DCA, CPUID_DCA_LEAF }, - { X86_FEATURE_XSAVE, 0x0000000d }, + { X86_FEATURE_XSAVE, XSTATE_CPUID }, { 0, 0 } }; =20 diff -puN arch/x86/kernel/fpu/xstate.c~xsave-leaf-checks-1 arch/x86/kernel/= fpu/xstate.c --- a/arch/x86/kernel/fpu/xstate.c~xsave-leaf-checks-1 2024-10-30 12:26:58.= 410214731 -0700 +++ b/arch/x86/kernel/fpu/xstate.c 2024-10-30 12:26:58.414214739 -0700 @@ -20,6 +20,7 @@ #include #include =20 +#include #include #include #include _