From nobody Mon Nov 25 02:02:23 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5CB821766F for ; Wed, 30 Oct 2024 21:33:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730323997; cv=none; b=OoaaA8SRatY1PX6onHeWF8DdRbX0a6j4Z+8BTJ/XzydyE8p+vDnOa9ikJ7QmdhVqTfC8iksR06YKi1D4B4Ql/OD8sXhpps2nbjptcJQujm+pXyr73MNEbxPbaZt5UlAySrJUQHVBdQ7gjPESGZIZ2fe5X1bcOTtqa7IF7PjPf88= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730323997; c=relaxed/simple; bh=gdPb/cie5h5aTBsUi0p8B0ddxH5T5MdH0dbGKN58dbA=; h=Subject:To:Cc:From:Date:References:In-Reply-To:Message-Id; b=kIBc9ebsy9pL0MUhnqxyo9dRgrS/ZuuPLMOsNxkVUibwt4YqKseXsbSC3DjZIyty9fPNcVLQ67uhsvqWsuYP17lCFo7Jbz0+hnleww/721YnOm1XTA1S58/MPE5v5o47mf3lIwT3Q6LvsSKW5CoiDctXWDRM/0avYKDh/asuO3U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=jFYP7Toc; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="jFYP7Toc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730323995; x=1761859995; h=subject:to:cc:from:date:references:in-reply-to: message-id; bh=gdPb/cie5h5aTBsUi0p8B0ddxH5T5MdH0dbGKN58dbA=; b=jFYP7TocdDKtBG/J4+29I3Jay7p1F29x2ztxjUklNVitqpnt7442nt4f tcNjENnRMLyCSeedTzDy9h5+eB9pwkVqlGJAJjtBMNIKOaMQvTqq52rRQ 2/kmVu72Qtw+N9vExhVEoDmrsd85R9pRpd1kzPQtGHX23CmatE/81JHl/ RZoE7VQGWpT7Xf5eHdXozlEBV9x42/LDsg3tWGOzdLU2tVEd4K1/QvdQO 9fg+4EJ1qn/rSUzw7liiNMZKhfoJgXWca2z5aMWIAvwrA37Fks0IJdb05 XD/GEvsAtwQaxYt27Gf2XGnTI3bImCp3Lf90c2L5Ox5bIoz0XoM1EAxBr g==; X-CSE-ConnectionGUID: qGeCVdi3QB+XN+7gF3QkGg== X-CSE-MsgGUID: mCy/P5G4SMiXCU+bj6plOA== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="29904670" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="29904670" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2024 14:33:13 -0700 X-CSE-ConnectionGUID: lgPD0kvSQDekrLhRcsClLg== X-CSE-MsgGUID: bk/a5UkUQ4OYQFHrzn/NPQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="82090451" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by fmviesa007.fm.intel.com with ESMTP; 30 Oct 2024 14:33:13 -0700 Subject: [PATCH 01/11] x86/cpu: Move MWAIT leaf definition to common header To: linux-kernel@vger.kernel.org Cc: x86@kernel.org,tglx@linutronix.de,bp@alien8.de,rafael@kernel.org,lenb@kernel.org,Dave Hansen From: Dave Hansen Date: Wed, 30 Oct 2024 14:33:12 -0700 References: <20241030213310.C4861EC0@davehans-spike.ostc.intel.com> In-Reply-To: <20241030213310.C4861EC0@davehans-spike.ostc.intel.com> Message-Id: <20241030213312.A739971C@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen Begin constructing a common place to keep all CPUID leaf definitions. Move CPUID_MWAIT_LEAF to the CPUID header and include it where needed. Signed-off-by: Dave Hansen --- b/arch/x86/include/asm/cpuid.h | 2 ++ b/arch/x86/include/asm/mwait.h | 1 - b/arch/x86/kernel/acpi/cstate.c | 1 + b/arch/x86/kernel/hpet.c | 1 + b/arch/x86/kernel/process.c | 1 + b/arch/x86/kernel/smpboot.c | 1 + b/arch/x86/xen/enlighten_pv.c | 1 + b/drivers/acpi/acpi_pad.c | 1 + b/drivers/idle/intel_idle.c | 1 + 9 files changed, 9 insertions(+), 1 deletion(-) diff -puN arch/x86/include/asm/cpuid.h~mwait-leaf-checks-0 arch/x86/include= /asm/cpuid.h --- a/arch/x86/include/asm/cpuid.h~mwait-leaf-checks-0 2024-10-30 12:28:09.= 050350096 -0700 +++ b/arch/x86/include/asm/cpuid.h 2024-10-30 12:28:09.062350119 -0700 @@ -19,6 +19,8 @@ enum cpuid_regs_idx { CPUID_EDX, }; =20 +#define CPUID_MWAIT_LEAF 5 + #ifdef CONFIG_X86_32 extern int have_cpuid_p(void); #else diff -puN arch/x86/include/asm/mwait.h~mwait-leaf-checks-0 arch/x86/include= /asm/mwait.h --- a/arch/x86/include/asm/mwait.h~mwait-leaf-checks-0 2024-10-30 12:28:09.= 050350096 -0700 +++ b/arch/x86/include/asm/mwait.h 2024-10-30 12:28:09.062350119 -0700 @@ -15,7 +15,6 @@ #define MWAIT_HINT2SUBSTATE(hint) ((hint) & MWAIT_CSTATE_MASK) #define MWAIT_C1_SUBSTATE_MASK 0xf0 =20 -#define CPUID_MWAIT_LEAF 5 #define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1 #define CPUID5_ECX_INTERRUPT_BREAK 0x2 =20 diff -puN arch/x86/kernel/acpi/cstate.c~mwait-leaf-checks-0 arch/x86/kernel= /acpi/cstate.c --- a/arch/x86/kernel/acpi/cstate.c~mwait-leaf-checks-0 2024-10-30 12:28:09= .054350104 -0700 +++ b/arch/x86/kernel/acpi/cstate.c 2024-10-30 12:28:09.062350119 -0700 @@ -13,6 +13,7 @@ #include =20 #include +#include #include #include =20 diff -puN arch/x86/kernel/hpet.c~mwait-leaf-checks-0 arch/x86/kernel/hpet.c --- a/arch/x86/kernel/hpet.c~mwait-leaf-checks-0 2024-10-30 12:28:09.054350= 104 -0700 +++ b/arch/x86/kernel/hpet.c 2024-10-30 12:28:09.062350119 -0700 @@ -7,6 +7,7 @@ #include #include =20 +#include #include #include #include diff -puN arch/x86/kernel/process.c~mwait-leaf-checks-0 arch/x86/kernel/pro= cess.c --- a/arch/x86/kernel/process.c~mwait-leaf-checks-0 2024-10-30 12:28:09.054= 350104 -0700 +++ b/arch/x86/kernel/process.c 2024-10-30 12:28:09.062350119 -0700 @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include diff -puN arch/x86/kernel/smpboot.c~mwait-leaf-checks-0 arch/x86/kernel/smp= boot.c --- a/arch/x86/kernel/smpboot.c~mwait-leaf-checks-0 2024-10-30 12:28:09.058= 350111 -0700 +++ b/arch/x86/kernel/smpboot.c 2024-10-30 12:28:09.062350119 -0700 @@ -64,6 +64,7 @@ =20 #include #include +#include #include #include #include diff -puN arch/x86/xen/enlighten_pv.c~mwait-leaf-checks-0 arch/x86/xen/enli= ghten_pv.c --- a/arch/x86/xen/enlighten_pv.c~mwait-leaf-checks-0 2024-10-30 12:28:09.0= 58350111 -0700 +++ b/arch/x86/xen/enlighten_pv.c 2024-10-30 12:28:09.062350119 -0700 @@ -49,6 +49,7 @@ #include #include =20 +#include #include #include #include diff -puN drivers/acpi/acpi_pad.c~mwait-leaf-checks-0 drivers/acpi/acpi_pad= .c --- a/drivers/acpi/acpi_pad.c~mwait-leaf-checks-0 2024-10-30 12:28:09.05835= 0111 -0700 +++ b/drivers/acpi/acpi_pad.c 2024-10-30 12:28:09.062350119 -0700 @@ -19,6 +19,7 @@ #include #include #include +#include #include #include =20 diff -puN drivers/idle/intel_idle.c~mwait-leaf-checks-0 drivers/idle/intel_= idle.c --- a/drivers/idle/intel_idle.c~mwait-leaf-checks-0 2024-10-30 12:28:09.062= 350119 -0700 +++ b/drivers/idle/intel_idle.c 2024-10-30 12:28:09.062350119 -0700 @@ -51,6 +51,7 @@ #include #include #include +#include #include #include #include _ From nobody Mon Nov 25 02:02:23 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EF8F1CF7BB for ; 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charset="utf-8" From: Dave Hansen This dependency array uses hard-coded leaf numbers. Use the new common header definition for the MWAIT leaf. Signed-off-by: Dave Hansen --- b/arch/x86/kernel/cpu/common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff -puN arch/x86/kernel/cpu/common.c~mwait-leaf-checks-1 arch/x86/kernel/= cpu/common.c --- a/arch/x86/kernel/cpu/common.c~mwait-leaf-checks-1 2024-10-30 12:28:09.= 562351049 -0700 +++ b/arch/x86/kernel/cpu/common.c 2024-10-30 12:28:09.566351056 -0700 @@ -29,6 +29,7 @@ =20 #include #include +#include #include #include #include @@ -636,7 +637,7 @@ struct cpuid_dependent_feature { =20 static const struct cpuid_dependent_feature cpuid_dependent_features[] =3D { - { X86_FEATURE_MWAIT, 0x00000005 }, + { X86_FEATURE_MWAIT, CPUID_MWAIT_LEAF }, { X86_FEATURE_DCA, 0x00000009 }, { X86_FEATURE_XSAVE, 0x0000000d }, { 0, 0 } _ From nobody Mon Nov 25 02:02:23 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85F2C2178F3 for ; Wed, 30 Oct 2024 21:33:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730323999; cv=none; b=gRjaPqmU1RVAkEKhqjrtrsoqqcoagcvqJWKcXDdQ040M6BaBRDDGXKlQWZ6YewSxwuh8pXF2SOrFCNwpjqb8OE04kUbEAQqRFPVTDRDc5AK9FVVlE32UTvKGLu/BgPvm1RG0nXFRcxAuw91ahBClSvNpQ4z2KBB6Aor0cvb12UQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730323999; c=relaxed/simple; bh=RiZlqPOkcWDYV3s/DPOSTEM4pUVUz5XSVeQqPPc2XjI=; h=Subject:To:Cc:From:Date:References:In-Reply-To:Message-Id; b=N+Sf4VzLMA+KAiCxhYomoBeiycGCPzJvSRLHPXpCpEIdWfsI6u2GDaF5ZzIntWW46d9KfrL1cNmgKqrf7nQvGLq8+YfXuAykE7t6+//mFiZJnA8HV4PTeqlWGA5RSOzrepZU0ZhF9GXmvATCTVboVZLhhN+yeE79wo/8aMce90w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RR8SFUrc; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RR8SFUrc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730323997; x=1761859997; h=subject:to:cc:from:date:references:in-reply-to: message-id; bh=RiZlqPOkcWDYV3s/DPOSTEM4pUVUz5XSVeQqPPc2XjI=; b=RR8SFUrcwDdjmilcs84p2KE+YqASnY4l0KtgQUs03h4NXzVsSendgcfT HCISidVr2yetuGdqq6rHFItpUHIWa3nL1C1kh8K4vzc/xqGepxrtXWFvH bKEiupd5EdWJ4QVyrqkuXiksdaIL/ccoZ6KfYuS/uuP66vXRX+vHwXi9d 7pPfc7ldEo00iDzs/+quT1dFLw4gJoYQdFq8VAzprI/KDTTkMUTOvYkn5 s3dQUGareedOnSoSWp/KesZ3eRRTz3A7t+EbRQJWOa+xYtPw1xPJP7moJ rCXMP6YPSQ9mMGuoDP0xlAneiqAHB7JcHA0OazXgJMNWskZRz9cT4dshW A==; X-CSE-ConnectionGUID: T6fbU6UGQhifv+mNCZoRcg== X-CSE-MsgGUID: fTZiZ3BuSeqDaTUGUQC4Vg== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="29904696" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="29904696" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2024 14:33:17 -0700 X-CSE-ConnectionGUID: zmfkBLItQXm954vjwb8Jug== X-CSE-MsgGUID: iTKVLLViSh2m8UwckepvLw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="82090496" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by fmviesa007.fm.intel.com with ESMTP; 30 Oct 2024 14:33:16 -0700 Subject: [PATCH 03/11] x86/cpu: Remove unnecessary MwAIT leaf checks To: linux-kernel@vger.kernel.org Cc: x86@kernel.org,tglx@linutronix.de,bp@alien8.de,rafael@kernel.org,lenb@kernel.org,Dave Hansen From: Dave Hansen Date: Wed, 30 Oct 2024 14:33:16 -0700 References: <20241030213310.C4861EC0@davehans-spike.ostc.intel.com> In-Reply-To: <20241030213310.C4861EC0@davehans-spike.ostc.intel.com> Message-Id: <20241030213316.95FD3C59@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen The CPUID leaf dependency checker will remove X86_FEATURE_MWAIT if the CPUID level is below the required level (CPUID_MWAIT_LEAF). Thus, if you check X86_FEATURE_MWAIT you do not need to also check the CPUID level. Signed-off-by: Dave Hansen --- b/arch/x86/kernel/hpet.c | 3 --- b/arch/x86/kernel/smpboot.c | 2 -- b/drivers/acpi/acpi_pad.c | 2 -- b/drivers/idle/intel_idle.c | 3 --- 4 files changed, 10 deletions(-) diff -puN arch/x86/kernel/hpet.c~mwait-leaf-checks-2 arch/x86/kernel/hpet.c --- a/arch/x86/kernel/hpet.c~mwait-leaf-checks-2 2024-10-30 12:28:09.946351= 764 -0700 +++ b/arch/x86/kernel/hpet.c 2024-10-30 12:28:09.950351772 -0700 @@ -928,9 +928,6 @@ static bool __init mwait_pc10_supported( if (!cpu_feature_enabled(X86_FEATURE_MWAIT)) return false; =20 - if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) - return false; - cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates); =20 return (ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) && diff -puN arch/x86/kernel/smpboot.c~mwait-leaf-checks-2 arch/x86/kernel/smp= boot.c --- a/arch/x86/kernel/smpboot.c~mwait-leaf-checks-2 2024-10-30 12:28:09.946= 351764 -0700 +++ b/arch/x86/kernel/smpboot.c 2024-10-30 12:28:09.950351772 -0700 @@ -1291,8 +1291,6 @@ static inline void mwait_play_dead(void) return; if (!this_cpu_has(X86_FEATURE_CLFLUSH)) return; - if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) - return; =20 eax =3D CPUID_MWAIT_LEAF; ecx =3D 0; diff -puN drivers/acpi/acpi_pad.c~mwait-leaf-checks-2 drivers/acpi/acpi_pad= .c --- a/drivers/acpi/acpi_pad.c~mwait-leaf-checks-2 2024-10-30 12:28:09.94635= 1764 -0700 +++ b/drivers/acpi/acpi_pad.c 2024-10-30 12:28:09.950351772 -0700 @@ -47,8 +47,6 @@ static void power_saving_mwait_init(void =20 if (!boot_cpu_has(X86_FEATURE_MWAIT)) return; - if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) - return; =20 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx); =20 diff -puN drivers/idle/intel_idle.c~mwait-leaf-checks-2 drivers/idle/intel_= idle.c --- a/drivers/idle/intel_idle.c~mwait-leaf-checks-2 2024-10-30 12:28:09.946= 351764 -0700 +++ b/drivers/idle/intel_idle.c 2024-10-30 12:28:09.950351772 -0700 @@ -2269,9 +2269,6 @@ static int __init intel_idle_init(void) return -ENODEV; } =20 - if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) - return -ENODEV; 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30 Oct 2024 14:33:19 -0700 Subject: [PATCH 04/11] x86/acpi: Check MWAIT feature instead of CPUID level To: linux-kernel@vger.kernel.org Cc: x86@kernel.org,tglx@linutronix.de,bp@alien8.de,rafael@kernel.org,lenb@kernel.org,Dave Hansen From: Dave Hansen Date: Wed, 30 Oct 2024 14:33:18 -0700 References: <20241030213310.C4861EC0@davehans-spike.ostc.intel.com> In-Reply-To: <20241030213310.C4861EC0@davehans-spike.ostc.intel.com> Message-Id: <20241030213318.55C19666@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen I think this code is possibly buggy. The CPU could have a high c->cpuid_level and not support MWAIT at all. It is much more clear to just check for MWAIT support directly. Also, because of the CPU level dependency code, any CPU that has X86_FEATURE_MWAIT also has a high-enough CPUID level. Check X86_FEATURE_MWAIT instead of the CPUID level. Signed-off-by: Dave Hansen --- b/arch/x86/kernel/acpi/cstate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff -puN arch/x86/kernel/acpi/cstate.c~mwait-leaf-checks-3 arch/x86/kernel= /acpi/cstate.c --- a/arch/x86/kernel/acpi/cstate.c~mwait-leaf-checks-3 2024-10-30 12:28:10= .374352561 -0700 +++ b/arch/x86/kernel/acpi/cstate.c 2024-10-30 12:28:10.374352561 -0700 @@ -173,7 +173,7 @@ int acpi_processor_ffh_cstate_probe(unsi struct cpuinfo_x86 *c =3D &cpu_data(cpu); long retval; =20 - if (!cpu_cstate_entry || c->cpuid_level < CPUID_MWAIT_LEAF) + if (!cpu_cstate_entry || cpu_has(c, X86_FEATURE_MWAIT)) return -1; =20 if (reg->bit_offset !=3D NATIVE_CSTATE_BEYOND_HALT) _ From nobody Mon Nov 25 02:02:23 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74985218923 for ; Wed, 30 Oct 2024 21:33:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730324002; cv=none; b=nLVnG/qNIQZXFZW4dL7pouIIt5pcb+V9LYY9sqV/wxERtz2kCrwy48JKWekunRbDt3vlaPNif7GY6hwguOyGPFTs8YrS72lVC1Gq1r7ZwX6+0x/XTc/EM83vCMyRLOC7nvLikLDSw0zW+JaJ1YCKKSz8Hm8FAPjKhbFfAqTi75k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730324002; c=relaxed/simple; bh=go8B4+pe7siTW5DGoQOIZxJeBXZ27xgMdk1GnZ/0bVQ=; h=Subject:To:Cc:From:Date:References:In-Reply-To:Message-Id; b=cFS093fEtDSk1MmPCxRVlgzA+9JTh/0B+GT7aSSgw1NmeNHqQ5nJUtNbNUe9upGLEqs/02OzI/iL5ZhARF5OG1Aj4e2viyciC/FcnlrAHuvqyMymr5CY+zKNX6ithipFoN/dYOoR2Uno+iaB8QkZ/yEJyQdGnUEw9BvVjES9QLw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ZohnSTq+; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ZohnSTq+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730324001; x=1761860001; h=subject:to:cc:from:date:references:in-reply-to: message-id; bh=go8B4+pe7siTW5DGoQOIZxJeBXZ27xgMdk1GnZ/0bVQ=; b=ZohnSTq+bsgC+p9GuE/bOvz+bxKl9xqyj31H3adkjqSsV4ePE6QMG8X5 dFenXqGWYGbq06aFoBZKKB/n46BU4sMe1bPkNteZ23R9Y5SSUj+dYSrPi rCyu/gL7EHmqxx2ghR/vEnOduTQjDZAFUzxEtZRV2rz45D7ltAtIcRZpn +1zswcJn6R9QLMQk+g9F7QisnMkys9QJ8yRbhlolPqo50zDWRoj45rYoD V9kiGtS7U+EWFmD2A6SXanQXrmuUPWE7ZTqbbnaF9aiHl83L+EdzEE4qy XAMPFRPYnBvQBcyXGnbFnE2/TYhUPtfLc3y2bUReB6TyHt1ttgtZ+JCtx Q==; X-CSE-ConnectionGUID: wke4n1gMTHqFRZCKBy1Twg== X-CSE-MsgGUID: cXqV+RNiR6iGzRaWOpD51A== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="33741592" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="33741592" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2024 14:33:20 -0700 X-CSE-ConnectionGUID: 76FhRMrbSmeR9xD1gsggfQ== X-CSE-MsgGUID: TQQrXaHhR9qOUEKpFvMtrw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="83257642" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by orviesa008.jf.intel.com with ESMTP; 30 Oct 2024 14:33:20 -0700 Subject: [PATCH 05/11] x86/cpu: Move DCA leaf definition To: linux-kernel@vger.kernel.org Cc: x86@kernel.org,tglx@linutronix.de,bp@alien8.de,rafael@kernel.org,lenb@kernel.org,Dave Hansen From: Dave Hansen Date: Wed, 30 Oct 2024 14:33:19 -0700 References: <20241030213310.C4861EC0@davehans-spike.ostc.intel.com> In-Reply-To: <20241030213310.C4861EC0@davehans-spike.ostc.intel.com> Message-Id: <20241030213319.DF09AE20@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen The DCA leaf number is also hard-coded in the CPUID level dependency table. Move its definition to common code and use it. While at it, fix up the naming and types in the probe code. All CPUID data is provided in 32-bit registers, not 'unsigned long'. Also stop referring to "level_9". Move away from test_bit() because the type is no longer an 'unsigned long'. Signed-off-by: Dave Hansen --- b/arch/x86/include/asm/cpuid.h | 3 ++- b/arch/x86/kernel/cpu/common.c | 2 +- b/drivers/dma/ioat/dca.c | 8 +++++--- 3 files changed, 8 insertions(+), 5 deletions(-) diff -puN arch/x86/include/asm/cpuid.h~dca-leaf-checks-1 arch/x86/include/a= sm/cpuid.h --- a/arch/x86/include/asm/cpuid.h~dca-leaf-checks-1 2024-10-30 12:26:56.77= 8211510 -0700 +++ b/arch/x86/include/asm/cpuid.h 2024-10-30 12:26:56.782211518 -0700 @@ -19,7 +19,8 @@ enum cpuid_regs_idx { CPUID_EDX, }; =20 -#define CPUID_MWAIT_LEAF 5 +#define CPUID_MWAIT_LEAF 0x5 +#define CPUID_DCA_LEAF 0x9 =20 #ifdef CONFIG_X86_32 extern int have_cpuid_p(void); diff -puN arch/x86/kernel/cpu/common.c~dca-leaf-checks-1 arch/x86/kernel/cp= u/common.c --- a/arch/x86/kernel/cpu/common.c~dca-leaf-checks-1 2024-10-30 12:26:56.78= 2211518 -0700 +++ b/arch/x86/kernel/cpu/common.c 2024-10-30 12:26:56.782211518 -0700 @@ -638,7 +638,7 @@ struct cpuid_dependent_feature { static const struct cpuid_dependent_feature cpuid_dependent_features[] =3D { { X86_FEATURE_MWAIT, CPUID_MWAIT_LEAF }, - { X86_FEATURE_DCA, 0x00000009 }, + { X86_FEATURE_DCA, CPUID_DCA_LEAF }, { X86_FEATURE_XSAVE, 0x0000000d }, { 0, 0 } }; diff -puN drivers/dma/ioat/dca.c~dca-leaf-checks-1 drivers/dma/ioat/dca.c --- a/drivers/dma/ioat/dca.c~dca-leaf-checks-1 2024-10-30 12:26:56.78221151= 8 -0700 +++ b/drivers/dma/ioat/dca.c 2024-10-30 12:26:56.782211518 -0700 @@ -10,6 +10,8 @@ #include #include =20 +#include + /* either a kernel change is needed, or we need something like this in ker= nel */ #ifndef CONFIG_SMP #include @@ -58,11 +60,11 @@ static int dca_enabled_in_bios(struct pc { /* CPUID level 9 returns DCA configuration */ /* Bit 0 indicates DCA enabled by the BIOS */ - unsigned long cpuid_level_9; + u32 eax; int res; =20 - cpuid_level_9 =3D cpuid_eax(9); - res =3D test_bit(0, &cpuid_level_9); + eax =3D cpuid_eax(CPUID_DCA_LEAF); + res =3D eax & BIT(0); if (!res) dev_dbg(&pdev->dev, "DCA is disabled in BIOS\n"); =20 _ From nobody Mon Nov 25 02:02:23 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA4BB21894E for ; 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charset="utf-8" From: Dave Hansen Prepare to use the TSC CPUID leaf definition more widely by moving it to the common header. Signed-off-by: Dave Hansen --- b/arch/x86/events/intel/pt.c | 1 + b/arch/x86/events/intel/pt.h | 3 --- b/arch/x86/include/asm/cpuid.h | 1 + 3 files changed, 2 insertions(+), 3 deletions(-) diff -puN arch/x86/events/intel/pt.c~tsc-leaf-checks-1 arch/x86/events/inte= l/pt.c --- a/arch/x86/events/intel/pt.c~tsc-leaf-checks-1 2024-10-30 12:26:57.1982= 12340 -0700 +++ b/arch/x86/events/intel/pt.c 2024-10-30 12:26:57.206212355 -0700 @@ -18,6 +18,7 @@ #include #include =20 +#include #include #include #include diff -puN arch/x86/events/intel/pt.h~tsc-leaf-checks-1 arch/x86/events/inte= l/pt.h --- a/arch/x86/events/intel/pt.h~tsc-leaf-checks-1 2024-10-30 12:26:57.2022= 12347 -0700 +++ b/arch/x86/events/intel/pt.h 2024-10-30 12:26:57.206212355 -0700 @@ -37,9 +37,6 @@ struct topa_entry { u64 rsvd4 : 12; }; =20 -/* TSC to Core Crystal Clock Ratio */ -#define CPUID_TSC_LEAF 0x15 - struct pt_pmu { struct pmu pmu; u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES]; diff -puN arch/x86/include/asm/cpuid.h~tsc-leaf-checks-1 arch/x86/include/a= sm/cpuid.h --- a/arch/x86/include/asm/cpuid.h~tsc-leaf-checks-1 2024-10-30 12:26:57.20= 2212347 -0700 +++ b/arch/x86/include/asm/cpuid.h 2024-10-30 12:26:57.206212355 -0700 @@ -21,6 +21,7 @@ enum cpuid_regs_idx { =20 #define CPUID_MWAIT_LEAF 0x5 #define CPUID_DCA_LEAF 0x9 +#define CPUID_TSC_LEAF 0x15 =20 #ifdef CONFIG_X86_32 extern int have_cpuid_p(void); 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charset="utf-8" From: Dave Hansen The TSC code has a bunch of hard-coded references to leaf 0x15. Change them over to the symbolic name. Also zap the 'ART_CPUID_LEAF' definition. It was a duplicate of 'CPUID_TSC_LEAF'. Signed-off-by: Dave Hansen --- b/arch/x86/kernel/tsc.c | 11 +++++------ b/drivers/platform/x86/intel/pmc/core.c | 7 ++++--- 2 files changed, 9 insertions(+), 9 deletions(-) diff -puN arch/x86/kernel/tsc.c~tsc-leaf-checks-2 arch/x86/kernel/tsc.c --- a/arch/x86/kernel/tsc.c~tsc-leaf-checks-2 2024-10-30 12:26:57.614213161= -0700 +++ b/arch/x86/kernel/tsc.c 2024-10-30 12:26:57.618213169 -0700 @@ -16,6 +16,7 @@ #include #include =20 +#include #include #include #include @@ -664,13 +665,13 @@ unsigned long native_calibrate_tsc(void) if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL) return 0; =20 - if (boot_cpu_data.cpuid_level < 0x15) + if (boot_cpu_data.cpuid_level < CPUID_TSC_LEAF) return 0; =20 eax_denominator =3D ebx_numerator =3D ecx_hz =3D edx =3D 0; =20 /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ - cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx); + cpuid(CPUID_TSC_LEAF, &eax_denominator, &ebx_numerator, &ecx_hz, &edx); =20 if (ebx_numerator =3D=3D 0 || eax_denominator =3D=3D 0) return 0; @@ -1066,10 +1067,8 @@ core_initcall(cpufreq_register_tsc_scali =20 #endif /* CONFIG_CPU_FREQ */ =20 -#define ART_CPUID_LEAF (0x15) #define ART_MIN_DENOMINATOR (1) =20 - /* * If ART is present detect the numerator:denominator to convert to TSC */ @@ -1077,7 +1076,7 @@ static void __init detect_art(void) { unsigned int unused; =20 - if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF) + if (boot_cpu_data.cpuid_level < CPUID_TSC_LEAF) return; =20 /* @@ -1090,7 +1089,7 @@ static void __init detect_art(void) tsc_async_resets) return; =20 - cpuid(ART_CPUID_LEAF, &art_base_clk.denominator, + cpuid(CPUID_TSC_LEAF, &art_base_clk.denominator, &art_base_clk.numerator, &art_base_clk.freq_khz, &unused); =20 art_base_clk.freq_khz /=3D KHZ; diff -puN drivers/platform/x86/intel/pmc/core.c~tsc-leaf-checks-2 drivers/p= latform/x86/intel/pmc/core.c --- a/drivers/platform/x86/intel/pmc/core.c~tsc-leaf-checks-2 2024-10-30 12= :26:57.614213161 -0700 +++ b/drivers/platform/x86/intel/pmc/core.c 2024-10-30 12:26:57.618213169 -= 0700 @@ -23,6 +23,7 @@ #include #include =20 +#include #include #include #include @@ -936,13 +937,13 @@ static unsigned int pmc_core_get_crystal { unsigned int eax_denominator, ebx_numerator, ecx_hz, edx; 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To: linux-kernel@vger.kernel.org Cc: x86@kernel.org,tglx@linutronix.de,bp@alien8.de,rafael@kernel.org,lenb@kernel.org,Dave Hansen From: Dave Hansen Date: Wed, 30 Oct 2024 14:33:24 -0700 References: <20241030213310.C4861EC0@davehans-spike.ostc.intel.com> In-Reply-To: <20241030213310.C4861EC0@davehans-spike.ostc.intel.com> Message-Id: <20241030213324.3750CF43@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen All the code that reads the CPUID frequency information leaf hard-codes a magic number. Give it a symbolic name and use it. Signed-off-by: Dave Hansen --- b/arch/x86/include/asm/cpuid.h | 1 + b/arch/x86/kernel/tsc.c | 12 ++++++------ 2 files changed, 7 insertions(+), 6 deletions(-) diff -puN arch/x86/include/asm/cpuid.h~tsc-leaf-checks-3 arch/x86/include/a= sm/cpuid.h --- a/arch/x86/include/asm/cpuid.h~tsc-leaf-checks-3 2024-10-30 12:26:58.00= 6213934 -0700 +++ b/arch/x86/include/asm/cpuid.h 2024-10-30 12:26:58.010213943 -0700 @@ -22,6 +22,7 @@ enum cpuid_regs_idx { #define CPUID_MWAIT_LEAF 0x5 #define CPUID_DCA_LEAF 0x9 #define CPUID_TSC_LEAF 0x15 +#define CPUID_FREQ_LEAF 0x16 =20 #ifdef CONFIG_X86_32 extern int have_cpuid_p(void); diff -puN arch/x86/kernel/tsc.c~tsc-leaf-checks-3 arch/x86/kernel/tsc.c --- a/arch/x86/kernel/tsc.c~tsc-leaf-checks-3 2024-10-30 12:26:58.010213943= -0700 +++ b/arch/x86/kernel/tsc.c 2024-10-30 12:26:58.010213943 -0700 @@ -680,8 +680,8 @@ unsigned long native_calibrate_tsc(void) =20 /* * Denverton SoCs don't report crystal clock, and also don't support - * CPUID.0x16 for the calculation below, so hardcode the 25MHz crystal - * clock. + * CPUID_FREQ_LEAF for the calculation below, so hardcode the 25MHz + * crystal clock. */ if (crystal_khz =3D=3D 0 && boot_cpu_data.x86_vfm =3D=3D INTEL_ATOM_GOLDMONT_D) @@ -700,10 +700,10 @@ unsigned long native_calibrate_tsc(void) * clock, but we can easily calculate it to a high degree of accuracy * by considering the crystal ratio and the CPU speed. */ - if (crystal_khz =3D=3D 0 && boot_cpu_data.cpuid_level >=3D 0x16) { + if (crystal_khz =3D=3D 0 && boot_cpu_data.cpuid_level >=3D CPUID_FREQ_LEA= F) { unsigned int eax_base_mhz, ebx, ecx, edx; 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charset="utf-8" From: Dave Hansen Move the XSAVE-related CPUID leaf definitions to common code. Then, use the new definition to remove the last magic number from the CPUID level dependency table. Signed-off-by: Dave Hansen --- b/arch/x86/include/asm/cpuid.h | 2 ++ b/arch/x86/include/asm/fpu/xstate.h | 4 ---- b/arch/x86/kernel/cpu/common.c | 2 +- b/arch/x86/kernel/fpu/xstate.c | 1 + 4 files changed, 4 insertions(+), 5 deletions(-) diff -puN arch/x86/include/asm/cpuid.h~xsave-leaf-checks-1 arch/x86/include= /asm/cpuid.h --- a/arch/x86/include/asm/cpuid.h~xsave-leaf-checks-1 2024-10-30 12:26:58.= 406214724 -0700 +++ b/arch/x86/include/asm/cpuid.h 2024-10-30 12:26:58.414214739 -0700 @@ -21,8 +21,10 @@ enum cpuid_regs_idx { =20 #define CPUID_MWAIT_LEAF 0x5 #define CPUID_DCA_LEAF 0x9 +#define XSTATE_CPUID 0x0d #define CPUID_TSC_LEAF 0x15 #define CPUID_FREQ_LEAF 0x16 +#define TILE_CPUID 0x1d =20 #ifdef CONFIG_X86_32 extern int have_cpuid_p(void); diff -puN arch/x86/include/asm/fpu/xstate.h~xsave-leaf-checks-1 arch/x86/in= clude/asm/fpu/xstate.h --- a/arch/x86/include/asm/fpu/xstate.h~xsave-leaf-checks-1 2024-10-30 12:2= 6:58.410214731 -0700 +++ b/arch/x86/include/asm/fpu/xstate.h 2024-10-30 12:26:58.414214739 -0700 @@ -12,10 +12,6 @@ /* Bit 63 of XCR0 is reserved for future expansion */ #define XFEATURE_MASK_EXTEND (~(XFEATURE_MASK_FPSSE | (1ULL << 63))) =20 -#define XSTATE_CPUID 0x0000000d - -#define TILE_CPUID 0x0000001d - #define FXSAVE_SIZE 512 =20 #define XSAVE_HDR_SIZE 64 diff -puN arch/x86/kernel/cpu/common.c~xsave-leaf-checks-1 arch/x86/kernel/= cpu/common.c --- a/arch/x86/kernel/cpu/common.c~xsave-leaf-checks-1 2024-10-30 12:26:58.= 410214731 -0700 +++ b/arch/x86/kernel/cpu/common.c 2024-10-30 12:26:58.414214739 -0700 @@ -639,7 +639,7 @@ static const struct cpuid_dependent_feat cpuid_dependent_features[] =3D { { X86_FEATURE_MWAIT, CPUID_MWAIT_LEAF }, { X86_FEATURE_DCA, CPUID_DCA_LEAF }, - { X86_FEATURE_XSAVE, 0x0000000d }, + { X86_FEATURE_XSAVE, XSTATE_CPUID }, { 0, 0 } }; =20 diff -puN arch/x86/kernel/fpu/xstate.c~xsave-leaf-checks-1 arch/x86/kernel/= fpu/xstate.c --- a/arch/x86/kernel/fpu/xstate.c~xsave-leaf-checks-1 2024-10-30 12:26:58.= 410214731 -0700 +++ b/arch/x86/kernel/fpu/xstate.c 2024-10-30 12:26:58.414214739 -0700 @@ -20,6 +20,7 @@ #include #include =20 +#include #include #include #include _ From nobody Mon Nov 25 02:02:23 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B072219CBF for ; Wed, 30 Oct 2024 21:33:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730324009; cv=none; b=bN/ty60AUp6q0teR3oQb5ZdgH5KqZuRewLIOt//gkmk2EROJJfVCAt3oRR4RoVSSL0IK6enTHTSLqn8LYcxm7W5yP4KqaEK5e3X7E+5aEXnTPZKKXdsDN5I6zaHfDGD3FzG/2AALaxfNbKWqs3aKSHEP8g05KGj/ldVZ38R19mw= ARC-Message-Signature: i=1; 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d="scan'208";a="83257723" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by orviesa008.jf.intel.com with ESMTP; 30 Oct 2024 14:33:28 -0700 Subject: [PATCH 10/11] x86/fpu: Remove unnecessary CPUID level check To: linux-kernel@vger.kernel.org Cc: x86@kernel.org,tglx@linutronix.de,bp@alien8.de,rafael@kernel.org,lenb@kernel.org,Dave Hansen From: Dave Hansen Date: Wed, 30 Oct 2024 14:33:27 -0700 References: <20241030213310.C4861EC0@davehans-spike.ostc.intel.com> In-Reply-To: <20241030213310.C4861EC0@davehans-spike.ostc.intel.com> Message-Id: <20241030213327.E04359C9@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen The CPUID level dependency table will entirely zap X86_FEATURE_XSAVE if the CPUID level is too low. This code is unreachable. Kill it. Signed-off-by: Dave Hansen --- b/arch/x86/kernel/fpu/xstate.c | 5 ----- 1 file changed, 5 deletions(-) diff -puN arch/x86/kernel/fpu/xstate.c~xsave-leaf-checks-2 arch/x86/kernel/= fpu/xstate.c --- a/arch/x86/kernel/fpu/xstate.c~xsave-leaf-checks-2 2024-10-30 12:26:58.= 838215576 -0700 +++ b/arch/x86/kernel/fpu/xstate.c 2024-10-30 12:26:58.842215584 -0700 @@ -764,11 +764,6 @@ void __init fpu__init_system_xstate(unsi return; } =20 - if (boot_cpu_data.cpuid_level < XSTATE_CPUID) { - WARN_ON_FPU(1); - return; - } - /* * Find user xstates supported by the processor. */ _ From nobody Mon Nov 25 02:02:23 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DAB121FD96 for ; Wed, 30 Oct 2024 21:33:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730324012; cv=none; b=HDksGubYpiPmkkX2Qyw8wAA0tgJP99jRGVOcLpwV6esw2S5evZNXfjLQ+kTpEkIL5F1txyLcggt1g+QCDtmm85Zl+a6TYUoul4+IZxfiQUE4S4c7k2x/YGIQvNa3izLuZoqm0sX5FBJ4/b9m6roPfK6+NPqOv3N3/FGMweEeTAA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730324012; c=relaxed/simple; bh=zDobnNZLKeCkWUADamBzKcMCAACutAY/GmYqtjmS7Xo=; h=Subject:To:Cc:From:Date:References:In-Reply-To:Message-Id; b=kaO1yj09bh2Hf04sSYhZVSCRcVYD+/4HVzqoTSUMnaCyhH9DupbQU6M0ywnatFiDU4T9jERcMjOIUQ3ZW2A+YODpaR5Zms4AY/WkWLWIkXPaVUpew2VJmC/BlpTVrB3jocAuOwcanZR9kR9k4i6ji/xb3d5vaIjKt76mQegcc0k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YvFgRDHc; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YvFgRDHc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730324010; x=1761860010; h=subject:to:cc:from:date:references:in-reply-to: message-id; bh=zDobnNZLKeCkWUADamBzKcMCAACutAY/GmYqtjmS7Xo=; b=YvFgRDHcCqZB2bI5Q8a57c+dC9LbJLI+HgHiKvxKrmFC2rd+x9v/pj5+ 87bB//bidJOqXgO+8+YzYqS4qyCK2Y/MRSwCwjbjVgEjkDkITV4iI6dF4 qLekerCY1ItNpjhfEoLfW+iCwO5dZ9CnNX9QBks9r8sYDhIEG/1DxHg2Y LdbeDIdmUf9IaIKhgR3X7R+NHHHvzLVWjYYyEjgPx2DpM0TWXEpfV+9bS fJMA4gqQfCXCPeLPQY9/C/MJSdeKz8l8upnR8sjrZN24YD/6wmSFkhi36 9z3nGOCv/cjYIPVpL4myews1lIjuA8QouO7xauTxOnQTZ6uUTFfs5HHqs w==; X-CSE-ConnectionGUID: bc1EfdPfQGmTAR0ihm3ZyA== X-CSE-MsgGUID: u39DXULTQY6ro0qUt0Bxrg== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="33741656" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="33741656" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2024 14:33:30 -0700 X-CSE-ConnectionGUID: EFqCcN62SdaMtwhbFszMQw== X-CSE-MsgGUID: A0RE+wMvSNmOl1Jq/ngUWw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="83257726" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by orviesa008.jf.intel.com with ESMTP; 30 Oct 2024 14:33:30 -0700 Subject: [PATCH 11/11] x86/cpu: Make all all CPUID leaf names consistent To: linux-kernel@vger.kernel.org Cc: x86@kernel.org,tglx@linutronix.de,bp@alien8.de,rafael@kernel.org,lenb@kernel.org,Dave Hansen From: Dave Hansen Date: Wed, 30 Oct 2024 14:33:29 -0700 References: <20241030213310.C4861EC0@davehans-spike.ostc.intel.com> In-Reply-To: <20241030213310.C4861EC0@davehans-spike.ostc.intel.com> Message-Id: <20241030213329.3253F5F3@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen The leaf names are not consistent. Give them all a CPUID_LEAF_ prefix for consistency and vertical alignment. Signed-off-by: Dave Hansen --- b/arch/x86/events/intel/pt.c | 4 ++-- b/arch/x86/include/asm/cpuid.h | 12 ++++++------ b/arch/x86/kernel/acpi/cstate.c | 2 +- b/arch/x86/kernel/cpu/common.c | 6 +++--- b/arch/x86/kernel/fpu/xstate.c | 20 ++++++++++---------- b/arch/x86/kernel/hpet.c | 2 +- b/arch/x86/kernel/process.c | 2 +- b/arch/x86/kernel/smpboot.c | 2 +- b/arch/x86/kernel/tsc.c | 18 +++++++++--------- b/arch/x86/xen/enlighten_pv.c | 4 ++-- b/drivers/acpi/acpi_pad.c | 2 +- b/drivers/dma/ioat/dca.c | 2 +- b/drivers/idle/intel_idle.c | 2 +- b/drivers/platform/x86/intel/pmc/core.c | 4 ++-- 14 files changed, 41 insertions(+), 41 deletions(-) diff -puN arch/x86/events/intel/pt.c~xsave-leaf-checks-3 arch/x86/events/in= tel/pt.c --- a/arch/x86/events/intel/pt.c~xsave-leaf-checks-3 2024-10-30 12:26:59.21= 8216325 -0700 +++ b/arch/x86/events/intel/pt.c 2024-10-30 12:26:59.238216364 -0700 @@ -202,10 +202,10 @@ static int __init pt_pmu_hw_init(void) * otherwise, zero for numerator stands for "not enumerated" * as per SDM */ - if (boot_cpu_data.cpuid_level >=3D CPUID_TSC_LEAF) { + if (boot_cpu_data.cpuid_level >=3D CPUID_LEAF_TSC) { u32 eax, ebx, ecx, edx; =20 - cpuid(CPUID_TSC_LEAF, &eax, &ebx, &ecx, &edx); + cpuid(CPUID_LEAF_TSC, &eax, &ebx, &ecx, &edx); =20 pt_pmu.tsc_art_num =3D ebx; pt_pmu.tsc_art_den =3D eax; diff -puN arch/x86/include/asm/cpuid.h~xsave-leaf-checks-3 arch/x86/include= /asm/cpuid.h --- a/arch/x86/include/asm/cpuid.h~xsave-leaf-checks-3 2024-10-30 12:26:59.= 222216332 -0700 +++ b/arch/x86/include/asm/cpuid.h 2024-10-30 12:26:59.238216364 -0700 @@ -19,12 +19,12 @@ enum cpuid_regs_idx { CPUID_EDX, }; =20 -#define CPUID_MWAIT_LEAF 0x5 -#define CPUID_DCA_LEAF 0x9 -#define XSTATE_CPUID 0x0d -#define CPUID_TSC_LEAF 0x15 -#define CPUID_FREQ_LEAF 0x16 -#define TILE_CPUID 0x1d +#define CPUID_LEAF_MWAIT 0x5 +#define CPUID_LEAF_DCA 0x9 +#define CPUID_LEAF_XSTATE 0x0d +#define CPUID_LEAF_TSC 0x15 +#define CPUID_LEAF_FREQ 0x16 +#define CPUID_LEAF_TILE 0x1d =20 #ifdef CONFIG_X86_32 extern int have_cpuid_p(void); diff -puN arch/x86/kernel/acpi/cstate.c~xsave-leaf-checks-3 arch/x86/kernel= /acpi/cstate.c --- a/arch/x86/kernel/acpi/cstate.c~xsave-leaf-checks-3 2024-10-30 12:26:59= .222216332 -0700 +++ b/arch/x86/kernel/acpi/cstate.c 2024-10-30 12:26:59.238216364 -0700 @@ -129,7 +129,7 @@ static long acpi_processor_ffh_cstate_pr unsigned int cstate_type; /* C-state type and not ACPI C-state type */ unsigned int num_cstate_subtype; =20 - cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx); + cpuid(CPUID_LEAF_MWAIT, &eax, &ebx, &ecx, &edx); =20 /* Check whether this particular cx_type (in CST) is supported or not */ cstate_type =3D (((cx->address >> MWAIT_SUBSTATE_SIZE) & diff -puN arch/x86/kernel/cpu/common.c~xsave-leaf-checks-3 arch/x86/kernel/= cpu/common.c --- a/arch/x86/kernel/cpu/common.c~xsave-leaf-checks-3 2024-10-30 12:26:59.= 222216332 -0700 +++ b/arch/x86/kernel/cpu/common.c 2024-10-30 12:26:59.238216364 -0700 @@ -637,9 +637,9 @@ struct cpuid_dependent_feature { =20 static const struct cpuid_dependent_feature cpuid_dependent_features[] =3D { - { X86_FEATURE_MWAIT, CPUID_MWAIT_LEAF }, - { X86_FEATURE_DCA, CPUID_DCA_LEAF }, - { X86_FEATURE_XSAVE, XSTATE_CPUID }, + { X86_FEATURE_MWAIT, CPUID_LEAF_MWAIT }, + { X86_FEATURE_DCA, CPUID_LEAF_DCA }, + { X86_FEATURE_XSAVE, CPUID_LEAF_XSTATE }, { 0, 0 } }; =20 diff -puN arch/x86/kernel/fpu/xstate.c~xsave-leaf-checks-3 arch/x86/kernel/= fpu/xstate.c --- a/arch/x86/kernel/fpu/xstate.c~xsave-leaf-checks-3 2024-10-30 12:26:59.= 226216341 -0700 +++ b/arch/x86/kernel/fpu/xstate.c 2024-10-30 12:26:59.238216364 -0700 @@ -233,7 +233,7 @@ static void __init setup_xstate_cache(vo xmm_space); =20 for_each_extended_xfeature(i, fpu_kernel_cfg.max_features) { - cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx); + cpuid_count(CPUID_LEAF_XSTATE, i, &eax, &ebx, &ecx, &edx); =20 xstate_sizes[i] =3D eax; xstate_flags[i] =3D ecx; @@ -399,7 +399,7 @@ int xfeature_size(int xfeature_nr) u32 eax, ebx, ecx, edx; =20 CHECK_XFEATURE(xfeature_nr); - cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx); + cpuid_count(CPUID_LEAF_XSTATE, xfeature_nr, &eax, &ebx, &ecx, &edx); return eax; } =20 @@ -442,9 +442,9 @@ static void __init __xstate_dump_leaves( * just in case there are some goodies up there */ for (i =3D 0; i < XFEATURE_MAX + 10; i++) { - cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx); + cpuid_count(CPUID_LEAF_XSTATE, i, &eax, &ebx, &ecx, &edx); pr_warn("CPUID[%02x, %02x]: eax=3D%08x ebx=3D%08x ecx=3D%08x edx=3D%08x\= n", - XSTATE_CPUID, i, eax, ebx, ecx, edx); + CPUID_LEAF_XSTATE, i, eax, ebx, ecx, edx); } } =20 @@ -485,7 +485,7 @@ static int __init check_xtile_data_again * Check the maximum palette id: * eax: the highest numbered palette subleaf. */ - cpuid_count(TILE_CPUID, 0, &max_palid, &ebx, &ecx, &edx); + cpuid_count(CPUID_LEAF_TILE, 0, &max_palid, &ebx, &ecx, &edx); =20 /* * Cross-check each tile size and find the maximum number of @@ -499,7 +499,7 @@ static int __init check_xtile_data_again * eax[31:16]: bytes per title * ebx[31:16]: the max names (or max number of tiles) */ - cpuid_count(TILE_CPUID, palid, &eax, &ebx, &edx, &edx); + cpuid_count(CPUID_LEAF_TILE, palid, &eax, &ebx, &edx, &edx); tile_size =3D eax >> 16; max =3D ebx >> 16; =20 @@ -634,7 +634,7 @@ static unsigned int __init get_compacted * are no supervisor states, but XSAVEC still uses compacted * format. */ - cpuid_count(XSTATE_CPUID, 1, &eax, &ebx, &ecx, &edx); + cpuid_count(CPUID_LEAF_XSTATE, 1, &eax, &ebx, &ecx, &edx); return ebx; } =20 @@ -675,7 +675,7 @@ static unsigned int __init get_xsave_siz * containing all the *user* state components * corresponding to bits currently set in XCR0. */ - cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); + cpuid_count(CPUID_LEAF_XSTATE, 0, &eax, &ebx, &ecx, &edx); return ebx; } =20 @@ -767,13 +767,13 @@ void __init fpu__init_system_xstate(unsi /* * Find user xstates supported by the processor. */ - cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); + cpuid_count(CPUID_LEAF_XSTATE, 0, &eax, &ebx, &ecx, &edx); fpu_kernel_cfg.max_features =3D eax + ((u64)edx << 32); =20 /* * Find supervisor xstates supported by the processor. */ - cpuid_count(XSTATE_CPUID, 1, &eax, &ebx, &ecx, &edx); + cpuid_count(CPUID_LEAF_XSTATE, 1, &eax, &ebx, &ecx, &edx); fpu_kernel_cfg.max_features |=3D ecx + ((u64)edx << 32); =20 if ((fpu_kernel_cfg.max_features & XFEATURE_MASK_FPSSE) !=3D XFEATURE_MAS= K_FPSSE) { diff -puN arch/x86/kernel/hpet.c~xsave-leaf-checks-3 arch/x86/kernel/hpet.c --- a/arch/x86/kernel/hpet.c~xsave-leaf-checks-3 2024-10-30 12:26:59.226216= 341 -0700 +++ b/arch/x86/kernel/hpet.c 2024-10-30 12:26:59.238216364 -0700 @@ -928,7 +928,7 @@ static bool __init mwait_pc10_supported( if (!cpu_feature_enabled(X86_FEATURE_MWAIT)) return false; =20 - cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates); + cpuid(CPUID_LEAF_MWAIT, &eax, &ebx, &ecx, &mwait_substates); =20 return (ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) && (ecx & CPUID5_ECX_INTERRUPT_BREAK) && diff -puN arch/x86/kernel/process.c~xsave-leaf-checks-3 arch/x86/kernel/pro= cess.c --- a/arch/x86/kernel/process.c~xsave-leaf-checks-3 2024-10-30 12:26:59.226= 216341 -0700 +++ b/arch/x86/kernel/process.c 2024-10-30 12:26:59.238216364 -0700 @@ -878,7 +878,7 @@ static __init bool prefer_mwait_c1_over_ if (boot_cpu_has_bug(X86_BUG_MONITOR) || boot_cpu_has_bug(X86_BUG_AMD_API= C_C1E)) return false; =20 - cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx); + cpuid(CPUID_LEAF_MWAIT, &eax, &ebx, &ecx, &edx); =20 /* * If MWAIT extensions are not available, it is safe to use MWAIT diff -puN arch/x86/kernel/smpboot.c~xsave-leaf-checks-3 arch/x86/kernel/smp= boot.c --- a/arch/x86/kernel/smpboot.c~xsave-leaf-checks-3 2024-10-30 12:26:59.226= 216341 -0700 +++ b/arch/x86/kernel/smpboot.c 2024-10-30 12:26:59.238216364 -0700 @@ -1292,7 +1292,7 @@ static inline void mwait_play_dead(void) if (!this_cpu_has(X86_FEATURE_CLFLUSH)) return; =20 - eax =3D CPUID_MWAIT_LEAF; + eax =3D CPUID_LEAF_MWAIT; ecx =3D 0; native_cpuid(&eax, &ebx, &ecx, &edx); =20 diff -puN arch/x86/kernel/tsc.c~xsave-leaf-checks-3 arch/x86/kernel/tsc.c --- a/arch/x86/kernel/tsc.c~xsave-leaf-checks-3 2024-10-30 12:26:59.2302163= 49 -0700 +++ b/arch/x86/kernel/tsc.c 2024-10-30 12:26:59.238216364 -0700 @@ -665,13 +665,13 @@ unsigned long native_calibrate_tsc(void) if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL) return 0; =20 - if (boot_cpu_data.cpuid_level < CPUID_TSC_LEAF) + if (boot_cpu_data.cpuid_level < CPUID_LEAF_TSC) return 0; =20 eax_denominator =3D ebx_numerator =3D ecx_hz =3D edx =3D 0; =20 /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ - cpuid(CPUID_TSC_LEAF, &eax_denominator, &ebx_numerator, &ecx_hz, &edx); + cpuid(CPUID_LEAF_TSC, &eax_denominator, &ebx_numerator, &ecx_hz, &edx); =20 if (ebx_numerator =3D=3D 0 || eax_denominator =3D=3D 0) return 0; @@ -680,7 +680,7 @@ unsigned long native_calibrate_tsc(void) =20 /* * Denverton SoCs don't report crystal clock, and also don't support - * CPUID_FREQ_LEAF for the calculation below, so hardcode the 25MHz + * CPUID_LEAF_FREQ for the calculation below, so hardcode the 25MHz * crystal clock. */ if (crystal_khz =3D=3D 0 && @@ -700,10 +700,10 @@ unsigned long native_calibrate_tsc(void) * clock, but we can easily calculate it to a high degree of accuracy * by considering the crystal ratio and the CPU speed. */ - if (crystal_khz =3D=3D 0 && boot_cpu_data.cpuid_level >=3D CPUID_FREQ_LEA= F) { + if (crystal_khz =3D=3D 0 && boot_cpu_data.cpuid_level >=3D CPUID_LEAF_FRE= Q) { unsigned int eax_base_mhz, ebx, ecx, edx; =20 - cpuid(CPUID_FREQ_LEAF, &eax_base_mhz, &ebx, &ecx, &edx); + cpuid(CPUID_LEAF_FREQ, &eax_base_mhz, &ebx, &ecx, &edx); crystal_khz =3D eax_base_mhz * 1000 * eax_denominator / ebx_numerator; } @@ -738,12 +738,12 @@ static unsigned long cpu_khz_from_cpuid( if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL) return 0; =20 - if (boot_cpu_data.cpuid_level < CPUID_FREQ_LEAF) + if (boot_cpu_data.cpuid_level < CPUID_LEAF_FREQ) return 0; =20 eax_base_mhz =3D ebx_max_mhz =3D ecx_bus_mhz =3D edx =3D 0; =20 - cpuid(CPUID_FREQ_LEAF, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx); + cpuid(CPUID_LEAF_FREQ, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx); =20 return eax_base_mhz * 1000; } @@ -1076,7 +1076,7 @@ static void __init detect_art(void) { unsigned int unused; =20 - if (boot_cpu_data.cpuid_level < CPUID_TSC_LEAF) + if (boot_cpu_data.cpuid_level < CPUID_LEAF_TSC) return; =20 /* @@ -1089,7 +1089,7 @@ static void __init detect_art(void) tsc_async_resets) return; =20 - cpuid(CPUID_TSC_LEAF, &art_base_clk.denominator, + cpuid(CPUID_LEAF_TSC, &art_base_clk.denominator, &art_base_clk.numerator, &art_base_clk.freq_khz, &unused); =20 art_base_clk.freq_khz /=3D KHZ; diff -puN arch/x86/xen/enlighten_pv.c~xsave-leaf-checks-3 arch/x86/xen/enli= ghten_pv.c --- a/arch/x86/xen/enlighten_pv.c~xsave-leaf-checks-3 2024-10-30 12:26:59.2= 30216349 -0700 +++ b/arch/x86/xen/enlighten_pv.c 2024-10-30 12:26:59.238216364 -0700 @@ -231,7 +231,7 @@ static void xen_cpuid(unsigned int *ax, or_ebx =3D smp_processor_id() << 24; break; =20 - case CPUID_MWAIT_LEAF: + case CPUID_LEAF_MWAIT: /* Synthesize the values.. */ *ax =3D 0; *bx =3D 0; @@ -301,7 +301,7 @@ static bool __init xen_check_mwait(void) * ecx and edx. The hypercall provides only partial information. */ =20 - ax =3D CPUID_MWAIT_LEAF; + ax =3D CPUID_LEAF_MWAIT; bx =3D 0; cx =3D 0; dx =3D 0; diff -puN drivers/acpi/acpi_pad.c~xsave-leaf-checks-3 drivers/acpi/acpi_pad= .c --- a/drivers/acpi/acpi_pad.c~xsave-leaf-checks-3 2024-10-30 12:26:59.23021= 6349 -0700 +++ b/drivers/acpi/acpi_pad.c 2024-10-30 12:26:59.238216364 -0700 @@ -48,7 +48,7 @@ static void power_saving_mwait_init(void if (!boot_cpu_has(X86_FEATURE_MWAIT)) return; =20 - cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx); + cpuid(CPUID_LEAF_MWAIT, &eax, &ebx, &ecx, &edx); =20 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) || !(ecx & CPUID5_ECX_INTERRUPT_BREAK)) diff -puN drivers/dma/ioat/dca.c~xsave-leaf-checks-3 drivers/dma/ioat/dca.c --- a/drivers/dma/ioat/dca.c~xsave-leaf-checks-3 2024-10-30 12:26:59.234216= 356 -0700 +++ b/drivers/dma/ioat/dca.c 2024-10-30 12:26:59.238216364 -0700 @@ -63,7 +63,7 @@ static int dca_enabled_in_bios(struct pc u32 eax; int res; =20 - eax =3D cpuid_eax(CPUID_DCA_LEAF); + eax =3D cpuid_eax(CPUID_LEAF_DCA); res =3D eax & BIT(0); if (!res) dev_dbg(&pdev->dev, "DCA is disabled in BIOS\n"); diff -puN drivers/idle/intel_idle.c~xsave-leaf-checks-3 drivers/idle/intel_= idle.c --- a/drivers/idle/intel_idle.c~xsave-leaf-checks-3 2024-10-30 12:26:59.234= 216356 -0700 +++ b/drivers/idle/intel_idle.c 2024-10-30 12:26:59.242216372 -0700 @@ -2269,7 +2269,7 @@ static int __init intel_idle_init(void) return -ENODEV; } =20 - cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates); + cpuid(CPUID_LEAF_MWAIT, &eax, &ebx, &ecx, &mwait_substates); =20 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) || !(ecx & CPUID5_ECX_INTERRUPT_BREAK) || diff -puN drivers/platform/x86/intel/pmc/core.c~xsave-leaf-checks-3 drivers= /platform/x86/intel/pmc/core.c --- a/drivers/platform/x86/intel/pmc/core.c~xsave-leaf-checks-3 2024-10-30 = 12:26:59.234216356 -0700 +++ b/drivers/platform/x86/intel/pmc/core.c 2024-10-30 12:26:59.242216372 -= 0700 @@ -937,13 +937,13 @@ static unsigned int pmc_core_get_crystal { unsigned int eax_denominator, ebx_numerator, ecx_hz, edx; =20 - if (boot_cpu_data.cpuid_level < CPUID_TSC_LEAF) + if (boot_cpu_data.cpuid_level < CPUID_LEAF_TSC) return 0; =20 eax_denominator =3D ebx_numerator =3D ecx_hz =3D edx =3D 0; =20 /* TSC/Crystal ratio, plus optionally Crystal Hz */ - cpuid(CPUID_TSC_LEAF, &eax_denominator, &ebx_numerator, &ecx_hz, &edx); + cpuid(CPUID_LEAF_TSC, &eax_denominator, &ebx_numerator, &ecx_hz, &edx); =20 if (ebx_numerator =3D=3D 0 || eax_denominator =3D=3D 0) return 0; _