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Signed-off-by: Sibi Sankar --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index f70a7e00ed50..be93e482bb28 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5786,6 +5786,13 @@ gic_its: msi-controller@17040000 { }; }; =20 + cpucp_mbox: mailbox@17430000 { + compatible =3D "qcom,x1e80100-cpucp-mbox"; + reg =3D <0 0x17430000 0 0x10000>, <0 0x18830000 0 0x10000>; + interrupts =3D ; + #mbox-cells =3D <1>; + }; + apps_rsc: rsc@17500000 { compatible =3D "qcom,rpmh-rsc"; reg =3D <0 0x17500000 0 0x10000>, @@ -5969,6 +5976,25 @@ frame@1780d000 { }; }; =20 + sram: sram@18b4e000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0x18b4e000 0x0 0x400>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x18b4e000 0x400>; + + cpu_scp_lpri0: scp-sram-section@0 { + compatible =3D "arm,scmi-shmem"; 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charset="utf-8" Enable cpufreq on X1E80100 SoCs through the SCMI perf protocol node. Signed-off-by: Sibi Sankar --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 63 ++++++++++++++++---------- 1 file changed, 39 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index be93e482bb28..9c6d223b1b60 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -71,8 +71,8 @@ cpu0: cpu@0 { reg =3D <0x0 0x0>; enable-method =3D "psci"; next-level-cache =3D <&l2_0>; - power-domains =3D <&cpu_pd0>; - power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd0>, <&scmi_dvfs 0>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&cluster_c4>; =20 l2_0: l2-cache { @@ -88,8 +88,8 @@ cpu1: cpu@100 { reg =3D <0x0 0x100>; enable-method =3D "psci"; next-level-cache =3D <&l2_0>; - power-domains =3D <&cpu_pd1>; - power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd1>, <&scmi_dvfs 0>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&cluster_c4>; }; =20 @@ -99,8 +99,8 @@ cpu2: cpu@200 { reg =3D <0x0 0x200>; enable-method =3D "psci"; next-level-cache =3D <&l2_0>; - power-domains =3D <&cpu_pd2>; - power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd2>, <&scmi_dvfs 0>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&cluster_c4>; }; =20 @@ -110,8 +110,8 @@ cpu3: cpu@300 { reg =3D <0x0 0x300>; enable-method =3D "psci"; next-level-cache =3D <&l2_0>; - power-domains =3D <&cpu_pd3>; - power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd3>, <&scmi_dvfs 0>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&cluster_c4>; }; =20 @@ -121,8 +121,8 @@ cpu4: cpu@10000 { reg =3D <0x0 0x10000>; enable-method =3D "psci"; next-level-cache =3D <&l2_1>; - power-domains =3D <&cpu_pd4>; - power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd4>, <&scmi_dvfs 1>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&cluster_c4>; =20 l2_1: l2-cache { @@ -138,8 +138,8 @@ cpu5: cpu@10100 { reg =3D <0x0 0x10100>; enable-method =3D "psci"; next-level-cache =3D <&l2_1>; - power-domains =3D <&cpu_pd5>; - power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd5>, <&scmi_dvfs 1>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&cluster_c4>; }; =20 @@ -149,8 +149,8 @@ cpu6: cpu@10200 { reg =3D <0x0 0x10200>; enable-method =3D "psci"; next-level-cache =3D <&l2_1>; - power-domains =3D <&cpu_pd6>; - power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd6>, <&scmi_dvfs 1>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&cluster_c4>; }; =20 @@ -160,8 +160,8 @@ cpu7: cpu@10300 { reg =3D <0x0 0x10300>; enable-method =3D "psci"; next-level-cache =3D <&l2_1>; - power-domains =3D <&cpu_pd7>; - power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd7>, <&scmi_dvfs 1>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&cluster_c4>; }; =20 @@ -171,8 +171,8 @@ cpu8: cpu@20000 { reg =3D <0x0 0x20000>; enable-method =3D "psci"; next-level-cache =3D <&l2_2>; - power-domains =3D <&cpu_pd8>; - power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd8>, <&scmi_dvfs 2>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&cluster_c4>; =20 l2_2: l2-cache { @@ -188,8 +188,8 @@ cpu9: cpu@20100 { reg =3D <0x0 0x20100>; enable-method =3D "psci"; next-level-cache =3D <&l2_2>; - power-domains =3D <&cpu_pd9>; - power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd9>, <&scmi_dvfs 2>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&cluster_c4>; }; =20 @@ -199,8 +199,8 @@ cpu10: cpu@20200 { reg =3D <0x0 0x20200>; enable-method =3D "psci"; next-level-cache =3D <&l2_2>; - power-domains =3D <&cpu_pd10>; - power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd10>, <&scmi_dvfs 2>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&cluster_c4>; }; =20 @@ -210,8 +210,8 @@ cpu11: cpu@20300 { reg =3D <0x0 0x20300>; enable-method =3D "psci"; next-level-cache =3D <&l2_2>; - power-domains =3D <&cpu_pd11>; - power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd11>, <&scmi_dvfs 2>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&cluster_c4>; }; =20 @@ -310,6 +310,21 @@ scm: scm { &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; qcom,dload-mode =3D <&tcsr 0x19000>; }; + + scmi { + compatible =3D "arm,scmi"; + mboxes =3D <&cpucp_mbox 0>, <&cpucp_mbox 2>; + mbox-names =3D "tx", "rx"; + shmem =3D <&cpu_scp_lpri0>, <&cpu_scp_lpri1>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + }; }; =20 clk_virt: interconnect-0 { --=20 2.34.1