From nobody Mon Nov 25 05:23:43 2024 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EC961EBFEB for ; Wed, 30 Oct 2024 12:54:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730292901; cv=none; b=f8xmP6pKLKujYKUaEc3aZr9QD6NU0ctSHZdxw2YJxFiHSS1sCv29WQgBlscwqxKReXrrcwZyAkJjn6Z5HlNOMCOcZTdd8kvD90Fai0kcLGGVFG2Q1FTAAsbC/IGMqxz/rK0AJgy8JpdMHbgSAxaoNP2LV5y41+8xw0tGrHZNjBA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730292901; c=relaxed/simple; bh=rKWlxDLz7pe3BUW6FOR9ArzGJ3D+v8hec/Oa2JWjlNk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hUvwQG10zid1hCY3niVrnLZdtSzBapDL4+EQisiVAm5/PzmP45mdmQn2JM6IjNeXJP2Q4eVQ+s0rcnLov+fpt0DoUFwWKvB2J3R4UUPGFIK0bT7X7YnUrWFFdWycGCp/MqG6Xe/kRBz2TK1tR64S7/lrL4GbB5cRXKvfPZLeS1Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.187 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.162.254]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4Xdn9H0YsvzyV2h; Wed, 30 Oct 2024 20:53:07 +0800 (CST) Received: from kwepemd200014.china.huawei.com (unknown [7.221.188.8]) by mail.maildlp.com (Postfix) with ESMTPS id 42D2218010F; Wed, 30 Oct 2024 20:54:46 +0800 (CST) Received: from localhost.localdomain (10.50.165.33) by kwepemd200014.china.huawei.com (7.221.188.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.34; Wed, 30 Oct 2024 20:54:45 +0800 From: Yicong Yang To: , , , , , , , , , , , CC: , , , , , , , , , , , , Subject: [PATCH v7 2/4] arch_topology: Support SMT control for OF based system Date: Wed, 30 Oct 2024 20:54:13 +0800 Message-ID: <20241030125415.18994-3-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20241030125415.18994-1-yangyicong@huawei.com> References: <20241030125415.18994-1-yangyicong@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To kwepemd200014.china.huawei.com (7.221.188.8) Content-Type: text/plain; charset="utf-8" From: Yicong Yang On building the topology from the devicetree, we've already gotten the SMT thread number of each core. Update the largest SMT thread number and enable the SMT control by the end of topology parsing. The core's SMT control provides two interface to the users [1]: 1) enable/disable SMT by writing on/off 2) enable/disable SMT by writing thread number 1/max_thread_number If a system have more than one SMT thread number the 2) may not handle it well, since there're multiple thread numbers in the system and 2) only accept 1/max_thread_number. So issue a warning to notify the users if such system detected. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree= /Documentation/ABI/testing/sysfs-devices-system-cpu#n542 Signed-off-by: Yicong Yang --- drivers/base/arch_topology.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c index 75fcb75d5515..e2c8e6d92414 100644 --- a/drivers/base/arch_topology.c +++ b/drivers/base/arch_topology.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -502,6 +503,10 @@ core_initcall(free_raw_capacity); #endif =20 #if defined(CONFIG_ARM64) || defined(CONFIG_RISCV) + +/* Maximum SMT thread number detected used to enable the SMT control */ +static unsigned int max_smt_thread_num; + /* * This function returns the logic cpu number of the node. * There are basically three kinds of return values: @@ -561,6 +566,17 @@ static int __init parse_core(struct device_node *core,= int package_id, i++; } while (1); =20 + /* + * If max_smt_thread_num has been initialized and doesn't match + * the thread number of this entry, then the system has + * heterogeneous SMT topology. + */ + if (max_smt_thread_num && max_smt_thread_num !=3D i) + pr_warn_once("Heterogeneous SMT topology is partly supported by SMT cont= rol\n"); + + if (max_smt_thread_num < i) + max_smt_thread_num =3D i; + cpu =3D get_cpu_for_node(core); if (cpu >=3D 0) { if (!leaf) { @@ -673,6 +689,14 @@ static int __init parse_socket(struct device_node *soc= ket) if (!has_socket) ret =3D parse_cluster(socket, 0, -1, 0); =20 + /* + * Notify the CPU framework of the SMT support. A thread number of 1 + * can be handled by the framework so we don't need to check + * max_smt_thread_num to see we support SMT or not. + */ + if (max_smt_thread_num) + cpu_smt_set_num_threads(max_smt_thread_num, max_smt_thread_num); + return ret; } =20 --=20 2.24.0