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([82.78.167.190]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-431bd99edebsm17956935e9.45.2024.10.30.04.01.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Oct 2024 04:01:46 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v5 06/10] arm64: dts: renesas: r9a08g045: Add VBATTB node Date: Wed, 30 Oct 2024 13:01:16 +0200 Message-Id: <20241030110120.332802-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241030110120.332802-1-claudiu.beznea.uj@bp.renesas.com> References: <20241030110120.332802-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add the DT node for the VBATTB IP along with DT bindings for the clock it provides. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v5: - dropped the status =3D "disabled"; for the vbattb-xtal node Changes in v4: - used clock-controller for the vbattb node name - move the node near scif0 for ordering - set the vbattb_xtal status as disabled to avoid having it exported in linux with frequency =3D 0 in boards that don't use it - collected tags Changes in v3: - dropped the child nodes of vbattb; along with this dropped ranges, interrupt-names, #address-cells, #size-cells - added vbattb_xtal as input clock for vbattb Changes in v2: - update compatibles - updated clocks and clock-names for clock-controller node - removed the power domain from the clock-controller as this is controlled by parent node in v2 arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g045.dtsi index 067a26a66c24..a1d5084b074a 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -72,6 +72,18 @@ scif0: serial@1004b800 { status =3D "disabled"; }; =20 + vbattb: clock-controller@1005c000 { + compatible =3D "renesas,r9a08g045-vbattb"; + reg =3D <0 0x1005c000 0 0x1000>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; + clock-names =3D "bclk", "rtx"; + #clock-cells =3D <1>; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A08G045_VBAT_BRESETN>; + status =3D "disabled"; + }; + i2c0: i2c@10090000 { compatible =3D "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; reg =3D <0 0x10090000 0 0x400>; @@ -425,4 +437,11 @@ timer { interrupt-names =3D "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; }; + + vbattb_xtal: vbattb-xtal { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board. */ + clock-frequency =3D <0>; + }; }; --=20 2.39.2