From nobody Mon Nov 25 02:39:54 2024 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C4F42C6A3 for ; Wed, 30 Oct 2024 10:47:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730285247; cv=none; b=B98oDdc2euBjbIf/BsWNgsmDQ5sR42VyFrX+FoI0T1MsUonuhnVU8HASyd+GtMclQoOuxOgXdiQADL+ui3ThQwMc5wHNN+y7hoCZjo+DzDAePp6U4KECXrs8hEvNzv/exXEmbhYt9uGZU38XmXtFZ7por6DFOSd+55vdu61P1HY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730285247; c=relaxed/simple; bh=MlHWuTh5yBgmlDp/sZvOENC+3hMjBC0EtLNcayA5/PE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qtGJ/wuMn34oQOKTcAqhsJwaOdGdFObRxBBULr70aXwGYmXzv9onEY9eSvVKxyMOgq7x/NuSW5h0rdp5uKIlCaNf3w8Lt9Y72KJYiMwF9Hk5aSP/zHdddJrvcJFMxfUxwMgmaE8FiLWyVgpQA8lVSHdxy2piiBo8qj/FGE4QowE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=ESkJAztH; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="ESkJAztH" Received: by mail.gandi.net (Postfix) with ESMTPA id F0A35C000E; Wed, 30 Oct 2024 10:47:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730285242; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PFBzuhNdSXqNgNayg9anCpQOhMp/UnCGkxs9tY+mxRc=; b=ESkJAztHiiohybeTLEHdA1PKGui5AaTvRnpZvWM4GMw+Z4fynM1VFIB1Q1wx/GbzfwLfCt XGhYT9OUCYHu5ChJX5zF9xb4+zo00YMT6IjG+P3SDI82+kff1wZGDXAA/Y8xk1lWE4p2qA PVkrOiuhOKYE/xQkj2dd9JofHmhxt/aTUiGIyxxQnIsFhHi3Bfe/wiDstjkrb4OdRhahcs NjVNU7jLXq8ZPJqgjZH6NAAIxeJhxq6c5WBNcDfe5hJxkL7MSMO55PT6Y9CPYrZXsDvBlN wp+VoDhsJBUpBOJfYJeDf0vfmIoZ8l4FSoBFqbdFyUKyTj+BB721sKWQLlwm2g== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH 1/5] memory: ti-aemif: Create aemif_set_cs_timings() Date: Wed, 30 Oct 2024 11:47:13 +0100 Message-ID: <20241030104717.88688-2-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241030104717.88688-1-bastien.curutchet@bootlin.com> References: <20241030104717.88688-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" Create an aemif_set_cs_timings() function to isolate the setting of a chip select timing configuration and ease its exportation. Move the check of the configuration validity from aemif_calc_rate() to this new function. Signed-off-by: Bastien Curutchet --- drivers/memory/ti-aemif.c | 111 ++++++++++++++++++++++++++------------ 1 file changed, 78 insertions(+), 33 deletions(-) diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index d54dc3cfff73..5be6df246075 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -69,15 +69,15 @@ #define ACR_SSTROBE_MASK BIT(31) #define ASIZE_16BIT 1 =20 -#define CONFIG_MASK (TA(TA_MAX) | \ - RHOLD(RHOLD_MAX) | \ - RSTROBE(RSTROBE_MAX) | \ - RSETUP(RSETUP_MAX) | \ - WHOLD(WHOLD_MAX) | \ - WSTROBE(WSTROBE_MAX) | \ - WSETUP(WSETUP_MAX) | \ - EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | \ - ASIZE_MAX) +#define TIMINGS_MASK (TA(TA_MAX) | \ + RHOLD(RHOLD_MAX) | \ + RSTROBE(RSTROBE_MAX) | \ + RSETUP(RSETUP_MAX) | \ + WHOLD(WHOLD_MAX) | \ + WSTROBE(WSTROBE_MAX) | \ + WSETUP(WSETUP_MAX)) + +#define CONFIG_MASK (EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | ASIZE_MAX) =20 /** * struct aemif_cs_data: structure to hold cs parameters @@ -107,6 +107,27 @@ struct aemif_cs_data { u8 asize; }; =20 +/** + * struct aemif_cs_timing: structure to hold cs timing configuration + * values are expressed in number of clock cycles - 1 + * @ta: minimum turn around time + * @rhold read hold width + * @rstrobe read strobe width + * @rsetup read setup width + * @whold write hold width + * @wstrobe write strobe width + * @wsetup write setup width + */ +struct aemif_cs_timings { + u32 ta; + u32 rhold; + u32 rstrobe; + u32 rsetup; + u32 whold; + u32 wstrobe; + u32 wsetup; +}; + /** * struct aemif_device: structure to hold device data * @base: base address of AEMIF registers @@ -125,6 +146,44 @@ struct aemif_device { struct aemif_cs_data cs_data[NUM_CS]; }; =20 +/** + * aemif_set_cs_timings - Set the timing configuration of a given chip sel= ect. + * @aemif: aemif device to configure + * @cs: index of the chip select to configure. + * @timings: timings configuration to set + * + * Returns 0 on success, else negative errno. + */ +static int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct = aemif_cs_timings *timings) +{ + unsigned int offset; + u32 val, set; + + if (!timings || !aemif) + return -EINVAL; + + if (cs > aemif->num_cs) + return -EINVAL; + + if (timings->ta > TA_MAX || timings->rhold > RHOLD_MAX || timings->rstrob= e > RSTROBE_MAX || + timings->rsetup > RSETUP_MAX || timings->whold > WHOLD_MAX || + timings->wstrobe > WSTROBE_MAX || timings->wsetup > WSETUP_MAX) + return -EINVAL; + + set =3D TA(timings->ta) | RHOLD(timings->rhold) | RSTROBE(timings->rstrob= e) | + RSETUP(timings->rsetup) | WHOLD(timings->whold) | + WSTROBE(timings->wstrobe) | WSETUP(timings->wsetup); + + offset =3D A1CR_OFFSET + cs * 4; + + val =3D readl(aemif->base + offset); + val &=3D ~TIMINGS_MASK; + val |=3D set; + writel(val, aemif->base + offset); + + return 0; +} + /** * aemif_calc_rate - calculate timing data. * @pdev: platform device to calculate for @@ -149,10 +208,6 @@ static int aemif_calc_rate(struct platform_device *pde= v, int wanted, if (result < 0) result =3D 0; =20 - /* ... But configuring tighter timings is not an option. */ - else if (result > max) - result =3D -EINVAL; - return result; } =20 @@ -174,32 +229,22 @@ static int aemif_config_abus(struct platform_device *= pdev, int csnum) { struct aemif_device *aemif =3D platform_get_drvdata(pdev); struct aemif_cs_data *data =3D &aemif->cs_data[csnum]; - int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup; unsigned long clk_rate =3D aemif->clk_rate; + struct aemif_cs_timings timings; unsigned offset; u32 set, val; =20 offset =3D A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; =20 - ta =3D aemif_calc_rate(pdev, data->ta, clk_rate, TA_MAX); - rhold =3D aemif_calc_rate(pdev, data->rhold, clk_rate, RHOLD_MAX); - rstrobe =3D aemif_calc_rate(pdev, data->rstrobe, clk_rate, RSTROBE_MAX); - rsetup =3D aemif_calc_rate(pdev, data->rsetup, clk_rate, RSETUP_MAX); - whold =3D aemif_calc_rate(pdev, data->whold, clk_rate, WHOLD_MAX); - wstrobe =3D aemif_calc_rate(pdev, data->wstrobe, clk_rate, WSTROBE_MAX); - wsetup =3D aemif_calc_rate(pdev, data->wsetup, clk_rate, WSETUP_MAX); - - if (ta < 0 || rhold < 0 || rstrobe < 0 || rsetup < 0 || - whold < 0 || wstrobe < 0 || wsetup < 0) { - dev_err(&pdev->dev, "%s: cannot get suitable timings\n", - __func__); - return -EINVAL; - } - - set =3D TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) | - WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup); + timings.ta =3D aemif_calc_rate(pdev, data->ta, clk_rate, TA_MAX); + timings.rhold =3D aemif_calc_rate(pdev, data->rhold, clk_rate, RHOLD_MAX); + timings.rstrobe =3D aemif_calc_rate(pdev, data->rstrobe, clk_rate, RSTROB= E_MAX); + timings.rsetup =3D aemif_calc_rate(pdev, data->rsetup, clk_rate, RSETUP_M= AX); + timings.whold =3D aemif_calc_rate(pdev, data->whold, clk_rate, WHOLD_MAX); + timings.wstrobe =3D aemif_calc_rate(pdev, data->wstrobe, clk_rate, WSTROB= E_MAX); + timings.wsetup =3D aemif_calc_rate(pdev, data->wsetup, clk_rate, WSETUP_M= AX); =20 - set |=3D (data->asize & ACR_ASIZE_MASK); + set =3D (data->asize & ACR_ASIZE_MASK); if (data->enable_ew) set |=3D ACR_EW_MASK; if (data->enable_ss) @@ -210,7 +255,7 @@ static int aemif_config_abus(struct platform_device *pd= ev, int csnum) val |=3D set; writel(val, aemif->base + offset); =20 - return 0; + return aemif_set_cs_timings(aemif, data->cs - aemif->cs_offset, &timings); } =20 static inline int aemif_cycles_to_nsec(int val, unsigned long clk_rate) --=20 2.47.0 From nobody Mon Nov 25 02:39:54 2024 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A426B1E32DE for ; Wed, 30 Oct 2024 10:47:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730285248; cv=none; b=CtNxQ9zMLpa5BQ4ZTIcpqMuIzjK+QwGS37tsE99cWXxzKWSIsGJJTMZKGsgzIr8tGsFwKFd028MHeeFz5D+o8DojzUN9lp2qQ/VzMgWGfX8HXIW0hcfWO1mmd/nOq6GOM/KMO+yDcS0piAP/f4krTIwW/60LMHMAjjhG2i0aylk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730285248; c=relaxed/simple; bh=WXAmA0b3w0csoNcyu9bCVZFa+7i7lNSgINUAn3ZBIrs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Jstpj5j1BklnbiMFQp57o2lekrCFlPAsZ/5zKGLRgPYoo50Hduw6QQbyPjDCpQTJGqS9pS6NTxQ7Ard+mMpKqH7DOPjMAipNOEdAlhA6CSJcme+clxVBqeYcI9R99uM9u+Gi4sjHW7Um69PGsSMSnlU96g5WN0IjYg/bkPTl2Lc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=Bz9mNLCz; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Bz9mNLCz" Received: by mail.gandi.net (Postfix) with ESMTPA id 7836AC000F; Wed, 30 Oct 2024 10:47:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730285244; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uYar1NhwlaSFetKjtJnCr/NEvl6DqNyF39VHto9LoRE=; b=Bz9mNLCzNjVoBUuvBwq86R9NoQKickHBphpyvI+UHXmYYqBnyNQ0+kcz8wIC5Zze8QTw4j /5DfqrdPFzh+4N471vdi6aBtohM5v4d9/Fi7QcMWN6NqC/gq+PD8a1RGH5l6rgNMge4CLw 8EBcjZwNzCwTvHr+18F+cLY2bo0Mk/5NDBVeLSExVO5Agl34c1FG/jby4FHOZSaV6H8Bkb 8n1A655pt4X9kndt/0Rw29QLyKe/rsXEzQ5cIDgJc0fgG0kYXWASU6RJa5XmemXBSNQkce l4H8A31LGmt5GAKl1lpjWTpCca1L7ttg+9TIm+eZn3Z/L+uEUdGoOAnwmGn8sw== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH 2/5] memory: ti-aemif: export aemif_set_cs_timing() Date: Wed, 30 Oct 2024 11:47:14 +0100 Message-ID: <20241030104717.88688-3-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241030104717.88688-1-bastien.curutchet@bootlin.com> References: <20241030104717.88688-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" Export the aemif_set_cs_timing() symbol so it can be used by other drivers Add a spinlock to protect the CS configuration register from concurrent accesses. Signed-off-by: Bastien Curutchet --- drivers/memory/ti-aemif.c | 35 +++++++++++++---------------------- include/memory/ti-aemif.h | 31 +++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+), 22 deletions(-) create mode 100644 include/memory/ti-aemif.h diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index 5be6df246075..ee857c16a02c 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -17,6 +17,8 @@ #include #include #include +#include +#include =20 #define TA_SHIFT 2 #define RHOLD_SHIFT 4 @@ -107,27 +109,6 @@ struct aemif_cs_data { u8 asize; }; =20 -/** - * struct aemif_cs_timing: structure to hold cs timing configuration - * values are expressed in number of clock cycles - 1 - * @ta: minimum turn around time - * @rhold read hold width - * @rstrobe read strobe width - * @rsetup read setup width - * @whold write hold width - * @wstrobe write strobe width - * @wsetup write setup width - */ -struct aemif_cs_timings { - u32 ta; - u32 rhold; - u32 rstrobe; - u32 rsetup; - u32 whold; - u32 wstrobe; - u32 wsetup; -}; - /** * struct aemif_device: structure to hold device data * @base: base address of AEMIF registers @@ -136,6 +117,7 @@ struct aemif_cs_timings { * @num_cs: number of assigned chip-selects * @cs_offset: start number of cs nodes * @cs_data: array of chip-select settings + * @cs_config_lock: lock used to access CS configuration */ struct aemif_device { void __iomem *base; @@ -144,6 +126,7 @@ struct aemif_device { u8 num_cs; int cs_offset; struct aemif_cs_data cs_data[NUM_CS]; + spinlock_t config_cs_lock; }; =20 /** @@ -154,8 +137,9 @@ struct aemif_device { * * Returns 0 on success, else negative errno. */ -static int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct = aemif_cs_timings *timings) +int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct aemif_c= s_timings *timings) { + unsigned long flags; unsigned int offset; u32 val, set; =20 @@ -176,13 +160,16 @@ static int aemif_set_cs_timings(struct aemif_device *= aemif, u8 cs, struct aemif_ =20 offset =3D A1CR_OFFSET + cs * 4; =20 + spin_lock_irqsave(&aemif->config_cs_lock, flags); val =3D readl(aemif->base + offset); val &=3D ~TIMINGS_MASK; val |=3D set; writel(val, aemif->base + offset); + spin_unlock_irqrestore(&aemif->config_cs_lock, flags); =20 return 0; } +EXPORT_SYMBOL(aemif_set_cs_timings); =20 /** * aemif_calc_rate - calculate timing data. @@ -231,6 +218,7 @@ static int aemif_config_abus(struct platform_device *pd= ev, int csnum) struct aemif_cs_data *data =3D &aemif->cs_data[csnum]; unsigned long clk_rate =3D aemif->clk_rate; struct aemif_cs_timings timings; + unsigned long flags; unsigned offset; u32 set, val; =20 @@ -250,10 +238,12 @@ static int aemif_config_abus(struct platform_device *= pdev, int csnum) if (data->enable_ss) set |=3D ACR_SSTROBE_MASK; =20 + spin_lock_irqsave(&aemif->config_cs_lock, flags); val =3D readl(aemif->base + offset); val &=3D ~CONFIG_MASK; val |=3D set; writel(val, aemif->base + offset); + spin_unlock_irqrestore(&aemif->config_cs_lock, flags); =20 return aemif_set_cs_timings(aemif, data->cs - aemif->cs_offset, &timings); } @@ -396,6 +386,7 @@ static int aemif_probe(struct platform_device *pdev) if (IS_ERR(aemif->base)) return PTR_ERR(aemif->base); =20 + spin_lock_init(&aemif->config_cs_lock); if (np) { /* * For every controller device node, there is a cs device node diff --git a/include/memory/ti-aemif.h b/include/memory/ti-aemif.h new file mode 100644 index 000000000000..a1478387a8d0 --- /dev/null +++ b/include/memory/ti-aemif.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __TI_AEMIF_H +#define __TI_AEMIF_H + +/** + * struct aemif_cs_timing: structure to hold cs timing configuration + * values are expressed in number of clock cycles - 1 + * @ta: minimum turn around time + * @rhold read hold width + * @rstrobe read strobe width + * @rsetup read setup width + * @whold write hold width + * @wstrobe write strobe width + * @wsetup write setup width + */ +struct aemif_cs_timings { + u32 ta; + u32 rhold; + u32 rstrobe; + u32 rsetup; + u32 whold; + u32 wstrobe; + u32 wsetup; +}; + +struct aemif_device; + +int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct aemif_c= s_timings *timings); + +#endif // __TI_AEMIF_H --=20 2.47.0 From nobody Mon Nov 25 02:39:54 2024 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A2B71E3DFD for ; Wed, 30 Oct 2024 10:47:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730285250; cv=none; b=fZOXJIwbpGJHhNjA2NSny5JcbifRz5/HU1NYJa3vvFmwQTWreOHJPxTpOUpi04ZPgeh+T86pCo8kxPI6uzN7u2p5QrJ6WmxVILwDkjik4AuIe5vYPnZPlGUYRfnbjdC5K9GpD3PfWkhQcI4YUM2MjpbXYdPSMXSj83/l/gZ1sOg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730285250; c=relaxed/simple; bh=deaieWFiVONpNRlAhKMPRKsF7JDojpQ/DZGVZJ9W5Dg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=paWkddUkrOMUcPRW7C6+INn7eogAUFIV6U8AThi47n127eJmFyjGE6/mrgVcQosUz6R9pHMKhwMyTQO/kEtD+cZLw+yHkaLUl6JE8FQMl4CrGcydwqLqK0C63fOh2ZiB1AuOBtAXsS9X0i4AvjKaiONeAqoVQgU6P0waonqD5Rw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=j2Wzx280; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="j2Wzx280" Received: by mail.gandi.net (Postfix) with ESMTPA id C87FBC0009; Wed, 30 Oct 2024 10:47:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730285245; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=khZM5fFii6r1q+Z9uZi3Zgk6G9+0lCTuTox0qCES4xo=; b=j2Wzx280k2XQM968sbuT1U2dYsnCPm2HLQU44ngdEJm5ohLBShOcnDn0Q8BiPY4sDbgywE vQ0iBf2JEtODkaqrQVeN2/BgUMxAfCjO5MG06L6KxFxBqhR8LpJRNiDcdsclMgTZh4hn3e I8dZbmyPUNWZoxXuR50KbLCpc2XnpGplT3QV9fclVnA/T5umEx3j5Dvet1COyfBQKpGele xaMxoqjVViK93DS3kgwOCpSU1NE3s2Yv3XOx3J6Jt2LoRX/Tyepf5p4aM3ojMnCZsbSTTl HZK+QqgIL/fo3mR6lyGQB89GBkcz9ndKpELVpfAlIPVmzPMtbKX7xz0PNXge3g== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH 3/5] mtd: rawnand: davinci: Order headers alphabetically Date: Wed, 30 Oct 2024 11:47:15 +0100 Message-ID: <20241030104717.88688-4-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241030104717.88688-1-bastien.curutchet@bootlin.com> References: <20241030104717.88688-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" Order headers alphabetically for better readability. Signed-off-by: Bastien Curutchet --- drivers/mtd/nand/raw/davinci_nand.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/dav= inci_nand.c index 392678143a36..3c0efbdd789e 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -10,15 +10,15 @@ * Dirk Behme */ =20 -#include -#include -#include #include #include +#include +#include #include #include -#include #include +#include +#include =20 #define NRCSR_OFFSET 0x00 #define NANDFCR_OFFSET 0x60 --=20 2.47.0 From nobody Mon Nov 25 02:39:54 2024 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2ABC51E4101 for ; Wed, 30 Oct 2024 10:47:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730285250; cv=none; b=UuieOhLo1OWoHgK/Zqb76fNrx55BMShmm5YBDg3MraJuDJyaMDX+IMhSNkoMXRIgBnwMd9OV0C0MU8gyrmvovjPUp22v3o6eqX98cMhq+39I0tOmvqoe5bqi5LPD6ohnhqC8z+BZ0pktvWNYlwp/8fkFcBPwLqgijdsIHliXnU4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730285250; c=relaxed/simple; bh=sbU5xQXF6E4XX9ncnkbKHW3kofSO0YDXfKRl90EyR54=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KtbNvFYzl3wk8rSrNNt2F5uixIZRHzWr4eAJEi/csiRmKdgGsNTT5Ijc9yWyD9dlPP379MMnu/fzvoFDo4fcYf6PDJszwPu6rP5z+qYq26VQDeDr4PWrYhkxxHH71CYbJK6KjV23DhnP/GXqdKldx7Mdfzz+mtTSgkGhW4FNG9M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=JtuhmXyJ; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="JtuhmXyJ" Received: by mail.gandi.net (Postfix) with ESMTPA id 2BB72C000B; Wed, 30 Oct 2024 10:47:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730285246; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=IUlUDpq8VP1OTa7j0y4mtc+eoVWsoIOVcCnsrw8rmJ8=; b=JtuhmXyJ48hFUcuMsvNP2kwUzG5k13sa3FfxMhrI5KIE0hzyiBWs9JLxOxn6moV/hOcgFl P5OwYt1HV5VdRAlNwYSthC7tTOXO/HdSr/DYcSgbLZyJxRmk4F6FqXlCqQk10GHlneYNRu JIOb7uW9iEnKWZ9smETw4LPVH30Zh9yNGLyDUYGUsPdebM+W83vwA/ALihBxfoF/LsneDR gp4IvmCTYlIOIGdIs1ZJ+KzPr8W5qnlFfDfXv1kkeyJcfXhy8iQ6ig/zN8Norv6aHBPMDn Hvkdn77siMNviFlOn4eoWhLQ/IHaTz6ZFZagTCqfn1ZOtF5M5/yWwrchRqo78g== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH 4/5] mtd: rawnand: davinci: Add clock resource Date: Wed, 30 Oct 2024 11:47:16 +0100 Message-ID: <20241030104717.88688-5-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241030104717.88688-1-bastien.curutchet@bootlin.com> References: <20241030104717.88688-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" NAND controller has a reference clock but the driver doesn't use it. Add a struct clock in the struct davinci_nand_info so it can be used to compute timings. Signed-off-by: Bastien Curutchet --- drivers/mtd/nand/raw/davinci_nand.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/dav= inci_nand.c index 3c0efbdd789e..11dc30c29957 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -10,6 +10,7 @@ * Dirk Behme */ =20 +#include #include #include #include @@ -117,6 +118,8 @@ struct davinci_nand_info { uint32_t mask_cle; =20 uint32_t core_chipsel; + + struct clk *clk; }; =20 static DEFINE_SPINLOCK(davinci_nand_lock); @@ -822,6 +825,12 @@ static int nand_davinci_probe(struct platform_device *= pdev) return -EADDRNOTAVAIL; } =20 + info->clk =3D devm_clk_get(&pdev->dev, "aemif"); + if (IS_ERR(info->clk)) { + dev_err(&pdev->dev, "failed to get clock %ld", PTR_ERR(info->clk)); + return PTR_ERR(info->clk); + } + info->pdev =3D pdev; info->base =3D base; info->vaddr =3D vaddr; --=20 2.47.0 From nobody Mon Nov 25 02:39:54 2024 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 735481E47AC for ; Wed, 30 Oct 2024 10:47:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730285252; cv=none; b=O0iEL0nKBEbdCp1jugYUpqVaPgEpi1+ftri+cbERTKcePz1vmDf5nWGS0KAAX/bwoFZML79ukYtRB5PmAVhJXtftOLljE5q8zarWCE6SRDhn2mC10UwdDi2NRhCPfsF/Sx1W61rb5sBvroBuK900RJDGtIFlYhpAVBeAiUf8bFM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730285252; c=relaxed/simple; bh=TN1cHZIOpy6i3DhRcNJ2ESG8eeF0p3jBWFhx4Uh7WYg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=O6b3IGzQT3cqI4Ja5gyBrqozRK69AZloWpa+JFTnt/bMnuuDYze03u1f3WJSxHhmoOgMyExAFSk5FQdYsFONMdMwyzUDhqYS5WrmHMsh0VTvvvYIPKCvGKldeqHqjB6wAEsrFrnFq+H/kQf76aqwYUxvI8lbTxUti887rVttJIo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=UEwPKUWv; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="UEwPKUWv" Received: by mail.gandi.net (Postfix) with ESMTPA id 821A2C0003; Wed, 30 Oct 2024 10:47:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730285248; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=v9j3vuJY/COyFVkvUtwz2LlT17k8T67pfaVSrv49d48=; b=UEwPKUWvjJ2u8dfZ4L4Viya3Wuxn5XcrOj6sZz0EJlBOQHmSvxhy93WFxYHR2DuXJJv4xw cw8xss9CIwvV0vrqWJf8D2r1b5Wh9Y6IZZeD508WBPqi1pwjco3Um5yW/xPvA9phSXUD6I OKzdWKv2YBoZyoYtQ9KQJyDZk6lY/0KtMoYJFmzGTa44JT4PlYmle5dtT76AZxfZVPH5e1 loMfH3iVTEfd0zGrc2wkW1gllJftbB7AbPQj5/TOjBtpcCyOSFSmZGYIcQyZ5Uqpvirx7j Z5xdCgw5ymkOezsYJPig6mw4L9S5GslNJofEC0iCxVTnWmJjlZblbDt3YsxbRQ== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH 5/5] mtd: rawnand: davinci: Implement setup_interface() operation Date: Wed, 30 Oct 2024 11:47:17 +0100 Message-ID: <20241030104717.88688-6-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241030104717.88688-1-bastien.curutchet@bootlin.com> References: <20241030104717.88688-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com The setup_interface() operation isn't implemented. It forces the driver to use the ONFI mode 0, though it could use more optimal modes. Implement the setup_interface() operation. It uses the aemif_set_cs_timings() function from the AEMIF driver to update the chip select timings. The calculation of the register's contents is directly extracted from =C2=A720.3.2.3 of the DaVinci TRM [1] These timings are previously set by the AEMIF driver itself from device-tree properties. Therefore, IMHO, failing to update them in the setup_interface() isn't critical, which is why 0 is returned even when timings aren't updated. MAX_TH_PS and MAX_TSU_PS are the worst case timings based on the Keystone2 and DaVinci datasheets. [1] : https://www.ti.com/lit/ug/spruh77c/spruh77c.pdf Signed-off-by: Bastien Curutchet --- drivers/mtd/nand/raw/davinci_nand.c | 78 +++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/dav= inci_nand.c index 11dc30c29957..76f0306dfe77 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -20,6 +20,7 @@ #include #include #include +#include =20 #define NRCSR_OFFSET 0x00 #define NANDFCR_OFFSET 0x60 @@ -44,6 +45,9 @@ #define MASK_ALE 0x08 #define MASK_CLE 0x10 =20 +#define MAX_TSU_PS 3000 /* Input setup time in ps */ +#define MAX_TH_PS 1600 /* Input hold time in ps */ + struct davinci_nand_pdata { uint32_t mask_ale; uint32_t mask_cle; @@ -120,6 +124,7 @@ struct davinci_nand_info { uint32_t core_chipsel; =20 struct clk *clk; + struct aemif_device *aemif; }; =20 static DEFINE_SPINLOCK(davinci_nand_lock); @@ -767,9 +772,81 @@ static int davinci_nand_exec_op(struct nand_chip *chip, return 0; } =20 +#define TO_CYCLES(ps, period_ns) (DIV_ROUND_UP((ps) / 1000, (period_ns))) + +static int davinci_nand_setup_interface(struct nand_chip *chip, int chipnr, + const struct nand_interface_config *conf) +{ + struct davinci_nand_info *info =3D to_davinci_nand(nand_to_mtd(chip)); + const struct nand_sdr_timings *sdr; + struct aemif_cs_timings timings; + s32 cfg, min, cyc_ns; + + cyc_ns =3D 1000000000 / clk_get_rate(info->clk); + + sdr =3D nand_get_sdr_timings(conf); + if (IS_ERR(sdr)) + return PTR_ERR(sdr); + + cfg =3D TO_CYCLES(sdr->tCLR_min, cyc_ns) - 1; + timings.rsetup =3D cfg > 0 ? cfg : 0; + + cfg =3D max_t(s32, TO_CYCLES(sdr->tREA_max + MAX_TSU_PS, cyc_ns), + TO_CYCLES(sdr->tRP_min, cyc_ns)) - 1; + timings.rstrobe =3D cfg > 0 ? cfg : 0; + + min =3D TO_CYCLES(sdr->tCEA_max + MAX_TSU_PS, cyc_ns) - 2; + while ((s32)(timings.rsetup + timings.rstrobe) < min) + timings.rstrobe++; + + cfg =3D TO_CYCLES((s32)(MAX_TH_PS - sdr->tCHZ_max), cyc_ns) - 1; + timings.rhold =3D cfg > 0 ? cfg : 0; + + min =3D TO_CYCLES(sdr->tRC_min, cyc_ns) - 3; + while ((s32)(timings.rsetup + timings.rstrobe + timings.rhold) < min) + timings.rhold++; + + cfg =3D TO_CYCLES((s32)(sdr->tRHZ_max - (timings.rhold + 1) * cyc_ns * 10= 00), cyc_ns); + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tCHZ_max, cyc_ns)) - 1; + timings.ta =3D cfg > 0 ? cfg : 0; + + cfg =3D TO_CYCLES(sdr->tWP_min, cyc_ns) - 1; + timings.wstrobe =3D cfg > 0 ? cfg : 0; + + cfg =3D max_t(s32, TO_CYCLES(sdr->tCLS_min, cyc_ns), TO_CYCLES(sdr->tALS_= min, cyc_ns)); + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tCS_min, cyc_ns)) - 1; + timings.wsetup =3D cfg > 0 ? cfg : 0; + + min =3D TO_CYCLES(sdr->tDS_min, cyc_ns) - 2; + while ((s32)(timings.wsetup + timings.wstrobe) < min) + timings.wstrobe++; + + cfg =3D max_t(s32, TO_CYCLES(sdr->tCLH_min, cyc_ns), TO_CYCLES(sdr->tALH_= min, cyc_ns)); + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tCH_min, cyc_ns)); + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tDH_min, cyc_ns)) - 1; + timings.whold =3D cfg > 0 ? cfg : 0; + + min =3D TO_CYCLES(sdr->tWC_min, cyc_ns) - 2; + while ((s32)(timings.wsetup + timings.wstrobe + timings.whold) < min) + timings.whold++; + + dev_dbg(&info->pdev->dev, "RSETUP %x RSTROBE %x RHOLD %x\n", + timings.rsetup, timings.rstrobe, timings.rhold); + dev_dbg(&info->pdev->dev, "TA %x\n", timings.ta); + dev_dbg(&info->pdev->dev, "WSETUP %x WSTROBE %x WHOLD %x\n", + timings.wsetup, timings.wstrobe, timings.whold); + + if (aemif_set_cs_timings(info->aemif, info->core_chipsel, &timings) < 0) + dev_info(&info->pdev->dev, + "Failed to dynamically update the CS timings, keep them unchanged"); + + return 0; +} + static const struct nand_controller_ops davinci_nand_controller_ops =3D { .attach_chip =3D davinci_nand_attach_chip, .exec_op =3D davinci_nand_exec_op, + .setup_interface =3D davinci_nand_setup_interface, }; =20 static int nand_davinci_probe(struct platform_device *pdev) @@ -834,6 +911,7 @@ static int nand_davinci_probe(struct platform_device *p= dev) info->pdev =3D pdev; info->base =3D base; info->vaddr =3D vaddr; + info->aemif =3D dev_get_drvdata(pdev->dev.parent); =20 mtd =3D nand_to_mtd(&info->chip); mtd->dev.parent =3D &pdev->dev; --=20 2.47.0