From nobody Mon Nov 25 04:54:58 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDDAA1E32C5; Wed, 30 Oct 2024 10:38:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730284689; cv=none; b=MQjoTeZNCxPCXpbt5nwEaWiGlNQKc5mQ5osBHbSlh0IDHChdMb8nU7l+j3ejzdnrMsh43+eLaCGo+OF/xKJUQpxPWh/6hzPKZd97CpZCvjy63Eo/kOt7preU1vIJUUMcZ5PQ9wFqZ6MPQ06uFKFbo6JtwtbMrsrxWZkXySyA6/g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730284689; c=relaxed/simple; bh=up00M4P8wHYUf9DZmtWdUuM2nsCE09kNV9Y2rzPY44w=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aF5PS9vfo3dRGXPnanJP6sM1NEZdAyMygSBNcjhAHKgGyjxnPl/f+kYD+1tH41iDaGPCDnRxlfza/wz3imCGzx5M3S101WnbNm2WdWq89MAc08KiOcgYv/RAVSbLh0b1rekB18txLw515gAF2tKXmYnmteH34WRWZayVB6ko45E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=gmvaLKnu; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="gmvaLKnu" X-UUID: 093e312c96ab11efb88477ffae1fc7a5-20241030 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=sNSa2kfL4CrNWDSpKuHuCoNeytvhALp1cji8Fdb0hKs=; b=gmvaLKnuptuRNZ+a7DLiFHpQlbsW7EImMLEbnriGl5T2JLWCjNVgqxMcBqsN5KMg9b2gb7A4LMIO/eYtrqVZqFAw8NQKFY54dN520F9RAY0VCoD984OKri0Nl65Fs7O01shykuHH6zX2ueGi/jhs/RY46gdh8MQfME0gF9B5/HI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.42,REQID:0043e5b4-295a-4dae-92c5-0eb3479f91a0,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:b0fcdc3,CLOUDID:47406d48-ca13-40ea-8070-fa012edab362,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULS X-UUID: 093e312c96ab11efb88477ffae1fc7a5-20241030 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1939567141; Wed, 30 Oct 2024 18:38:01 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 30 Oct 2024 18:37:58 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 30 Oct 2024 18:37:58 +0800 From: Sky Huang To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , "Simon Horman" , , , , CC: Steven Liu , SkyLake.Huang Subject: [PATCH net-next 4/5] net: phy: mediatek: Integrate read/write page helper functions Date: Wed, 30 Oct 2024 18:35:53 +0800 Message-ID: <20241030103554.29218-5-SkyLake.Huang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241030103554.29218-1-SkyLake.Huang@mediatek.com> References: <20241030103554.29218-1-SkyLake.Huang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--3.069700-8.000000 X-TMASE-MatchedRID: dY/STlX7LWKw8kFTdnBpUcdDwwczffCufLPKYyLDlAdo5YsPsbyLXUgC lCIX2geweeTK1AUftLLijpjet3oGSAV0DOIpze3p4pdq9sdj8LUK3n1SHen81fFJXtgF4GFLUPL 91Dv7dOIBz/qRD2hFcngQwncoPpqKCYQihzr905ltPeYaZY+k178sbddn7IcZRi9INZ1ZpGEx4S ftoQr3xM3ZiXXMcP4YoqDdv5CX5TjDiZmOF0V5FZ4CIKY/Hg3AGdQnQSTrKGPEQdG7H66TyJ8TM nmE+d0Z1AsD/E4UR7Ws3XFbuXbpsaUGTnfsa7pox7Z20LmKG/OsF/46ifTin+W21jS40FF+nwUd hkr42QLeuUz0FT6I0xjTW0JmC2y2eZUpm6wun3ba/06NhYDa4wyzCDjlUx89p2y3mIB+it9WXGv UUmKP2w== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--3.069700-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: B53C67DA0D8030081098948A7979B88326A69ED31E79DA156411C06A0C26351E2000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "SkyLake.Huang" This patch integrates read/write page helper functions as MTK phy lib. They are basically the same in mtk-ge.c & mtk-ge-soc.c. Signed-off-by: SkyLake.Huang --- No change since commit: https://lore.kernel.org/netdev/20241004102413.5838-6-SkyLake.Huang@mediatek= .com/ Andrew Lunn has already reviewed this. --- drivers/net/phy/mediatek/mtk-ge-soc.c | 18 ++++-------------- drivers/net/phy/mediatek/mtk-ge.c | 20 ++++++-------------- drivers/net/phy/mediatek/mtk-phy-lib.c | 12 ++++++++++++ drivers/net/phy/mediatek/mtk.h | 3 +++ 4 files changed, 25 insertions(+), 28 deletions(-) diff --git a/drivers/net/phy/mediatek/mtk-ge-soc.c b/drivers/net/phy/mediat= ek/mtk-ge-soc.c index d3a8b39..38dc898 100644 --- a/drivers/net/phy/mediatek/mtk-ge-soc.c +++ b/drivers/net/phy/mediatek/mtk-ge-soc.c @@ -271,16 +271,6 @@ struct mtk_socphy_shared { struct mtk_socphy_priv priv[4]; }; =20 -static int mtk_socphy_read_page(struct phy_device *phydev) -{ - return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); -} - -static int mtk_socphy_write_page(struct phy_device *phydev, int page) -{ - return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); -} - /* One calibration cycle consists of: * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high * until AD_CAL_COMP is ready to output calibration result. @@ -1337,8 +1327,8 @@ static struct phy_driver mtk_socphy_driver[] =3D { .probe =3D mt7981_phy_probe, .suspend =3D genphy_suspend, .resume =3D genphy_resume, - .read_page =3D mtk_socphy_read_page, - .write_page =3D mtk_socphy_write_page, + .read_page =3D mtk_phy_read_page, + .write_page =3D mtk_phy_write_page, .led_blink_set =3D mt798x_phy_led_blink_set, .led_brightness_set =3D mt798x_phy_led_brightness_set, .led_hw_is_supported =3D mt798x_phy_led_hw_is_supported, @@ -1354,8 +1344,8 @@ static struct phy_driver mtk_socphy_driver[] =3D { .probe =3D mt7988_phy_probe, .suspend =3D genphy_suspend, .resume =3D genphy_resume, - .read_page =3D mtk_socphy_read_page, - .write_page =3D mtk_socphy_write_page, + .read_page =3D mtk_phy_read_page, + .write_page =3D mtk_phy_write_page, .led_blink_set =3D mt798x_phy_led_blink_set, .led_brightness_set =3D mt798x_phy_led_brightness_set, .led_hw_is_supported =3D mt798x_phy_led_hw_is_supported, diff --git a/drivers/net/phy/mediatek/mtk-ge.c b/drivers/net/phy/mediatek/m= tk-ge.c index 54ea64a..9122899 100644 --- a/drivers/net/phy/mediatek/mtk-ge.c +++ b/drivers/net/phy/mediatek/mtk-ge.c @@ -3,6 +3,8 @@ #include #include =20 +#include "mtk.h" + #define MTK_EXT_PAGE_ACCESS 0x1f #define MTK_PHY_PAGE_STANDARD 0x0000 #define MTK_PHY_PAGE_EXTENDED 0x0001 @@ -11,16 +13,6 @@ #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 =20 -static int mtk_gephy_read_page(struct phy_device *phydev) -{ - return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); -} - -static int mtk_gephy_write_page(struct phy_device *phydev, int page) -{ - return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); -} - static void mtk_gephy_config_init(struct phy_device *phydev) { /* Enable HW auto downshift */ @@ -77,8 +69,8 @@ static struct phy_driver mtk_gephy_driver[] =3D { .handle_interrupt =3D genphy_handle_interrupt_no_ack, .suspend =3D genphy_suspend, .resume =3D genphy_resume, - .read_page =3D mtk_gephy_read_page, - .write_page =3D mtk_gephy_write_page, + .read_page =3D mtk_phy_read_page, + .write_page =3D mtk_phy_write_page, }, { PHY_ID_MATCH_EXACT(0x03a29441), @@ -91,8 +83,8 @@ static struct phy_driver mtk_gephy_driver[] =3D { .handle_interrupt =3D genphy_handle_interrupt_no_ack, .suspend =3D genphy_suspend, .resume =3D genphy_resume, - .read_page =3D mtk_gephy_read_page, - .write_page =3D mtk_gephy_write_page, + .read_page =3D mtk_phy_read_page, + .write_page =3D mtk_phy_write_page, }, }; =20 diff --git a/drivers/net/phy/mediatek/mtk-phy-lib.c b/drivers/net/phy/media= tek/mtk-phy-lib.c index 8d795bc..98a09d6 100644 --- a/drivers/net/phy/mediatek/mtk-phy-lib.c +++ b/drivers/net/phy/mediatek/mtk-phy-lib.c @@ -6,6 +6,18 @@ =20 #include "mtk.h" =20 +int mtk_phy_read_page(struct phy_device *phydev) +{ + return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); +} +EXPORT_SYMBOL_GPL(mtk_phy_read_page); + +int mtk_phy_write_page(struct phy_device *phydev, int page) +{ + return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); +} +EXPORT_SYMBOL_GPL(mtk_phy_write_page); + int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, unsigned long rules, unsigned long supported_triggers) diff --git a/drivers/net/phy/mediatek/mtk.h b/drivers/net/phy/mediatek/mtk.h index 9aaff2c..63d9fe1 100644 --- a/drivers/net/phy/mediatek/mtk.h +++ b/drivers/net/phy/mediatek/mtk.h @@ -66,6 +66,9 @@ struct mtk_socphy_priv { unsigned long led_state; }; =20 +int mtk_phy_read_page(struct phy_device *phydev); +int mtk_phy_write_page(struct phy_device *phydev, int page); + int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, unsigned long rules, unsigned long supported_triggers); --=20 2.45.2