From nobody Mon Nov 25 05:19:30 2024 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4E971E47C3 for ; Wed, 30 Oct 2024 12:10:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730290226; cv=none; b=TFbwsiMp2NjXfbmBPSeqgJ1kd0WPyKiA2w/z8Up6kzctuEtkzOeQhrhaHDTA9BRue1gF6p+/hyzkKeffiA5fZ3vPyK/qxcqivBykRqXh4A51G2ABKu/iwjK1du+bZZlC4JetKcpxolQ3DaMj4qyoaDfZ6g/sGm8bMCUqJmyIOQc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730290226; c=relaxed/simple; bh=CPjrZ4fKhbLXk0zIZxVMkwmvH7cZECkh0hUkVKEQKCc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Gx1iApnjWqBCpHS12SbxPxdbfX+WWicw6A3/6TSpIakQZym3DgMwvrdiGxK2YqjyaxkhdcJImVgMUzVM0tKTA4yxvwOybwRups33LIGz5j2J10M+OSQqh4LiPN7kc2uQJpa/9UNhsyEeN/RLg2q8jOx0l9aPCjVRinQ++2RTS18= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from ptz.office.stw.pengutronix.de ([2a0a:edc0:0:900:1d::77] helo=ratatoskr.trumtrar.info) by metis.whiteo.stw.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1t67Wm-0006os-Tb; Wed, 30 Oct 2024 13:10:20 +0100 From: Steffen Trumtrar Date: Wed, 30 Oct 2024 13:10:13 +0100 Subject: [PATCH 2/4] arm64: dts: agilex5: add gmac nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241030-v6-12-topic-socfpga-agilex5-v1-2-b2b67780e60e@pengutronix.de> References: <20241030-v6-12-topic-socfpga-agilex5-v1-0-b2b67780e60e@pengutronix.de> In-Reply-To: <20241030-v6-12-topic-socfpga-agilex5-v1-0-b2b67780e60e@pengutronix.de> To: Dinh Nguyen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Michael Turquette , Stephen Boyd Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-clk@vger.kernel.org, kernel@pengutronix.de, Steffen Trumtrar X-Mailer: b4 0.14.2 X-SA-Exim-Connect-IP: 2a0a:edc0:0:900:1d::77 X-SA-Exim-Mail-From: s.trumtrar@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org The Agilex5 provides three Synopsys XGMAC ethernet cores, that can be used to transmit and receive data at 10M/100M/1G/2.5G over ethernet connections and enables support for Time Sensitive Networking (TSN) applications. Signed-off-by: Steffen Trumtrar --- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 321 +++++++++++++++++++++= ++++ 1 file changed, 321 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/bo= ot/dts/intel/socfpga_agilex5.dtsi index 57c28e284cccdb99ede6cea2bc0e8dd8aaf47fe9..761d970f8de59e08275edf15a9c= 890ba3bb1404c 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -141,6 +141,327 @@ soc: soc@0 { device_type =3D "soc"; interrupt-parent =3D <&intc>; =20 + gmac0: ethernet@10810000 { + compatible =3D "altr,socfpga-stmmac-a10-s10", + "snps,dwxgmac-2.10", + "snps,dwxgmac"; + reg =3D <0x10810000 0x3500>; + interrupt-parent =3D <&intc>; + interrupts =3D ; + interrupt-names =3D "macirq"; + max-frame-size =3D <3800>; + snps,multicast-filter-bins =3D <64>; + snps,perfect-filter-entries =3D <64>; + rx-fifo-depth =3D <16384>; + tx-fifo-depth =3D <32768>; + resets =3D <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; + reset-names =3D "stmmaceth", "stmmaceth-ocp"; + clocks =3D <&clkmgr AGILEX5_EMAC0_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names =3D "stmmaceth", "ptp_ref"; + snps,axi-config =3D <&stmmac_axi_emac0_setup>; + snps,mtl-rx-config =3D <&mtl_rx_emac0_setup>; + snps,mtl-tx-config =3D <&mtl_tx_emac0_setup>; + altr,sysmgr-syscon =3D <&sysmgr 0x44 0>; + status =3D "disabled"; + + stmmac_axi_emac0_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <31>; + snps,rd_osr_lmt =3D <31>; + snps,blen =3D <0 0 0 32 16 8 4>; + }; + + mtl_rx_emac0_setup: rx-queues-config { + snps,rx-queues-to-use =3D <8>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + }; + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x4>; + }; + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x5>; + }; + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x6>; + }; + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x7>; + }; + }; + + mtl_tx_emac0_setup: tx-queues-config { + snps,tx-queues-to-use =3D <8>; + snps,tx-sched-wrr; + queue0 { + snps,weight =3D <0x9>; + snps,dcb-algorithm; + }; + queue1 { + snps,weight =3D <0x0A>; + snps,dcb-algorithm; + }; + queue2 { + snps,weight =3D <0x0B>; + snps,dcb-algorithm; + }; + queue3 { + snps,weight =3D <0x0C>; + snps,dcb-algorithm; + }; + queue4 { + snps,weight =3D <0x0D>; + snps,dcb-algorithm; + }; + queue5 { + snps,weight =3D <0x0E>; + snps,dcb-algorithm; + }; + queue6 { + snps,weight =3D <0x0F>; + snps,dcb-algorithm; + snps,tbs-enable; + }; + queue7 { + snps,weight =3D <0x10>; + snps,dcb-algorithm; + snps,tbs-enable; + }; + }; + }; + + gmac1: ethernet@10820000 { + compatible =3D "altr,socfpga-stmmac-a10-s10", + "snps,dwxgmac-2.10", + "snps,dwxgmac"; + reg =3D <0x10820000 0x3500>; + interrupt-parent =3D <&intc>; + interrupts =3D ; + interrupt-names =3D "macirq"; + max-frame-size =3D <3800>; + snps,multicast-filter-bins =3D <64>; + snps,perfect-filter-entries =3D <64>; + rx-fifo-depth =3D <16384>; + tx-fifo-depth =3D <32768>; + resets =3D <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; + reset-names =3D "stmmaceth", "stmmaceth-ocp"; + clocks =3D <&clkmgr AGILEX5_EMAC1_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names =3D "stmmaceth", "ptp_ref"; + snps,axi-config =3D <&stmmac_axi_emac1_setup>; + snps,mtl-rx-config =3D <&mtl_rx_emac1_setup>; + snps,mtl-tx-config =3D <&mtl_tx_emac1_setup>; + altr,sysmgr-syscon =3D <&sysmgr 0x48 0>; + status =3D "disabled"; + + stmmac_axi_emac1_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <31>; + snps,rd_osr_lmt =3D <31>; + snps,blen =3D <0 0 0 32 16 8 4>; + }; + + mtl_rx_emac1_setup: rx-queues-config { + snps,rx-queues-to-use =3D <8>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + }; + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x4>; + }; + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x5>; + }; + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x6>; + }; + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x7>; + }; + }; + + mtl_tx_emac1_setup: tx-queues-config { + snps,tx-queues-to-use =3D <8>; + snps,tx-sched-wrr; + queue0 { + snps,weight =3D <0x9>; + snps,dcb-algorithm; + }; + queue1 { + snps,weight =3D <0x0A>; + snps,dcb-algorithm; + }; + queue2 { + snps,weight =3D <0x0B>; + snps,dcb-algorithm; + }; + queue3 { + snps,weight =3D <0x0C>; + snps,dcb-algorithm; + }; + queue4 { + snps,weight =3D <0x0D>; + snps,dcb-algorithm; + }; + queue5 { + snps,weight =3D <0x0E>; + snps,dcb-algorithm; + }; + queue6 { + snps,weight =3D <0x0F>; + snps,dcb-algorithm; + snps,tbs-enable; + }; + queue7 { + snps,weight =3D <0x10>; + snps,dcb-algorithm; + snps,tbs-enable; + }; + }; + }; + + gmac2: ethernet@10830000 { + compatible =3D "altr,socfpga-stmmac-a10-s10", + "snps,dwxgmac-2.10", + "snps,dwxgmac"; + reg =3D <0x10830000 0x3500>; + interrupt-parent =3D <&intc>; + interrupts =3D ; + interrupt-names =3D "macirq"; + max-frame-size =3D <3800>; + snps,multicast-filter-bins =3D <64>; + snps,perfect-filter-entries =3D <64>; + rx-fifo-depth =3D <16384>; + tx-fifo-depth =3D <32768>; + resets =3D <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; + reset-names =3D "stmmaceth", "stmmaceth-ocp"; + clocks =3D <&clkmgr AGILEX5_EMAC2_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names =3D "stmmaceth", "ptp_ref"; + snps,axi-config =3D <&stmmac_axi_emac2_setup>; + snps,mtl-rx-config =3D <&mtl_rx_emac2_setup>; + snps,mtl-tx-config =3D <&mtl_tx_emac2_setup>; + altr,sysmgr-syscon =3D <&sysmgr 0x4c 0>; + status =3D "disabled"; + + stmmac_axi_emac2_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <31>; + snps,rd_osr_lmt =3D <31>; + snps,blen =3D <0 0 0 32 16 8 4>; + }; + + mtl_rx_emac2_setup: rx-queues-config { + snps,rx-queues-to-use =3D <8>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + }; + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x4>; + }; + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x5>; + }; + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x6>; + }; + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x7>; + }; + }; + + mtl_tx_emac2_setup: tx-queues-config { + snps,tx-queues-to-use =3D <8>; + snps,tx-sched-wrr; + queue0 { + snps,weight =3D <0x9>; + snps,dcb-algorithm; + }; + queue1 { + snps,weight =3D <0x0A>; + snps,dcb-algorithm; + }; + queue2 { + snps,weight =3D <0x0B>; + snps,dcb-algorithm; + }; + queue3 { + snps,weight =3D <0x0C>; + snps,dcb-algorithm; + }; + queue4 { + snps,weight =3D <0x0D>; + snps,dcb-algorithm; + }; + queue5 { + snps,weight =3D <0x0E>; + snps,dcb-algorithm; + }; + queue6 { + snps,weight =3D <0x0F>; + snps,dcb-algorithm; + snps,tbs-enable; + }; + queue7 { + snps,weight =3D <0x10>; + snps,dcb-algorithm; + snps,tbs-enable; + }; + }; + }; + clkmgr: clock-controller@10d10000 { compatible =3D "intel,agilex5-clkmgr"; reg =3D <0x10d10000 0x1000>; --=20 2.46.0