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[46.53.189.50]) by smtp.googlemail.com with ESMTPSA id 4fb4d7f45d1cf-5cbb62c20dasm4970447a12.46.2024.10.30.11.57.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Oct 2024 11:57:47 -0700 (PDT) From: Dzmitry Sankouski Date: Wed, 30 Oct 2024 21:57:38 +0300 Subject: [PATCH v8 2/3] clk: qcom: clk-rcg2: split __clk_rcg2_configure function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241030-starqltechn_integration_upstream-v8-2-40f8d5e47062@gmail.com> References: <20241030-starqltechn_integration_upstream-v8-0-40f8d5e47062@gmail.com> In-Reply-To: <20241030-starqltechn_integration_upstream-v8-0-40f8d5e47062@gmail.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Dzmitry Sankouski X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730314661; l=2751; i=dsankouski@gmail.com; s=20240619; h=from:subject:message-id; bh=QVwTe5vkCgC6ZyHfvLeoIbyNzROGNaBzi2ICIXq0Aks=; b=3jw5m2WKGbv5GxIj0Es3IcK7dcummTxD9aCszeX1Y8Vw5GUfX/+tYNIGvILQVIFDY+VsuVo+0 6wsRagdd9ejAXWCkotTootxrnGI6RwtrmnTQrI03cbkjunRsvsKpFqx X-Developer-Key: i=dsankouski@gmail.com; a=ed25519; pk=YJcXFcN1EWrzBYuiE2yi5Mn6WLn6L1H71J+f7X8fMag= __clk_rcg2_configure function does 2 things - configures parent and mnd values. In order to be able to add new clock options, we should split. Move __clk_rcg2_configure logic on 2 functions: - __clk_rcg2_configure_parent which configures clock parent - __clk_rcg2_configure_mnd which configures mnd values __clk_rcg2_configure delegates to mentioned functions. Signed-off-by: Dzmitry Sankouski --- drivers/clk/qcom/clk-rcg2.c | 37 +++++++++++++++++++++++++++++++------ 1 file changed, 31 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index b403e4d6dcdd..714ab79e11d6 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -402,16 +402,26 @@ static int clk_rcg2_fm_determine_rate(struct clk_hw *= hw, return _freq_tbl_fm_determine_rate(hw, rcg->freq_multi_tbl, req); } =20 -static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tb= l *f, - u32 *_cfg) +static int __clk_rcg2_configure_parent(struct clk_rcg2 *rcg, u8 src, u32 *= _cfg) { - u32 cfg, mask, d_val, not2d_val, n_minus_m; struct clk_hw *hw =3D &rcg->clkr.hw; - int ret, index =3D qcom_find_src_index(hw, rcg->parent_map, f->src); + int index =3D qcom_find_src_index(hw, rcg->parent_map, src); =20 if (index < 0) return index; =20 + *_cfg &=3D ~CFG_SRC_SEL_MASK; + *_cfg |=3D rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; + + return 0; +} + +static int __clk_rcg2_configure_mnd(struct clk_rcg2 *rcg, const struct fre= q_tbl *f, + u32 *_cfg) +{ + u32 cfg, mask, d_val, not2d_val, n_minus_m; + int ret; + if (rcg->mnd_width && f->n) { mask =3D BIT(rcg->mnd_width) - 1; ret =3D regmap_update_bits(rcg->clkr.regmap, @@ -440,9 +450,8 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, c= onst struct freq_tbl *f, } =20 mask =3D BIT(rcg->hid_width) - 1; - mask |=3D CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK; + mask |=3D CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK; cfg =3D f->pre_div << CFG_SRC_DIV_SHIFT; - cfg |=3D rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; if (rcg->mnd_width && f->n && (f->m !=3D f->n)) cfg |=3D CFG_MODE_DUAL_EDGE; if (rcg->hw_clk_ctrl) @@ -454,6 +463,22 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, = const struct freq_tbl *f, return 0; } =20 +static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tb= l *f, + u32 *_cfg) +{ + int ret; + + ret =3D __clk_rcg2_configure_parent(rcg, f->src, _cfg); + if (ret) + return ret; + + ret =3D __clk_rcg2_configure_mnd(rcg, f, _cfg); + if (ret) + return ret; + + return 0; +} + static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl = *f) { u32 cfg; --=20 2.39.2