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[2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53bb81a5760sm233049e87.84.2024.10.30.04.51.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Oct 2024 04:51:05 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 30 Oct 2024 13:50:57 +0200 Subject: [PATCH v2 4/4] arm64: dts: qcom: sar2130p: add QAR2130P board file Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241030-sar2130p-dt-v2-4-027364ca0e86@linaro.org> References: <20241030-sar2130p-dt-v2-0-027364ca0e86@linaro.org> In-Reply-To: <20241030-sar2130p-dt-v2-0-027364ca0e86@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Krishna Kurapati , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=13712; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=oKK5gbWEejDoMYSUIFjcuSz0eq7ltuyCy9xv93iydLE=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnIh2jbu5dYacdVO7RIUpjWTpmXN7d81KAKC2Ti T/WTvVcB9SJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZyIdowAKCRAU23LtvoBl uPpHD/0djvST80zZJetKLUvSf8hmnEpo02O26DvdoMSYX+0gQXtX8rPw8+wCuL6+/GOhKt16kjd uf+CVXHtcMfBwpXLj3zSgNVEZyaxhmU1zzMXTh/9NM505CJRBQb0V4CoSEmlANU+8sjksu1quof P6JWYDxDFG+LA/Z1xWeVMwqYwezEJpnSvcNS/mZ5eiSAF6tDWDhGRF00nv+6FVIRTkDpbY0vNTL SK6GKFQu+CIBz3pnxH4sY6Js0D9dfv2idc48Khx92RCSKFWGZb9OTfVtNW2aq3o5G0McpAuQWUj YMpZU3geL/B/oqvYY63f1lTDnnKGd8ObwQBuSERjU1Umg71SP/IEzV3+n/F7idys/+lo6uNTDg2 xN0hBHjyGbFvR5VWfbP6/zd30XEpC5NaP/huguZdiNwd/RS8Xgq9eFSTF1h4nDM+pW3Xf6j98DP Qrn2k1NrTMwFOrJFdtzbI2gpfUZLXA4W+1wI+kD33d6VjYFiyWtGt1zu7VIj38kCGKwxshzMugv DUBYHAc/Q03Wju8Na6SGd/LBASu9wNaXR/bPjJN2uImWM6/GJ6m3je2hRvXhxT+1qUbhEkf4PId JCm4YSETBPIWXDu5rSC54GjYDltAF1PIkgn33ZPFuasxo3/ornXy67f4dCM0lwewVGtwfeDS8aR 0Mi+YsKY0OH/QPA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Add board DT file for the Qualcomm Snapdragon AR2 Gen1 Smart Viewer Development Kit. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/Makefile | 2 + arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts | 551 +++++++++++++++++++++= ++++ 2 files changed, 553 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index ac199f809b0d4e514878518604a23b4f1ab8ef79..fc4ab86895441fb3832e43eed75= 8719cee73a250 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -3,6 +3,8 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D apq8016-sbc.dtb =20 apq8016-sbc-usb-host-dtbs :=3D apq8016-sbc.dtb apq8016-sbc-usb-host.dtbo =20 +dtb-$(CONFIG_ARCH_QCOM) +=3D sar2130p-qar2130p.dtb + dtb-$(CONFIG_ARCH_QCOM) +=3D apq8016-sbc-usb-host.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D apq8016-sbc-d3-camera-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D apq8016-schneider-hmibsc.dtb diff --git a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts b/arch/arm64/bo= ot/dts/qcom/sar2130p-qar2130p.dts new file mode 100644 index 0000000000000000000000000000000000000000..fbf84877672ed9065db2ff6f2c8= bf742291deda6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts @@ -0,0 +1,551 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Linaro Limited + */ + +/dts-v1/; + +#include +#include +#include "sar2130p.dtsi" +#include "pm8150.dtsi" + +/ { + model =3D "Qualcomm Snapdragon AR2 Gen1 Smart Viewer Development Kit"; + compatible =3D "qcom,qar2130p", "qcom,sar2130p"; + chassis-type =3D "embedded"; + + aliases { + serial0 =3D &uart11; + serial1 =3D &uart7; + i2c0 =3D &i2c8; + i2c1 =3D &i2c10; + mmc1 =3D &sdhc_1; + spi0 =3D &spi0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + regulator-always-on; + }; + + /* pm3003a on I2C0, should not be controlled */ + vreg_ext_1p3: regulator-ext-1p3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_ext_1p3"; + regulator-min-microvolt =3D <1300000>; + regulator-max-microvolt =3D <1300000>; + regulator-always-on; + vin-supply =3D <&vph_pwr>; + }; + + /* EBI rail, used as LDO input, can not be part of PMIC config */ + vreg_s10a_0p89: regulator-s10a-0p89 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_s10a_0p89"; + regulator-min-microvolt =3D <890000>; + regulator-max-microvolt =3D <890000>; + regulator-always-on; + vin-supply =3D <&vph_pwr>; + }; + + thermal-zones { + sar2130p-thermal { + thermal-sensors =3D <&pm8150_adc_tm 1>; + + trips { + active-config0 { + temperature =3D <100000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + wifi-thermal { + thermal-sensors =3D <&pm8150_adc_tm 2>; + + trips { + active-config0 { + temperature =3D <52000>; + hysteresis =3D <4000>; + type =3D "passive"; + }; + }; + }; + + xo-thermal { + thermal-sensors =3D <&pm8150_adc_tm 0>; + + trips { + active-config0 { + temperature =3D <50000>; + hysteresis =3D <4000>; + type =3D "passive"; + }; + }; + }; + }; + + wcn7850-pmu { + compatible =3D "qcom,wcn7850-pmu"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wlan_en_state>, <&bt_en_state>; + + wlan-enable-gpios =3D <&tlmm 45 GPIO_ACTIVE_HIGH>; + bt-enable-gpios =3D <&tlmm 46 GPIO_ACTIVE_HIGH>; + + vdd-supply =3D <&vreg_s4a_0p95>; + vddio-supply =3D <&vreg_l15a_1p8>; + vddaon-supply =3D <&vreg_s4a_0p95>; + vdddig-supply =3D <&vreg_s4a_0p95>; + vddrfa1p2-supply =3D <&vreg_s4a_0p95>; + vddrfa1p8-supply =3D <&vreg_s5a_1p88>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name =3D "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name =3D "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name =3D "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name =3D "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name =3D "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name =3D "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name =3D "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name =3D "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name =3D "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name =3D "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id =3D "a"; + + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + vdd-s7-supply =3D <&vph_pwr>; + vdd-s8-supply =3D <&vph_pwr>; + vdd-s9-supply =3D <&vph_pwr>; + vdd-s10-supply =3D <&vph_pwr>; + vdd-l1-l8-l11-supply =3D <&vreg_s4a_0p95>; + vdd-l3-l4-l5-l18-supply =3D <&vreg_ext_1p3>; + vdd-l6-l9-supply =3D <&vreg_s10a_0p89>; + vdd-l7-l12-l14-l15-supply =3D <&vreg_s5a_1p88>; + + vreg_s4a_0p95: smps6 { + regulator-name =3D "vreg_s4a_0p95"; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <1170000>; + regulator-initial-mode =3D ; + }; + + vreg_s5a_1p88: smps5 { + regulator-name =3D "vreg_s5a_1p88"; + regulator-min-microvolt =3D <1856000>; + regulator-max-microvolt =3D <2040000>; + regulator-initial-mode =3D ; + }; + + vreg_l1a_0p91: ldo1 { + regulator-name =3D "vreg_l1a_0p91"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + + vreg_l2a_3p1: ldo2 { + regulator-name =3D "vreg_l2a_3p1"; + regulator-min-microvolt =3D <3080000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_l3a_1p2: ldo3 { + regulator-name =3D "vreg_l3a_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1304000>; + regulator-initial-mode =3D ; + }; + + /* ldo4 1.26 - system ? */ + + vreg_l5a_1p13: ldo5 { + regulator-name =3D "vreg_l5a_1p13"; + regulator-min-microvolt =3D <1128000>; + regulator-max-microvolt =3D <1170000>; + regulator-initial-mode =3D ; + }; + + vreg_l6a_0p6: ldo6 { + regulator-name =3D "vreg_l6a_0p6"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <650000>; + regulator-initial-mode =3D ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-name =3D "vreg_l7a_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1950000>; + regulator-initial-mode =3D ; + }; + + vreg_l8a_0p88: ldo8 { + regulator-name =3D "vreg_l8a_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <950000>; + regulator-initial-mode =3D ; + }; + + /* ldo9 - LCX */ + + vreg_l10a_2p95: ldo10 { + regulator-name =3D "vreg_l10a_2p95"; + regulator-min-microvolt =3D <2952000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + /* ldo11 - LMX */ + + vreg_l12a_1p8: ldo12 { + regulator-name =3D "vreg_l12a_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1880000>; + regulator-initial-mode =3D ; + }; + + /* no ldo13 */ + + vreg_l14a_1p8: ldo14 { + regulator-name =3D "vreg_l14a_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1880000>; + regulator-initial-mode =3D ; + }; + + vreg_l15a_1p8: ldo15 { + regulator-name =3D "vreg_l15a_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + /* no ldo16 - system */ + + vreg_l17a_3p26: ldo17 { + regulator-name =3D "vreg_l17a_3p26"; + regulator-min-microvolt =3D <3200000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_l18a_1p2: ldo18 { + regulator-name =3D "vreg_l18a_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1304000>; + regulator-initial-mode =3D ; + }; + }; + +}; + +&gpi_dma0 { + status =3D "okay"; +}; + +&gpi_dma1 { + status =3D "okay"; +}; + +&gpu { + status =3D "okay"; +}; + +&gpu_zap_shader { + firmware-name =3D "qcom/sar2130p/a620_zap.mbn"; +}; + +&pon_pwrkey { + status =3D "okay"; +}; + +&pon_resin { + status =3D "okay"; + + linux,code =3D ; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&i2c4 { + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c8 { + clock-frequency =3D <400000>; + status =3D "okay"; + + ptn3222: redriver@4f { + compatible =3D "nxp,ptn3222"; + reg =3D <0x4f>; + #phy-cells =3D <0>; + vdd3v3-supply =3D <&vreg_l2a_3p1>; + vdd1v8-supply =3D <&vreg_l15a_1p8>; + reset-gpios =3D <&tlmm 99 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c10 { + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&pcie0 { + perst-gpios =3D <&tlmm 55 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 57 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcieport0 { + wifi@0 { + compatible =3D "pci17cb,1107"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply =3D <&vreg_pmu_aon_0p59>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply =3D <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply =3D <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l8a_0p88>; + vdda-pll-supply =3D <&vreg_l3a_1p2>; + + status =3D "okay"; +}; + +&pm8150_adc { + channel@4c { + reg =3D ; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + label =3D "xo_therm"; + }; + + channel@4d { + reg =3D ; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + label =3D "skin_therm"; + }; + + channel@4e { + /* msm-5.10 uses ADC5_AMUX_THM2 / 0x0e, although there is a pullup */ + reg =3D ; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + label =3D "wifi_therm"; + }; +}; + +&pm8150_adc_tm { + status =3D "okay"; + + xo-therm@0 { + reg =3D <0>; + io-channels =3D <&pm8150_adc ADC5_XO_THERM_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us =3D <200>; + }; + + skin-therm@1 { + reg =3D <1>; + io-channels =3D <&pm8150_adc ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us =3D <200>; + }; + + wifi-therm@2 { + reg =3D <2>; + /* msm-5.10 uses ADC5_AMUX_THM2, although there is a pullup */ + io-channels =3D <&pm8150_adc ADC5_AMUX_THM2_100K_PU>; + qcom,hw-settle-time-us =3D <200>; + }; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/sar2130p/adsp.mbn"; + status =3D "okay"; +}; + +&sdhc_1 { + vmmc-supply =3D <&vreg_l10a_2p95>; + vqmmc-supply =3D <&vreg_l7a_1p8>; + + status =3D "okay"; +}; + +&tlmm { + bt_en_state: bt-enable-state { + pins =3D "gpio46"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; + + pcie0_default_state: pcie0-default-state { + perst-pins { + pins =3D "gpio55"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + clkreq-pins { + pins =3D "gpio56"; + function =3D "pcie0_clkreqn"; + drive-strength =3D <2>; + bias-pull-up; + }; + + wake-pins { + pins =3D "gpio57"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default-state { + perst-pins { + pins =3D "gpio58"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + clkreq-pins { + pins =3D "gpio59"; + function =3D "pcie1_clkreqn"; + drive-strength =3D <2>; + bias-pull-up; + }; + + wake-pins { + pins =3D "gpio60"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + wlan_en_state: wlan-enable-state { + pins =3D "gpio45"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; +}; + +&uart7 { + status =3D "okay"; + + bluetooth { + compatible =3D "qcom,wcn7850-bt"; + + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn>; + vddaon-supply =3D <&vreg_pmu_aon_0p59>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p8>; + + max-speed =3D <3200000>; + }; +}; + +&uart11 { + status =3D "okay"; +}; + +&usb_1 { + status =3D "okay"; +}; + +&usb_1_hsphy { + vdd-supply =3D <&vreg_l8a_0p88>; + vdda12-supply =3D <&vreg_l3a_1p2>; + + phys =3D <&ptn3222>; + + status =3D "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply =3D <&vreg_l3a_1p2>; + vdda-pll-supply =3D <&vreg_l1a_0p91>; + + status =3D "okay"; +}; --=20 2.39.5