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Wed, 30 Oct 2024 07:02:45 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49U72iYr008631 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Oct 2024 07:02:44 GMT Received: from [10.213.111.143] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 30 Oct 2024 00:02:38 -0700 From: Akhil P Oommen Date: Wed, 30 Oct 2024 12:32:02 +0530 Subject: [PATCH v3 1/2] arm64: dts: qcom: sa8775p: Add gpu and gmu nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241030-a663-gpu-support-v3-1-bdf1d9ce6021@quicinc.com> References: <20241030-a663-gpu-support-v3-0-bdf1d9ce6021@quicinc.com> In-Reply-To: <20241030-a663-gpu-support-v3-0-bdf1d9ce6021@quicinc.com> To: Rob Clark , Sean Paul , "Konrad Dybcio" , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , "Simona Vetter" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Connor Abbott CC: , , , , , Puranam V G Tejaswi , Akhil P Oommen X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; 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As of now all SKUs have the same GPU fmax, so there is no requirement of speed bin support. Signed-off-by: Puranam V G Tejaswi Signed-off-by: Akhil P Oommen Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 94 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 94 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index e8dbc8d820a6..c6cb18193787 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3072,6 +3072,100 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells =3D <1>; }; =20 + gpu: gpu@3d00000 { + compatible =3D "qcom,adreno-663.0", "qcom,adreno"; + reg =3D <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names =3D "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + interrupts =3D ; + iommus =3D <&adreno_smmu 0 0xc00>, + <&adreno_smmu 1 0xc00>; + operating-points-v2 =3D <&gpu_opp_table>; + qcom,gmu =3D <&gmu>; + interconnects =3D <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "gfx-mem"; + #cooling-cells =3D <2>; + + status =3D "disabled"; + + gpu_zap_shader: zap-shader { + memory-region =3D <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-405000000 { + opp-hz =3D /bits/ 64 <405000000>; + opp-level =3D ; + opp-peak-kBps =3D <5285156>; + }; + + opp-676000000 { + opp-hz =3D /bits/ 64 <676000000>; + opp-level =3D ; + opp-peak-kBps =3D <8171875>; + }; + + opp-778000000 { + opp-hz =3D /bits/ 64 <778000000>; + opp-level =3D ; + opp-peak-kBps =3D <10687500>; + }; + + opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-level =3D ; + opp-peak-kBps =3D <12484375>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible =3D "qcom,adreno-gmu-663.0", "qcom,adreno-gmu"; + reg =3D <0x0 0x03d6a000 0x0 0x34000>, + <0x0 0x03de0000 0x0 0x10000>, + <0x0 0x0b290000 0x0 0x10000>; + reg-names =3D "gmu", "rscc", "gmu_pdc"; + interrupts =3D , + ; + interrupt-names =3D "hfi", "gmu"; + clocks =3D <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names =3D "gmu", + "cxo", + "axi", + "memnoc", + "ahb", + "hub", + "smmu_vote"; + power-domains =3D <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names =3D "cx", + "gx"; + iommus =3D <&adreno_smmu 5 0xc00>; + operating-points-v2 =3D <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + opp-level =3D ; + }; + }; + }; + + gpucc: clock-controller@3d90000 { compatible =3D "qcom,sa8775p-gpucc"; reg =3D <0x0 0x03d90000 0x0 0xa000>; --=20 2.45.2