From nobody Mon Nov 25 08:33:42 2024 Received: from mail11.truemail.it (mail11.truemail.it [217.194.8.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D40051FF7A8; Tue, 29 Oct 2024 07:24:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.194.8.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730186696; cv=none; b=JITRA+0htrxNlfbpFTnF2x2pBy093bBe72Bigaw8bYW2Ah7pIWV49LGz0lWXkGQuaWnYFOmbGy6Mj6XGgETUpN1XAOreL4c1wfENLeFsuARt0QxfaAaWl1UVzKNoRqge7Plfwb2tH5CTFw/pujUZgVbgL93daCQiCBL+McFiFjU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730186696; c=relaxed/simple; bh=dD6sfEA6TyrR92IuEwIrvwGdiNhG++5AP5oCyAJBRv8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=aQc2lfkoZptLhfaqcNRnS6IUX7RgaTcZQDOxb2XZ+kihtPTGsQ4HrN//7/92gHHIaj7Myu0RLovqRtaTpDeLysmF8xbim4WSCxNpKXcfXMPn9kU/oCP1HUTQay/6grLDqCyJ1sCZtKU4PIiXRjOBtO3Gecquxty1XNL2kf3MP50= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dolcini.it; spf=pass smtp.mailfrom=dolcini.it; dkim=pass (2048-bit key) header.d=dolcini.it header.i=@dolcini.it header.b=mYBZ8O2c; arc=none smtp.client-ip=217.194.8.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dolcini.it Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=dolcini.it Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=dolcini.it header.i=@dolcini.it header.b="mYBZ8O2c" Received: from francesco-nb.pivistrello.it (93-49-2-63.ip317.fastwebnet.it [93.49.2.63]) by mail11.truemail.it (Postfix) with ESMTPA id 647481F9F5; Tue, 29 Oct 2024 08:24:49 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dolcini.it; s=default; t=1730186689; bh=zJNrAwAncRDPcYMxzosZep3z32xn7omnGmf2DkOscDA=; h=From:To:Subject; b=mYBZ8O2cH/93cCXsLZ5jlf8UCQuSLx6er4SbJxa+hFPMGCJG4XZXsQ0A6RXE3gEF+ TDO1EKFhduTCVcXCADWs7lN5KVkx5/cEt825kqniLcczjvj3ppQ8O6Btd8ZpShvYfI JYncPE4kcT9sHI2sLeLM27iaoTK3Io6zHXWOrJx2+i/XwyWhJbOWwfygJDkhNqGKh9 yYBcakeHLIvHKHHptER9emnTfGfRUvmko6NpUxmRXUSxb0pWFEKqQgMQ12ZMH3Gjgh 8nOL+QrzG7DlSFH5uAYH+KW/BMkJD9cPkwHBJa70dY5GTzCbb2m1I7KpDrHUxNKyT8 c815J4RrX3jVQ== From: Francesco Dolcini To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathias Nyman , Francesco Dolcini Cc: Parth Pancholi , linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 1/2] dt-bindings: usb: add TUSB73x0 PCIe Date: Tue, 29 Oct 2024 08:24:43 +0100 Message-Id: <20241029072444.8827-2-francesco@dolcini.it> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241029072444.8827-1-francesco@dolcini.it> References: <20241029072444.8827-1-francesco@dolcini.it> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Parth Pancholi Add device tree bindings for TI's TUSB73x0 PCIe-to-USB 3.0 xHCI host controller. The controller supports software configuration through PCIe registers, such as controlling the PWRONx polarity via the USB control register (E0h). Datasheet: https://www.ti.com/lit/ds/symlink/tusb7320.pdf Signed-off-by: Parth Pancholi Signed-off-by: Francesco Dolcini Reviewed-by: Krzysztof Kozlowski --- v5: - s/ti,tusb7320-pwron-active-high/ti,pwron-active-high/ v4: - add $ref: usb-xhci.yaml - description: wrap to 80 columns, add that the two variants use the same device ID - revise the example, based on comment from Rob and taking marvell,prestera.yaml as an example (this binding was reviewed and amended by Rob in the past). v3: use lowercase hex in compatible v2: rename property to ti,tusb7320-pwron-active-high and change type to flag --- .../bindings/usb/ti,tusb73x0-pci.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.y= aml diff --git a/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml b/D= ocumentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml new file mode 100644 index 000000000000..ddda734f36fb --- /dev/null +++ b/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/ti,tusb73x0-pci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TUSB73x0 USB 3.0 xHCI Host Controller (PCIe) + +maintainers: + - Francesco Dolcini + +description: + TUSB73x0 USB 3.0 xHCI Host Controller via PCIe x1 Gen2 interface. + The TUSB7320 supports up to two downstream ports, the TUSB7340 supports = up + to four downstream ports, both variants share the same PCI device ID. + +properties: + compatible: + const: pci104c,8241 + + reg: + maxItems: 1 + + ti,pwron-active-high: + $ref: /schemas/types.yaml#/definitions/flag + description: + Configure the polarity of the PWRONx# signals. When this is present,= the + PWRONx# pins are active high and their internal pull-down resistors = are + disabled. When this is absent, the PWRONx# pins are active low (defa= ult) + and their internal pull-down resistors are enabled. + +required: + - compatible + - reg + +allOf: + - $ref: usb-xhci.yaml + +additionalProperties: false + +examples: + - | + pcie@0 { + reg =3D <0x0 0x1000>; + ranges =3D <0x02000000 0x0 0x100000 0x10000000 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + + usb@0 { + compatible =3D "pci104c,8241"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + ti,pwron-active-high; + }; + }; --=20 2.39.5 From nobody Mon Nov 25 08:33:42 2024 Received: from mail11.truemail.it (mail11.truemail.it [217.194.8.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4751D2022DF; Tue, 29 Oct 2024 07:24:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.194.8.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730186695; cv=none; b=Yhus12AoHIlPPf55yKvZsRy8lXK8fma2e7uC7lk0QkuUHBXfHKpmLDHa3UHWTWfCQ+1Po4SIOTVJf15rp6spExfEdp+j1AO4+Hwqsj7g573OYnbxSx5O4nKX2U9nejG/0oIu+AEhYQNMgKh0a4lQKpZLI+qWkhXG8lTFzZv/olI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730186695; c=relaxed/simple; bh=bujN33g16oHNeeyO3ZGbViJYxBOYuYTm+DxN3be+hS4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YGmZ7Z36nrLF2CmVpNBaS8QfnXFNTWLrkVfhQRAN4It/iTkZfhDEQLR5s2JGKOt7e8IRHIbSbdXnlBSfGjXDUeMXPoBthazFCNooEcFZBXHKPgiSpHdc9yng+c6wOoxELHeGLKpu6kiliu/tV7dOGmePMZ4btLr080kBIfDin0Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dolcini.it; spf=pass smtp.mailfrom=dolcini.it; dkim=pass (2048-bit key) header.d=dolcini.it header.i=@dolcini.it header.b=PxiYcBfN; arc=none smtp.client-ip=217.194.8.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dolcini.it Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=dolcini.it Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=dolcini.it header.i=@dolcini.it header.b="PxiYcBfN" Received: from francesco-nb.pivistrello.it (93-49-2-63.ip317.fastwebnet.it [93.49.2.63]) by mail11.truemail.it (Postfix) with ESMTPA id EDDC91FA13; Tue, 29 Oct 2024 08:24:49 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dolcini.it; s=default; t=1730186690; bh=y6XwsU0U/5vhJTZLKZbpSfkUbG50QcLapUoV17QlMjw=; h=From:To:Subject; b=PxiYcBfN5S2vXfEE5CaOZ3S/wt/jww6iSYozhth0QP0jxRRQxJFgek6C7my4O14wf jcn5FgjCe7cik5V4cb7b0SPhsKoY9bz254AzsqndPLwC98EQxdwnTKGMII7v24YTbz ixPGNpoIUmDWmwhuIqIU6nca1Ss+FgqhjLWYsuM/B+Orz0z6X8SMMsFke5Pt+hlOWR GuUAMIe+YEhQ2472j3BAejkXMDkrsEbrIurp3ar9Gstk96A+aPY/WKvChjAwCuEFer I+omolGMhgoDD+i57vYLTaKy2o94hIqKiePsOMoPfhHvQdie4j90c3JmgGuezcR40x WV4bknbTrVCIw== From: Francesco Dolcini To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathias Nyman , Francesco Dolcini Cc: Parth Pancholi , linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 2/2] USB: xhci: add support for PWRON active high Date: Tue, 29 Oct 2024 08:24:44 +0100 Message-Id: <20241029072444.8827-3-francesco@dolcini.it> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241029072444.8827-1-francesco@dolcini.it> References: <20241029072444.8827-1-francesco@dolcini.it> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Parth Pancholi Some PCIe-to-USB controllers such as TI's TUSB73x0 3.0 xHCI host controller supports controlling the PWRONx polarity via the USB control register (E0h). Add support for device tree property ti,pwron-active-high which indicates PWRONx to be active high and configure the E0h register accordingly. This enables the software control for the TUSB73x0's PWRONx outputs with an inverted polarity from the default configuration which could be used as USB EN signals for the other hubs or devices. Signed-off-by: Parth Pancholi Signed-off-by: Francesco Dolcini --- v5:s/ti,tusb7320-pwron-active-high/ti,pwron-active-high/ v4: no changes v3: no changes v2: s/polarity-invert/active-high --- drivers/usb/host/xhci-pci.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index 91dccd25a551..39456ec268f5 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -641,6 +641,9 @@ int xhci_pci_common_probe(struct pci_dev *dev, const st= ruct pci_device_id *id) =20 dma_set_max_seg_size(&dev->dev, UINT_MAX); =20 + if (device_property_read_bool(&dev->dev, "ti,pwron-active-high")) + pci_clear_and_set_config_dword(dev, 0xE0, 0, 1 << 22); + return 0; =20 put_usb3_hcd: --=20 2.39.5