From nobody Mon Nov 25 06:53:49 2024 Received: from mail-pf1-f175.google.com (mail-pf1-f175.google.com [209.85.210.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2ACA1212D3B for ; Tue, 29 Oct 2024 23:44:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730245501; cv=none; b=u7K2momq8+JBRNnK5HldXTQxJLmFYkbhrHcQ89ZXDHlkAAY59P6jBlspF1HmQ5hASR8ThwnVL0JVS6kpUDTogoT5HKI8zB/YLXH9pf23F/f3mEbkZw/77YVXaeDskHxkX9OFrgh57jjroEKbfQL2GSkRYsTmAMn2COLhCBFSwyw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730245501; c=relaxed/simple; bh=Rvw7HPG+REQ+hDm9pcTpOm9qFEyGAVUHYNCGotsiHag=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Jx4Q4dXXdSQrvEetft8Rx8Wlo3jGPADoCRYlspRYV83VgeDmkxttqWgNSiGEpO2WPlK0t5ldAi4f3mFVvosbpJO6OGAUNeoUcMRk9IDJSpdaYXDDOeu7JNX8kY2L4b6nuWHQmTUprPwgS8E+PxIFHRNRSX/6vuw/YAHnYR2sLR4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=xjSXRhhc; arc=none smtp.client-ip=209.85.210.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="xjSXRhhc" Received: by mail-pf1-f175.google.com with SMTP id d2e1a72fcca58-71e79f73aaeso4229398b3a.3 for ; Tue, 29 Oct 2024 16:44:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1730245498; x=1730850298; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=MX17XgayDE8GvInbCjC/4NqKFQNSI1sjKyctPVZ+mGg=; b=xjSXRhhci7nMgZF4DlYc/Kz/gH3nEVhElnC8PCqjMMuAKKzaZn4xjWhizUUIOciRSX im8xtKFBKN26hX+wH9c6RkZSEMVm2phciYbYET0Dtb4nIsJ7/HF0at2LRTWnpGCWu+As XUHvMY6HO34A6cqz6sjTuPwpgCAa/5nGLK+xsezkUtAYbM+5MooA8ArL8eTEIB9dXCm/ rgi9907VpMWe5Ib8BykXfo5X1NPn4Uptx77smAdK0mxzxI8hZfES0Xd7YxHMtm1qLqi3 nW2LSvorMRkG5oTPl0BrvmKFokcnhG6li6SpNCc1QGD9s7eR//VDiIiRinBxvVuPtE2i sySg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730245498; x=1730850298; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MX17XgayDE8GvInbCjC/4NqKFQNSI1sjKyctPVZ+mGg=; b=Rs5YYXHOVGSiKGuqTb64LSBpZ5a1bFGtsue20bQQ8QGSJQ2ivgerUEJN7jhFSPZnQX E4+xb7Ghjz/BvtRiAEkApHSOxot0Ua8RKRyGANl5diFLcM7VrXGitOiw+we2fazoTTmc 55RMdCCLUdxccrahlmCRp2akWaLkJwEFg2XcJxvB+OLF5C9RsBGEXj0/MiUe9QJlprhg IShwgpz6oW4FK5t6EJRCvAhmbpalWS0COGXVs80oI54u6XqTVec+y4VrAWDIplzYs5QN 5B87DEZSOzOqhPctv3AUHV3iD09xo2JRePQfnG/ULEtz7Lb+U0xdq+pnNcccqgfInxAT k6RQ== X-Gm-Message-State: AOJu0Yy13VYSsX38Y36EWGSksQvLtK8RamkTT5HAeCMpsW15CyL4Y3jF DYAz9X2cOaNotMtfJnhXm2XGlCTCwRNPZOq9+IbJEU8NkE5jPcKi01j3AhIX710= X-Google-Smtp-Source: AGHT+IExoxYnLt1GvbT6MZVWFjKFOSbr7AEUolTL6dzHWvO6oME8gZh14LO3LJsC9IhYy2Z5JyMh8A== X-Received: by 2002:a05:6a00:4610:b0:71e:4fe4:282e with SMTP id d2e1a72fcca58-72063096385mr19719551b3a.28.1730245498419; Tue, 29 Oct 2024 16:44:58 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72057921863sm8157643b3a.33.2024.10.29.16.44.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 16:44:57 -0700 (PDT) From: Deepak Gupta Date: Tue, 29 Oct 2024 16:44:16 -0700 Subject: [PATCH v7 16/32] prctl: arch-agnostic prctl for shadow stack Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241029-v5_user_cfi_series-v7-16-2727ce9936cb@rivosinc.com> References: <20241029-v5_user_cfi_series-v7-0-2727ce9936cb@rivosinc.com> In-Reply-To: <20241029-v5_user_cfi_series-v7-0-2727ce9936cb@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta X-Mailer: b4 0.14.0 From: Mark Brown Three architectures (x86, aarch64, riscv) have announced support for shadow stacks with fairly similar functionality. While x86 is using arch_prctl() to control the functionality neither arm64 nor riscv uses that interface so this patch adds arch-agnostic prctl() support to get and set status of shadow stacks and lock the current configuration to prevent further changes, with support for turning on and off individual subfeatures so applications can limit their exposure to features that they do not need. The features are: - PR_SHADOW_STACK_ENABLE: Tracking and enforcement of shadow stacks, including allocation of a shadow stack if one is not already allocated. - PR_SHADOW_STACK_WRITE: Writes to specific addresses in the shadow stack. - PR_SHADOW_STACK_PUSH: Push additional values onto the shadow stack. - PR_SHADOW_STACK_DISABLE: Allow to disable shadow stack. Note once locked, disable must fail. These features are expected to be inherited by new threads and cleared on exec(), unknown features should be rejected for enable but accepted for locking (in order to allow for future proofing). This is based on a patch originally written by Deepak Gupta but later modified by Mark Brown for arm's GCS patch series. Signed-off-by: Mark Brown Signed-off-by: Deepak Gupta --- include/linux/mm.h | 3 +++ include/uapi/linux/prctl.h | 21 +++++++++++++++++++++ kernel/sys.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 54 insertions(+) diff --git a/include/linux/mm.h b/include/linux/mm.h index 57533b9cae95..54e2b3f1cc30 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -4146,6 +4146,9 @@ static inline bool pfn_is_unaccepted_memory(unsigned = long pfn) { return range_contains_unaccepted_memory(pfn << PAGE_SHIFT, PAGE_SIZE); } +int arch_get_shadow_stack_status(struct task_struct *t, unsigned long __us= er *status); +int arch_set_shadow_stack_status(struct task_struct *t, unsigned long stat= us); +int arch_lock_shadow_stack_status(struct task_struct *t, unsigned long sta= tus); =20 void vma_pgtable_walk_begin(struct vm_area_struct *vma); void vma_pgtable_walk_end(struct vm_area_struct *vma); diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index 35791791a879..b8d7b6361754 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -327,5 +327,26 @@ struct prctl_mm_map { # define PR_PPC_DEXCR_CTRL_SET_ONEXEC 0x8 /* Set the aspect on exec */ # define PR_PPC_DEXCR_CTRL_CLEAR_ONEXEC 0x10 /* Clear the aspect on exec */ # define PR_PPC_DEXCR_CTRL_MASK 0x1f +/* + * Get the current shadow stack configuration for the current thread, + * this will be the value configured via PR_SET_SHADOW_STACK_STATUS. + */ +#define PR_GET_SHADOW_STACK_STATUS 74 + +/* + * Set the current shadow stack configuration. Enabling the shadow + * stack will cause a shadow stack to be allocated for the thread. + */ +#define PR_SET_SHADOW_STACK_STATUS 75 +# define PR_SHADOW_STACK_ENABLE (1UL << 0) +# define PR_SHADOW_STACK_WRITE (1UL << 1) +# define PR_SHADOW_STACK_PUSH (1UL << 2) + +/* + * Prevent further changes to the specified shadow stack + * configuration. All bits may be locked via this call, including + * undefined bits. + */ +#define PR_LOCK_SHADOW_STACK_STATUS 76 =20 #endif /* _LINUX_PRCTL_H */ diff --git a/kernel/sys.c b/kernel/sys.c index 4da31f28fda8..3d38a9c7c5c9 100644 --- a/kernel/sys.c +++ b/kernel/sys.c @@ -2324,6 +2324,21 @@ int __weak arch_prctl_spec_ctrl_set(struct task_stru= ct *t, unsigned long which, return -EINVAL; } =20 +int __weak arch_get_shadow_stack_status(struct task_struct *t, unsigned lo= ng __user *status) +{ + return -EINVAL; +} + +int __weak arch_set_shadow_stack_status(struct task_struct *t, unsigned lo= ng status) +{ + return -EINVAL; +} + +int __weak arch_lock_shadow_stack_status(struct task_struct *t, unsigned l= ong status) +{ + return -EINVAL; +} + #define PR_IO_FLUSHER (PF_MEMALLOC_NOIO | PF_LOCAL_THROTTLE) =20 #ifdef CONFIG_ANON_VMA_NAME @@ -2784,6 +2799,21 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, a= rg2, unsigned long, arg3, case PR_RISCV_SET_ICACHE_FLUSH_CTX: error =3D RISCV_SET_ICACHE_FLUSH_CTX(arg2, arg3); break; + case PR_GET_SHADOW_STACK_STATUS: + if (arg3 || arg4 || arg5) + return -EINVAL; + error =3D arch_get_shadow_stack_status(me, (unsigned long __user *) arg2= ); + break; + case PR_SET_SHADOW_STACK_STATUS: + if (arg3 || arg4 || arg5) + return -EINVAL; + error =3D arch_set_shadow_stack_status(me, arg2); + break; + case PR_LOCK_SHADOW_STACK_STATUS: + if (arg3 || arg4 || arg5) + return -EINVAL; + error =3D arch_lock_shadow_stack_status(me, arg2); + break; default: error =3D -EINVAL; break; --=20 2.34.1