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Most system's bus fabric use 1:1 map between input and output address. but some hardware like i.MX8QXP doesn't use 1:1 map. See below diagram: =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=8C=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94= =82 =E2=94=82 IA: 0x8ff8_0000 =E2=94=82 =E2=94=82 =E2=94=82 CPU =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=96=BA=E2=94=82 =E2= =94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=96=BA=E2=94=9C=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 = =E2=94=82 PCI =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94= =82 =E2=94=82 =E2=94=82 IA: 0x8ff0_0000 =E2=94=82 =E2=94=82 = =E2=94=82 CPU Addr =E2=94=82 =E2=94=82 =E2=94=8C=E2=94=80=E2=96=BA=E2=94=9C=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82 =E2=94=82 Con= troller =E2=94=82 0x7ff8_0000=E2=94=80=E2=94=BC=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94= =82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2= =94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2= =94=82 =E2=94=82 =E2=94=82 PCI Addr 0x7ff0_0000=E2=94=80=E2=94=BC=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=98 =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80=E2= =94=80=E2=96=BA IOSpace =E2=94=80=E2=94=BC=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=96=BA =E2=94=82 =E2=94=82 =E2=94=82 =E2=94= =82 =E2=94=82 0 0x7000_0000=E2=94=80=E2=94=BC=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=96=BA=E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82 = =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=94=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=96=BA CfgSpace =E2=94=80= =E2=94=BC=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=96=BA BUS Fabric =E2=94=82 =E2=94=82 =E2= =94=82 0 =E2=94=82 =E2=94=82 =E2= =94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=96=BA MemSpace= =E2=94=80=E2=94=BC=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=96=BA IA: 0x8000_0000 =E2=94=82 =E2=94=82 = 0x8000_0000 =E2=94=94=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=98 bus@5f000000 { compatible =3D "simple-bus"; #address-cells =3D <1>; #size-cells =3D <1>; ranges =3D <0x80000000 0x0 0x70000000 0x10000000>; pcie@5f010000 { compatible =3D "fsl,imx8q-pcie"; reg =3D <0x5f010000 0x10000>, <0x8ff00000 0x80000>; reg-names =3D "dbi", "config"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; bus-range =3D <0x00 0xff>; ranges =3D <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; ... }; }; Term internal address (IA) here means the address just before PCIe controller. After ATU use this IA instead CPU address, cpu_addr_fixup() can be removed. Signed-off-by: Frank Li --- Add a resource_size_t parent_bus_addr local varible to fix 32bit build error. | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202410291546.kvgEWJv7-lkp@i= ntel.com/ Chagne from v5 to v6 -add comments for of_property_read_reg(). Change from v4 to v5 - remove confused 0x5f00_0000 range in sample dts. - reorder address at above diagram. Change from v3 to v4 - none Change from v2 to v3 - %s/cpu_untranslate_addr/parent_bus_addr/g - update diagram. - improve commit message. Change from v1 to v2 - update because patch1 change get untranslate address method. - add using_dtbus_info in case break back compatibility for exited platform. --- drivers/pci/controller/dwc/pcie-designware-host.c | 55 +++++++++++++++++++= +++- drivers/pci/controller/dwc/pcie-designware.h | 8 ++++ 2 files changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 3e41865c72904..ea01b7bda0a76 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -418,6 +418,34 @@ static void dw_pcie_host_request_msg_tlp_res(struct dw= _pcie_rp *pp) } } =20 +static int dw_pcie_get_untranslate_addr(struct dw_pcie *pci, resource_size= _t pci_addr, + resource_size_t *i_addr) +{ + struct device *dev =3D pci->dev; + struct device_node *np =3D dev->of_node; + struct of_range_parser parser; + struct of_range range; + int ret; + + if (!pci->using_dtbus_info) { + *i_addr =3D pci_addr; + return 0; + } + + ret =3D of_range_parser_init(&parser, np); + if (ret) + return ret; + + for_each_of_pci_range(&parser, &range) { + if (pci_addr =3D=3D range.bus_addr) { + *i_addr =3D range.parent_bus_addr; + break; + } + } + + return 0; +} + int dw_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); @@ -427,6 +455,7 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) struct resource_entry *win; struct pci_host_bridge *bridge; struct resource *res; + int index; int ret; =20 raw_spin_lock_init(&pp->lock); @@ -440,6 +469,20 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) pp->cfg0_size =3D resource_size(res); pp->cfg0_base =3D res->start; =20 + if (pci->using_dtbus_info) { + index =3D of_property_match_string(np, "reg-names", "config"); + if (index < 0) + return -EINVAL; + /* + * Retrieve the parent bus address of PCI config space. + * If the parent bus ranges in the device tree provide + * the correct address conversion information, set + * 'using_dtbus_info' to true, The 'cpu_addr_fixup()' + * can be eliminated. + */ + of_property_read_reg(np, index, &pp->cfg0_base, NULL); + } + pp->va_cfg0_base =3D devm_pci_remap_cfg_resource(dev, res); if (IS_ERR(pp->va_cfg0_base)) return PTR_ERR(pp->va_cfg0_base); @@ -462,6 +505,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) pp->io_base =3D pci_pio_to_address(win->res->start); } =20 + if (dw_pcie_get_untranslate_addr(pci, pp->io_bus_addr, &pp->io_base)) + return -ENODEV; + /* Set default bus ops */ bridge->ops =3D &dw_pcie_ops; bridge->child_ops =3D &dw_child_pcie_ops; @@ -722,6 +768,8 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) =20 i =3D 0; resource_list_for_each_entry(entry, &pp->bridge->windows) { + resource_size_t parent_bus_addr; + if (resource_type(entry->res) !=3D IORESOURCE_MEM) continue; =20 @@ -730,9 +778,14 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) =20 atu.index =3D i; atu.type =3D PCIE_ATU_TYPE_MEM; - atu.cpu_addr =3D entry->res->start; + parent_bus_addr =3D entry->res->start; atu.pci_addr =3D entry->res->start - entry->offset; =20 + if (dw_pcie_get_untranslate_addr(pci, entry->res->start, &parent_bus_add= r)) + return -EINVAL; + + atu.cpu_addr =3D parent_bus_addr; + /* Adjust iATU size if MSG TLP region was allocated before */ if (pp->msg_res && pp->msg_res->parent =3D=3D entry->res) atu.size =3D resource_size(entry->res) - diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 347ab74ac35aa..f8067393ad35a 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -463,6 +463,14 @@ struct dw_pcie { struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS]; struct gpio_desc *pe_rst; bool suspended; + /* + * Use device tree 'ranges' property of bus node instead using + * cpu_addr_fixup(). Some old platform dts 'ranges' in bus node may not + * reflect real hardware's behavior. In case break these platform back + * compatibility, add below flags. Set it true if dts already correct + * indicate bus fabric address convert. + */ + bool using_dtbus_info; }; =20 #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) --=20 2.34.1