From nobody Sat Feb 7 06:50:23 2026 Received: from mail-lf1-f43.google.com (mail-lf1-f43.google.com [209.85.167.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BD6B20CCDA for ; Tue, 29 Oct 2024 10:53:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730199205; cv=none; b=Ys1t7VQMTN2jQ+eKedbKp2ESnfda0ga8wFCP9NK2d4oFkVOybWYY/Vk2ypcq50uUn6kvjhD0XWfHsFNcQyXfpGSu2dMT1hf4p5J8/6JGqipDTiEXc0tjSxhaw1ujhF46gyiLG0LImvnAo5k0fPGu/4vwHQikb3akuJdv6Ii+Zes= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730199205; c=relaxed/simple; bh=Qsa08BehM4uts93sI8Y9iubQvhsHZG2Sg6J31UXi3tM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iuN8x5dQfbHdk0X5fKo/Zn1CMkfC9s2LRXNSFW2MFaNXfqm4jHHmn+EKychZXLsn5uaxgNpcovv65+YWaQxUIgFMvQut7t+DBM/OW/fLhVcgn+zPoK1Y16ORUm4UEZhhRy1A9Vdfe+/q0W4AKtF3sLQJUoEIv4po1fcGCNZX3Jw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=LdAnZ/uR; arc=none smtp.client-ip=209.85.167.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="LdAnZ/uR" Received: by mail-lf1-f43.google.com with SMTP id 2adb3069b0e04-53a007743e7so6044161e87.1 for ; Tue, 29 Oct 2024 03:53:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1730199201; x=1730804001; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=4s7yTStZNPQghs61B8MN+wTLfopUv2dudvbP9oK+hzk=; b=LdAnZ/uRdG6AeFaYmfuh/wWVAnVWuypsHdezhqvMnoTyUtBHTvYrwPq7rH8liZARgF RisMpxmjJB/RFMz1LQ2ES/Wl8qgFvdvkEaZW6i3OHlEwBfj0b4k8idY9HoUukxeFul6L ENmFmo4WBtDAwr0XrIHs6Von1u68yt07Wt0H/FKNNfWxyGuJU2440MiTgCFckYTf3Zsx iF+1L8vC6vwDHholhmu2XuBf7zlTBYjHmqKpdx1rsOyasws5lRJPmANEa3Izy5ed4YVP f9Ktpkh+ItjSPmE20d0aXdfU4efc0fCaN0xnsnXgzAvZonesXswuwVo5VK4AhM3NY/Ti WFpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730199201; x=1730804001; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4s7yTStZNPQghs61B8MN+wTLfopUv2dudvbP9oK+hzk=; b=pCztKOJqVEzPFLTgtDs5EudAVqOBOfQ9VDD17zTow2us8j/xjQ5luFpGT8jSxJGx2f eCJNqWqzamYxVHXq5xp5HLDONrON4vVFl5SOA5786RFxHZ+DsrJS9ngW1LdgWIuhNvXn lhBJztLpfjiMSfvQiDQ9NnivWQEcqE3GnbP3/Zv18wBrGNzmSOsuWkuc46KiCx4+7Jlb XYDvRIp+V/QhdA687FNsiUjEUVbpvQVIULrHU2ANhfuNrbe6yahrg8LMDJbzOuaVXN9J 3TmeVQipFDhEL7TahOC92OFEEFRLfby4+QmnW3MPeUx+kCPwZ/VTS7RQnFm5BlD/AaPh Jd+A== X-Forwarded-Encrypted: i=1; AJvYcCXVxgvqP2GZnZHEUipdpKfskMqKeAtco4J7TawzRy6VB1pIMHmgNaUv1nzkXPy6AP2f1qbLKL5CTga/yxU=@vger.kernel.org X-Gm-Message-State: AOJu0Yw8l+ejLD/hPfSPviaOOjDHMMUBiBM8z7kC1x+RUzlSirDg6FAG HTWA124+Xtq8epATrUWXDWDIXgOtKF6IHqiv2/w9l66CAgaQobkM0rAdbqXbtCo= X-Google-Smtp-Source: AGHT+IElXNTIUEjBzs2hSzfFmPti763QWvOuxnOHRmGwE5++Rd45XLgtaXunwBM8zueTxRgHduPWMA== X-Received: by 2002:a05:6512:104a:b0:539:f4ab:5638 with SMTP id 2adb3069b0e04-53b34c466d0mr4122591e87.60.1730199201347; Tue, 29 Oct 2024 03:53:21 -0700 (PDT) Received: from lino.lan ([85.235.12.238]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53b2e12452fsm1351307e87.73.2024.10.29.03.53.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 03:53:20 -0700 (PDT) From: Linus Walleij Date: Tue, 29 Oct 2024 11:52:59 +0100 Subject: [PATCH RFC v2 19/28] ARM: entry: Remove fast and offset register restore Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241029-arm-generic-entry-v2-19-573519abef38@linaro.org> References: <20241029-arm-generic-entry-v2-0-573519abef38@linaro.org> In-Reply-To: <20241029-arm-generic-entry-v2-0-573519abef38@linaro.org> To: Oleg Nesterov , Russell King , Kees Cook , Andy Lutomirski , Will Drewry , Frederic Weisbecker , "Paul E. McKenney" , Jinjie Ruan , Arnd Bergmann , Ard Biesheuvel , Al Viro Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linus Walleij X-Mailer: b4 0.14.0 Now all remaining invocations of restore_user_regs has fast =3D 0 and offset =3D 0 set, so drop these parameters to the macro. Signed-off-by: Linus Walleij --- arch/arm/kernel/entry-armv.S | 2 +- arch/arm/kernel/entry-common.S | 2 +- arch/arm/kernel/entry-header.S | 29 +++++++++-------------------- 3 files changed, 11 insertions(+), 22 deletions(-) diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 09ce1be1f677..bd468d58dc02 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -496,7 +496,7 @@ __fiq_usr: mov r0, sp @ struct pt_regs *regs bl handle_fiq_as_nmi get_thread_info tsk - restore_user_regs fast =3D 0, offset =3D 0 + restore_user_regs UNWIND(.fnend ) ENDPROC(__fiq_usr) =20 diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index dddbd6ba1eb9..d27e34d7e97a 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -81,7 +81,7 @@ no_work_pending: #ifdef CONFIG_GCC_PLUGIN_STACKLEAK bl stackleak_erase_on_task_stack #endif - restore_user_regs fast =3D 0, offset =3D 0 + restore_user_regs ENDPROC(ret_to_user_from_irq) ENDPROC(ret_to_user) =20 diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S index 50c0b55adc74..51c7f93c1ded 100644 --- a/arch/arm/kernel/entry-header.S +++ b/arch/arm/kernel/entry-header.S @@ -290,7 +290,7 @@ .endm =20 =20 - .macro restore_user_regs, fast =3D 0, offset =3D 0 + .macro restore_user_regs #if defined(CONFIG_CPU_32v6K) && \ (!defined(CONFIG_CPU_V6) || defined(CONFIG_SMP)) #ifdef CONFIG_CPU_V6 @@ -309,8 +309,8 @@ ALT_UP_B(.L1_\@) #ifndef CONFIG_THUMB2_KERNEL @ ARM mode restore mov r2, sp - ldr r1, [r2, #\offset + S_PSR] @ get calling cpsr - ldr lr, [r2, #\offset + S_PC]! @ get pc + ldr r1, [r2, S_PSR] @ get calling cpsr + ldr lr, [r2, S_PC]! @ get pc tst r1, #PSR_I_BIT | 0x0f bne 1f msr spsr_cxsf, r1 @ save in spsr_svc @@ -318,31 +318,24 @@ ALT_UP_B(.L1_\@) @ We must avoid clrex due to Cortex-A15 erratum #830321 strex r1, r2, [r2] @ clear the exclusive monitor #endif - .if \fast - ldmdb r2, {r1 - lr}^ @ get calling r1 - lr - .else ldmdb r2, {r0 - lr}^ @ get calling r0 - lr - .endif mov r0, r0 @ ARMv5T and earlier require a nop @ after ldm {}^ - add sp, sp, #\offset + PT_REGS_SIZE + add sp, sp, #PT_REGS_SIZE movs pc, lr @ return & move spsr_svc into cpsr 1: bug "Returning to usermode but unexpected PSR bits set?", \@ #elif defined(CONFIG_CPU_V7M) @ V7M restore. @ Note that we don't need to do clrex here as clearing the local @ monitor is part of the exception entry and exit sequence. - .if \offset - add sp, #\offset - .endif - v7m_exception_slow_exit ret_r0 =3D \fast + v7m_exception_slow_exit ret_r0 =3D 0 #else @ Thumb mode restore mov r2, sp - load_user_sp_lr r2, r3, \offset + S_SP @ calling sp, lr - ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr - ldr lr, [sp, #\offset + S_PC] @ get pc - add sp, sp, #\offset + S_SP + load_user_sp_lr r2, r3, S_SP @ calling sp, lr + ldr r1, [sp, S_PSR] @ get calling cpsr + ldr lr, [sp, S_PC] @ get pc + add sp, sp, S_SP tst r1, #PSR_I_BIT | 0x0f bne 1f msr spsr_cxsf, r1 @ save in spsr_svc @@ -350,11 +343,7 @@ ALT_UP_B(.L1_\@) @ We must avoid clrex due to Cortex-A15 erratum #830321 strex r1, r2, [sp] @ clear the exclusive monitor =20 - .if \fast - ldmdb sp, {r1 - r12} @ get calling r1 - r12 - .else ldmdb sp, {r0 - r12} @ get calling r0 - r12 - .endif add sp, sp, #PT_REGS_SIZE - S_SP movs pc, lr @ return & move spsr_svc into cpsr 1: bug "Returning to usermode but unexpected PSR bits set?", \@ --=20 2.46.2