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Some clocks, like those in the CRU block, require specific sequences for enabling/disabling, making them incompatible with standard Runtime PM handling. For instance, initializing the CSI-2 D-PHY involves toggling individual clocks, which prevents the use of Runtime PM. Introduce a `no_pm` flag in the `mod_clock` and `rzv2h_mod_clk` structures to indicate clocks that do not support PM. Add a helper function `rzv2h_cpg_is_pm_clk()` to determine if a clock should be managed by Runtime PM based on this flag. Define new macros like `DEF_MOD_NO_PM` for easier specification of such clocks. Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/rzv2h-cpg.c | 37 +++++++++++++++++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.h | 12 ++++++++--- 2 files changed, 46 insertions(+), 3 deletions(-) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cp= g.c index b524a9d33610..ed45dbc1cc40 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -98,6 +98,7 @@ struct pll_clk { * * @priv: CPG private data * @hw: handle between common and hardware-specific interfaces + * @no_pm: flag to indicate PM is not supported * @on_index: register offset * @on_bit: ON/MON bit * @mon_index: monitor register offset @@ -106,6 +107,7 @@ struct pll_clk { struct mod_clock { struct rzv2h_cpg_priv *priv; struct clk_hw hw; + bool no_pm; u8 on_index; u8 on_bit; s8 mon_index; @@ -541,6 +543,7 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *= mod, clock->on_bit =3D mod->on_bit; clock->mon_index =3D mod->mon_index; clock->mon_bit =3D mod->mon_bit; + clock->no_pm =3D mod->no_pm; clock->priv =3D priv; clock->hw.init =3D &init; =20 @@ -658,6 +661,32 @@ static int rzv2h_cpg_reset_controller_register(struct = rzv2h_cpg_priv *priv) return devm_reset_controller_register(priv->dev, &priv->rcdev); } =20 +static bool rzv2h_cpg_is_pm_clk(struct rzv2h_cpg_priv *priv, + const struct of_phandle_args *clkspec) +{ + struct mod_clock *clock; + struct clk_hw *hw; + unsigned int id; + + if (clkspec->args_count !=3D 2) + return true; + + id =3D clkspec->args[1]; + if (clkspec->args[0] !=3D CPG_MOD || + id >=3D priv->num_core_clks + priv->num_mod_clks) + return true; + + if (priv->clks[priv->num_core_clks + id] =3D=3D ERR_PTR(-ENOENT)) + return true; + + hw =3D __clk_get_hw(priv->clks[priv->num_core_clks + id]); + clock =3D to_mod_clock(hw); + if (clock->no_pm) + return false; + + return true; +} + /** * struct rzv2h_cpg_pd - RZ/V2H power domain data structure * @priv: pointer to CPG private data structure @@ -670,6 +699,8 @@ struct rzv2h_cpg_pd { =20 static int rzv2h_cpg_attach_dev(struct generic_pm_domain *domain, struct d= evice *dev) { + struct rzv2h_cpg_pd *pd =3D container_of(domain, struct rzv2h_cpg_pd, gen= pd); + struct rzv2h_cpg_priv *priv =3D pd->priv; struct device_node *np =3D dev->of_node; struct of_phandle_args clkspec; bool once =3D true; @@ -679,6 +710,12 @@ static int rzv2h_cpg_attach_dev(struct generic_pm_doma= in *domain, struct device =20 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, &clkspec)) { + if (!rzv2h_cpg_is_pm_clk(priv, &clkspec)) { + of_node_put(clkspec.np); + i++; + continue; + } + if (once) { once =3D false; error =3D pm_clk_create(dev); diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cp= g.h index 819029c81904..0723df4c1134 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -100,6 +100,7 @@ enum clk_types { * @name: handle between common and hardware-specific interfaces * @parent: id of parent clock * @critical: flag to indicate the clock is critical + * @no_pm: flag to indicate PM is not supported * @on_index: control register index * @on_bit: ON bit * @mon_index: monitor register index @@ -109,17 +110,19 @@ struct rzv2h_mod_clk { const char *name; u16 parent; bool critical; + bool no_pm; u8 on_index; u8 on_bit; s8 mon_index; u8 mon_bit; }; =20 -#define DEF_MOD_BASE(_name, _parent, _critical, _onindex, _onbit, _moninde= x, _monbit) \ +#define DEF_MOD_BASE(_name, _parent, _critical, _no_pm, _onindex, _onbit, = _monindex, _monbit) \ { \ .name =3D (_name), \ .parent =3D (_parent), \ .critical =3D (_critical), \ + .no_pm =3D (_no_pm), \ .on_index =3D (_onindex), \ .on_bit =3D (_onbit), \ .mon_index =3D (_monindex), \ @@ -127,10 +130,13 @@ struct rzv2h_mod_clk { } =20 #define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit) \ - DEF_MOD_BASE(_name, _parent, false, _onindex, _onbit, _monindex, _monbit) + DEF_MOD_BASE(_name, _parent, false, false, _onindex, _onbit, _monindex, _= monbit) =20 #define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _mon= bit) \ - DEF_MOD_BASE(_name, _parent, true, _onindex, _onbit, _monindex, _monbit) + DEF_MOD_BASE(_name, _parent, true, false, _onindex, _onbit, _monindex, _m= onbit) + +#define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit= ) \ + DEF_MOD_BASE(_name, _parent, false, true, _onindex, _onbit, _monindex, _m= onbit) =20 /** * struct rzv2h_reset - Reset definitions --=20 2.43.0