From nobody Mon Nov 25 11:29:04 2024 Received: from mail-ed1-f45.google.com (mail-ed1-f45.google.com [209.85.208.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C97B91E0B61; Mon, 28 Oct 2024 17:59:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730138399; cv=none; b=n7RrlII9euzpYn6abIzzlEgEk//cmV3Mj0jWXHx9Y4cnq+u2DxbjgqCF8Fb789A2vGdk8HKVTtVD7TmTOBqJiX2F20kr0gWUjpz+cICSwS1aXKiRNBawbo09wT0pSBF91l1GVZPpYlVdlP9d+ENupoVVuvhP+PKt+FnMByURTUY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730138399; c=relaxed/simple; bh=GOD8XfkJz4zsO80sDemTkSTBWYgvVnNxTFCnWXZ0gII=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TT4bHmBX+7n8jcZ81901Ow7EkM8DmybXGtsVThA2plRXaIyMwYW/OpRkNm9NhIfpjYnqYavwexS95XYt8QJLdKBug1RFnDxqNyActkUrAyfafd9aolV0Dsz52PlB4CaiGnXdxI31D035KGrSVyTDkJolfyaXdtdky54L9rEVK0c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=mDcvWb1K; arc=none smtp.client-ip=209.85.208.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="mDcvWb1K" Received: by mail-ed1-f45.google.com with SMTP id 4fb4d7f45d1cf-5c935d99dc5so5240379a12.1; Mon, 28 Oct 2024 10:59:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730138395; x=1730743195; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4jHqaxSvoWLgnCFeLMCaBBBf/bAjTs2yGSSBO7ssnOk=; b=mDcvWb1K5JZYShm5ymJ2Nno1ysF/igrAOJoXtqYyy7e9q8oU3HfkifN/G+2WsSTaEM q90o7jx2dXKSS83flbyOcpz2ysbk3gBWgFUaMouooMQd3K580ugDELi37cfZWaaNdtjw uXU4FUglGcqF9ecAW2gX7Cxg5NmicZvVdyadqvhziZqvmYKYCUoCDJGeo8gHOtaQDAjs QQEDGfv0IA5BBTQGBdfjza5hhD/SoMB+0v9G/R6wabT1dywCioaGXT7dZiVAr+KnfHTD uETuhPD6A52SMN9praHYMgeTE9+yspUmE6fwe1J7NRAaq4aw7RQfSt0IjFPUlK9qA8CA zLYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730138395; x=1730743195; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4jHqaxSvoWLgnCFeLMCaBBBf/bAjTs2yGSSBO7ssnOk=; b=bWMZIc1woW2La9dWJb3QsPTm7vAdLOcF0J3eNeiyhvX1HUh5Fn+TLBeHcJq2Khyt4p av77O8uexoJBf3OXi5ycoHApVqV9sLSHexE3K+008LD6T0q8UjWB8KjtjDj+WSJA7SH7 EuO0M0OqXoGTwnqOq9J0em7E9DkQ/9smT/vFCy78RVDObPyM3vjBmzD25oGN23HFkF6/ T3sQHpdXYpuCBVOr3FSfXW5XseFud8UrKKtCsG5KkgQTbJSZ64KMPvFvcOaNckx+xa7M jAB8iES+FQqBYlXajSd9oTX+XI2CTuOZ/a5rgDHrKrUkx3VNRKzKsCsSJsbs62IMtYwy ZuRA== X-Forwarded-Encrypted: i=1; AJvYcCWsbCB3bJpaypcCRH4BkDGiuvmkqrxMXtb4wyq/bbrVKEHKc9Dj7B+ol6srI2WbeUXIepYGrH9YCoOdAfPT@vger.kernel.org, AJvYcCX83N7kDMuOBTpdjG5IccP+auF8yXJtmK9Gk/h0eqpt2RwrwkE3yAA3k0+cF3OHrwbG/JqJMyn/7bCKRg==@vger.kernel.org, AJvYcCXLDNlJ4RZkPwNhJCzrAmXumkTCXhSPKJxQa2+aTZwjdDsDGiaVUP0qKTNMRJz1BioJdDsBpbPLkKay@vger.kernel.org X-Gm-Message-State: AOJu0YzFMQTZRDCxGN7ChmCs+yZrO0UTwth2hKTSlOSde7lzXWIGqHod 5htuiKp1VP+V2BnB0Cuyx9RHCUURe1tw0OdwZorH+HZEcN7PY7ae X-Google-Smtp-Source: AGHT+IEmeSOtc9Iyr4lHeC6Hz0t0cL8os8+bzqNv8I7gV7skDce9pH2TrwhZJlfkeIGSdqRoh0xSHA== X-Received: by 2002:a17:907:6d0d:b0:a9a:147d:fe9c with SMTP id a640c23a62f3a-a9de61d5d59mr865717766b.43.1730138394960; Mon, 28 Oct 2024 10:59:54 -0700 (PDT) Received: from localhost.localdomain ([79.175.114.8]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b1dfbdfe2sm396990766b.36.2024.10.28.10.59.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Oct 2024 10:59:54 -0700 (PDT) From: Aleksandar Rikalo To: Thomas Bogendoerfer Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vladimir Kondratiev , Gregory CLEMENT , Theo Lebrun , Arnd Bergmann , devicetree@vger.kernel.org, Djordje Todorovic , Chao-ying Fu , Daniel Lezcano , Geert Uytterhoeven , Greg Ungerer , Hauke Mehrtens , Ilya Lipnitskiy , Jiaxun Yang , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Marc Zyngier , Paul Burton , Peter Zijlstra , Serge Semin , Tiezhu Yang , Aleksandar Rikalo Subject: [PATCH v8 08/13] MIPS: CPS: Introduce struct cluster_boot_config Date: Mon, 28 Oct 2024 18:59:30 +0100 Message-Id: <20241028175935.51250-9-arikalo@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241028175935.51250-1-arikalo@gmail.com> References: <20241028175935.51250-1-arikalo@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Paul Burton In preparation for supporting multi-cluster systems, introduce a struct cluster_boot_config as an extra layer in the boot configuration maintained by the MIPS Coherent Processing System (CPS) SMP implementation. For now only one struct cluster_boot_config will be allocated & we'll simply defererence its core_config field to find the struct core_boot_config array which can be used to boot as usual. Signed-off-by: Paul Burton Signed-off-by: Dragan Mladjenovic Signed-off-by: Aleksandar Rikalo Tested-by: Serge Semin Tested-by: Gregory CLEMENT --- arch/mips/include/asm/smp-cps.h | 6 ++- arch/mips/kernel/asm-offsets.c | 3 ++ arch/mips/kernel/cps-vec.S | 19 ++++++-- arch/mips/kernel/pm-cps.c | 5 +- arch/mips/kernel/smp-cps.c | 82 +++++++++++++++++++++------------ 5 files changed, 81 insertions(+), 34 deletions(-) diff --git a/arch/mips/include/asm/smp-cps.h b/arch/mips/include/asm/smp-cp= s.h index ab94e50f62b8..a629e948a6fd 100644 --- a/arch/mips/include/asm/smp-cps.h +++ b/arch/mips/include/asm/smp-cps.h @@ -22,7 +22,11 @@ struct core_boot_config { struct vpe_boot_config *vpe_config; }; =20 -extern struct core_boot_config *mips_cps_core_bootcfg; +struct cluster_boot_config { + struct core_boot_config *core_config; +}; + +extern struct cluster_boot_config *mips_cps_cluster_bootcfg; =20 extern void mips_cps_core_boot(int cca, void __iomem *gcr_base); extern void mips_cps_core_init(void); diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index cb1045ebab06..b29944160b28 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c @@ -404,6 +404,9 @@ void output_cps_defines(void) { COMMENT(" MIPS CPS offsets. "); =20 + OFFSET(CLUSTERBOOTCFG_CORECONFIG, cluster_boot_config, core_config); + DEFINE(CLUSTERBOOTCFG_SIZE, sizeof(struct cluster_boot_config)); + OFFSET(COREBOOTCFG_VPEMASK, core_boot_config, vpe_mask); OFFSET(COREBOOTCFG_VPECONFIG, core_boot_config, vpe_config); DEFINE(COREBOOTCFG_SIZE, sizeof(struct core_boot_config)); diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index f876309130ad..2ae7034a3d5c 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -19,6 +19,10 @@ #define GCR_CPC_BASE_OFS 0x0088 #define GCR_CL_COHERENCE_OFS 0x2008 #define GCR_CL_ID_OFS 0x2028 +#define CM3_GCR_Cx_ID_CLUSTER_SHF 8 +#define CM3_GCR_Cx_ID_CLUSTER_MSK (0xff << 8) +#define CM3_GCR_Cx_ID_CORENUM_SHF 0 +#define CM3_GCR_Cx_ID_CORENUM_MSK (0xff << 0) =20 #define CPC_CL_VC_STOP_OFS 0x2020 #define CPC_CL_VC_RUN_OFS 0x2028 @@ -271,12 +275,21 @@ LEAF(mips_cps_core_init) */ LEAF(mips_cps_get_bootcfg) /* Calculate a pointer to this cores struct core_boot_config */ + PTR_LA v0, mips_cps_cluster_bootcfg + PTR_L v0, 0(v0) lw t0, GCR_CL_ID_OFS(s1) +#ifdef CONFIG_CPU_MIPSR6 + ext t1, t0, CM3_GCR_Cx_ID_CLUSTER_SHF, 8 + li t2, CLUSTERBOOTCFG_SIZE + mul t1, t1, t2 + PTR_ADDU \ + v0, v0, t1 +#endif + PTR_L v0, CLUSTERBOOTCFG_CORECONFIG(v0) + andi t0, t0, CM3_GCR_Cx_ID_CORENUM_MSK li t1, COREBOOTCFG_SIZE mul t0, t0, t1 - PTR_LA t1, mips_cps_core_bootcfg - PTR_L t1, 0(t1) - PTR_ADDU v0, t0, t1 + PTR_ADDU v0, v0, t0 =20 /* Calculate this VPEs ID. If the core doesn't support MT use 0 */ li t9, 0 diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c index 9369a8dc385e..3de0e05e0511 100644 --- a/arch/mips/kernel/pm-cps.c +++ b/arch/mips/kernel/pm-cps.c @@ -101,12 +101,14 @@ static void coupled_barrier(atomic_t *a, unsigned onl= ine) int cps_pm_enter_state(enum cps_pm_state state) { unsigned cpu =3D smp_processor_id(); + unsigned int cluster =3D cpu_cluster(¤t_cpu_data); unsigned core =3D cpu_core(¤t_cpu_data); unsigned online, left; cpumask_t *coupled_mask =3D this_cpu_ptr(&online_coupled); u32 *core_ready_count, *nc_core_ready_count; void *nc_addr; cps_nc_entry_fn entry; + struct cluster_boot_config *cluster_cfg; struct core_boot_config *core_cfg; struct vpe_boot_config *vpe_cfg; atomic_t *barrier; @@ -136,7 +138,8 @@ int cps_pm_enter_state(enum cps_pm_state state) if (!mips_cps_smp_in_use()) return -EINVAL; =20 - core_cfg =3D &mips_cps_core_bootcfg[core]; + cluster_cfg =3D &mips_cps_cluster_bootcfg[cluster]; + core_cfg =3D &cluster_cfg->core_config[core]; vpe_cfg =3D &core_cfg->vpe_config[cpu_vpe_id(¤t_cpu_data)]; vpe_cfg->pc =3D (unsigned long)mips_cps_pm_restore; vpe_cfg->gp =3D (unsigned long)current_thread_info(); diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 395622c37325..f71e2bb58318 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -40,7 +40,7 @@ static DECLARE_BITMAP(core_power, NR_CPUS); static uint32_t core_entry_reg; static phys_addr_t cps_vec_pa; =20 -struct core_boot_config *mips_cps_core_bootcfg; +struct cluster_boot_config *mips_cps_cluster_bootcfg; =20 static unsigned __init core_vpe_count(unsigned int cluster, unsigned core) { @@ -212,8 +212,10 @@ static void __init cps_smp_setup(void) =20 static void __init cps_prepare_cpus(unsigned int max_cpus) { - unsigned ncores, core_vpes, c, cca; + unsigned int nclusters, ncores, core_vpes, c, cl, cca; bool cca_unsuitable, cores_limited; + struct cluster_boot_config *cluster_bootcfg; + struct core_boot_config *core_bootcfg; =20 mips_mt_set_cpuoptions(); =20 @@ -255,40 +257,54 @@ static void __init cps_prepare_cpus(unsigned int max_= cpus) =20 setup_cps_vecs(); =20 - /* Allocate core boot configuration structs */ - ncores =3D mips_cps_numcores(0); - mips_cps_core_bootcfg =3D kcalloc(ncores, sizeof(*mips_cps_core_bootcfg), - GFP_KERNEL); - if (!mips_cps_core_bootcfg) { - pr_err("Failed to allocate boot config for %u cores\n", ncores); - goto err_out; - } + /* Allocate cluster boot configuration structs */ + nclusters =3D mips_cps_numclusters(); + mips_cps_cluster_bootcfg =3D kcalloc(nclusters, + sizeof(*mips_cps_cluster_bootcfg), + GFP_KERNEL); =20 - /* Allocate VPE boot configuration structs */ - for (c =3D 0; c < ncores; c++) { - core_vpes =3D core_vpe_count(0, c); - mips_cps_core_bootcfg[c].vpe_config =3D kcalloc(core_vpes, - sizeof(*mips_cps_core_bootcfg[c].vpe_config), - GFP_KERNEL); - if (!mips_cps_core_bootcfg[c].vpe_config) { - pr_err("Failed to allocate %u VPE boot configs\n", - core_vpes); + for (cl =3D 0; cl < nclusters; cl++) { + /* Allocate core boot configuration structs */ + ncores =3D mips_cps_numcores(cl); + core_bootcfg =3D kcalloc(ncores, sizeof(*core_bootcfg), + GFP_KERNEL); + if (!core_bootcfg) goto err_out; + mips_cps_cluster_bootcfg[cl].core_config =3D core_bootcfg; + + /* Allocate VPE boot configuration structs */ + for (c =3D 0; c < ncores; c++) { + core_vpes =3D core_vpe_count(cl, c); + core_bootcfg[c].vpe_config =3D kcalloc(core_vpes, + sizeof(*core_bootcfg[c].vpe_config), + GFP_KERNEL); + if (!core_bootcfg[c].vpe_config) + goto err_out; } } =20 /* Mark this CPU as booted */ - atomic_set(&mips_cps_core_bootcfg[cpu_core(¤t_cpu_data)].vpe_mask, - 1 << cpu_vpe_id(¤t_cpu_data)); + cl =3D cpu_cluster(¤t_cpu_data); + c =3D cpu_core(¤t_cpu_data); + cluster_bootcfg =3D &mips_cps_cluster_bootcfg[cl]; + core_bootcfg =3D &cluster_bootcfg->core_config[c]; + atomic_set(&core_bootcfg->vpe_mask, 1 << cpu_vpe_id(¤t_cpu_data)); =20 return; err_out: /* Clean up allocations */ - if (mips_cps_core_bootcfg) { - for (c =3D 0; c < ncores; c++) - kfree(mips_cps_core_bootcfg[c].vpe_config); - kfree(mips_cps_core_bootcfg); - mips_cps_core_bootcfg =3D NULL; + if (mips_cps_cluster_bootcfg) { + for (cl =3D 0; cl < nclusters; cl++) { + cluster_bootcfg =3D &mips_cps_cluster_bootcfg[cl]; + ncores =3D mips_cps_numcores(cl); + for (c =3D 0; c < ncores; c++) { + core_bootcfg =3D &cluster_bootcfg->core_config[c]; + kfree(core_bootcfg->vpe_config); + } + kfree(mips_cps_cluster_bootcfg[c].core_config); + } + kfree(mips_cps_cluster_bootcfg); + mips_cps_cluster_bootcfg =3D NULL; } =20 /* Effectively disable SMP by declaring CPUs not present */ @@ -376,17 +392,23 @@ static void boot_core(unsigned int core, unsigned int= vpe_id) =20 static void remote_vpe_boot(void *dummy) { + unsigned int cluster =3D cpu_cluster(¤t_cpu_data); unsigned core =3D cpu_core(¤t_cpu_data); - struct core_boot_config *core_cfg =3D &mips_cps_core_bootcfg[core]; + struct cluster_boot_config *cluster_cfg =3D + &mips_cps_cluster_bootcfg[cluster]; + struct core_boot_config *core_cfg =3D &cluster_cfg->core_config[core]; =20 mips_cps_boot_vpes(core_cfg, cpu_vpe_id(¤t_cpu_data)); } =20 static int cps_boot_secondary(int cpu, struct task_struct *idle) { + unsigned int cluster =3D cpu_cluster(&cpu_data[cpu]); unsigned core =3D cpu_core(&cpu_data[cpu]); unsigned vpe_id =3D cpu_vpe_id(&cpu_data[cpu]); - struct core_boot_config *core_cfg =3D &mips_cps_core_bootcfg[core]; + struct cluster_boot_config *cluster_cfg =3D + &mips_cps_cluster_bootcfg[cluster]; + struct core_boot_config *core_cfg =3D &cluster_cfg->core_config[core]; struct vpe_boot_config *vpe_cfg =3D &core_cfg->vpe_config[vpe_id]; unsigned int remote; int err; @@ -544,12 +566,14 @@ static void cps_kexec_nonboot_cpu(void) static int cps_cpu_disable(void) { unsigned cpu =3D smp_processor_id(); + struct cluster_boot_config *cluster_cfg; struct core_boot_config *core_cfg; =20 if (!cps_pm_support_state(CPS_PM_POWER_GATED)) return -EINVAL; =20 - core_cfg =3D &mips_cps_core_bootcfg[cpu_core(¤t_cpu_data)]; + cluster_cfg =3D &mips_cps_cluster_bootcfg[cpu_cluster(¤t_cpu_data)]; + core_cfg =3D &cluster_cfg->core_config[cpu_core(¤t_cpu_data)]; atomic_sub(1 << cpu_vpe_id(¤t_cpu_data), &core_cfg->vpe_mask); smp_mb__after_atomic(); set_cpu_online(cpu, false); --=20 2.25.1