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charset="utf-8" From: Gregory CLEMENT It is possible to have no CPU cores in a cluster; in such cases, it is not possible to access the GIC, and any indirect access leads to an exception. This patch dynamically skips the indirect access in such situations. Signed-off-by: Gregory CLEMENT Signed-off-by: Aleksandar Rikalo Tested-by: Gregory CLEMENT --- drivers/irqchip/irq-mips-gic.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index f42f69bbd6fb..bca8053864b2 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -141,7 +141,8 @@ static bool gic_irq_lock_cluster(struct irq_data *d) cl =3D cpu_cluster(&cpu_data[cpu]); if (cl =3D=3D cpu_cluster(¤t_cpu_data)) return false; - + if (mips_cps_numcores(cl) =3D=3D 0) + return false; mips_cm_lock_other(cl, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL); return true; } @@ -507,6 +508,9 @@ static void gic_mask_local_irq_all_vpes(struct irq_data= *d) struct gic_all_vpes_chip_data *cd; int intr, cpu; =20 + if (!mips_cps_multicluster_cpus()) + return; + intr =3D GIC_HWIRQ_TO_LOCAL(d->hwirq); cd =3D irq_data_get_irq_chip_data(d); cd->mask =3D false; @@ -520,6 +524,9 @@ static void gic_unmask_local_irq_all_vpes(struct irq_da= ta *d) struct gic_all_vpes_chip_data *cd; int intr, cpu; =20 + if (!mips_cps_multicluster_cpus()) + return; + intr =3D GIC_HWIRQ_TO_LOCAL(d->hwirq); cd =3D irq_data_get_irq_chip_data(d); cd->mask =3D true; @@ -687,8 +694,10 @@ static int gic_irq_domain_map(struct irq_domain *d, un= signed int virq, if (!gic_local_irq_is_routable(intr)) return -EPERM; =20 - for_each_online_cpu_gic(cpu, &gic_lock) - write_gic_vo_map(mips_gic_vx_map_reg(intr), map); + if (mips_cps_multicluster_cpus()) { + for_each_online_cpu_gic(cpu, &gic_lock) + write_gic_vo_map(mips_gic_vx_map_reg(intr), map); + } =20 return 0; } @@ -982,7 +991,7 @@ static int __init gic_of_init(struct device_node *node, change_gic_trig(i, GIC_TRIG_LEVEL); write_gic_rmask(i); } - } else { + } else if (mips_cps_numcores(cl) !=3D 0) { mips_cm_lock_other(cl, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL); for (i =3D 0; i < gic_shared_intrs; i++) { change_gic_redir_pol(i, GIC_POL_ACTIVE_HIGH); @@ -990,6 +999,9 @@ static int __init gic_of_init(struct device_node *node, write_gic_redir_rmask(i); } mips_cm_unlock_other(); + + } else { + pr_warn("No CPU cores on the cluster %d skip it\n", cl); } } =20 --=20 2.25.1