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charset="utf-8" From: Gregory CLEMENT The CM3.5 device used in EyeQ6H SoCs incorrectly reports the status for Hardware Cache Initialization (HCI). This commit adds a property to acknowledge this issue, which enables the use of the second CPU cluster. Signed-off-by: Gregory CLEMENT Signed-off-by: Aleksandar Rikalo Tested-by: Gregory CLEMENT --- arch/mips/boot/dts/mobileye/eyeq6h.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi b/arch/mips/boot/dts/m= obileye/eyeq6h.dtsi index 1db3c3cda2e3..4ea85dfd4eed 100644 --- a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi @@ -18,6 +18,7 @@ cpu@0 { compatible =3D "img,i6500"; reg =3D <0>; clocks =3D <&occ_cpu>; + cm3-l2-config-hci-broken; }; }; =20 --=20 2.25.1