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X-OriginatorOrg: leica-geosystems.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2024 14:59:21.8408 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d754728f-0599-4490-e223-08dcf7611b26 X-MS-Exchange-CrossTenant-Id: 1b16ab3e-b8f6-4fe3-9f3e-2db7fe549f6a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=1b16ab3e-b8f6-4fe3-9f3e-2db7fe549f6a;Ip=[193.8.40.94];Helo=[hexagon.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00025F96.EURPRD83.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU4PR06MB9681 Content-Type: text/plain; charset="utf-8" The ahb reset is deasserted in probe before first register access, while the stmmacheth-ocp reset needs to be asserted every time before changing the phy mode in Arria10[1]. Changed in Upstream to "ahb"(331085a423b arm64: dts: socfpga: change the reset-name of "stmmaceth-ocp" to "ahb" ).This change was intended for arm64 socfpga and it is not applicable to Arria10. Further with STMMAC-SELFTEST Driver enabled, ethtool test also FAILS. $ ethtool -t eth0 [ 322.946709] socfpga-dwmac ff800000.ethernet eth0: entered promiscuous mo= de [ 323.374558] socfpga-dwmac ff800000.ethernet eth0: left promiscuous mode The test result is FAIL The test extra info: 1. MAC Loopback 0 2. PHY Loopback -110 3. MMC Counters -110 4. EEE -95 5. Hash Filter MC 0 6. Perfect Filter UC -110 7. MC Filter -110 8. UC Filter 0 9. Flow Control -110 10. RSS -95 11. VLAN Filtering -95 12. VLAN Filtering (perf) -95 13. Double VLAN Filter -95 14. Double VLAN Filter (perf) -95 15. Flexible RX Parser -95 16. SA Insertion (desc) -95 17. SA Replacement (desc) -95 18. SA Insertion (reg) -95 19. SA Replacement (reg) -95 20. VLAN TX Insertion -95 21. SVLAN TX Insertion -95 22. L3 DA Filtering -95 23. L3 SA Filtering -95 24. L4 DA TCP Filtering -95 25. L4 SA TCP Filtering -95 26. L4 DA UDP Filtering -95 27. L4 SA UDP Filtering -95 28. ARP Offload -95 29. Jumbo Frame -110 30. Multichannel Jumbo -95 31. Split Header -95 32. TBS (ETF Scheduler) -95 [ 324.881327] socfpga-dwmac ff800000.ethernet eth0: Link is Down [ 327.995360] socfpga-dwmac ff800000.ethernet eth0: Link is Up - 1Gbps/Ful= l - flow control rx/tx Link:[1] https://www.intel.com/content/www/us/en/docs/programmable/683711/2= 1-2/functional-description-of-the-emac.html Fixes: 331085a423b ("arm64: dts: socfpga: change the reset-name of "stmmace= th-ocp" to "ahb") Signed-off-by: Mamta Shukla Tested-by: Ahmad Fatoum Reviewed-by: Ahmad Fatoum --- Changes in v2: - Fix subject prefix - Reword commit message. arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/ar= m/boot/dts/intel/socfpga/socfpga_arria10.dtsi index f36063c57c7f..72c55e5187ca 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -440,7 +440,7 @@ gmac0: ethernet@ff800000 { clocks =3D <&l4_mp_clk>, <&peri_emac_ptp_clk>; clock-names =3D "stmmaceth", "ptp_ref"; resets =3D <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; - reset-names =3D "stmmaceth", "ahb"; + reset-names =3D "stmmaceth", "stmmaceth-ocp"; snps,axi-config =3D <&socfpga_axi_setup>; status =3D "disabled"; }; @@ -460,7 +460,7 @@ gmac1: ethernet@ff802000 { clocks =3D <&l4_mp_clk>, <&peri_emac_ptp_clk>; clock-names =3D "stmmaceth", "ptp_ref"; resets =3D <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; - reset-names =3D "stmmaceth", "ahb"; + reset-names =3D "stmmaceth", "stmmaceth-ocp"; snps,axi-config =3D <&socfpga_axi_setup>; status =3D "disabled"; }; @@ -480,7 +480,7 @@ gmac2: ethernet@ff804000 { clocks =3D <&l4_mp_clk>, <&peri_emac_ptp_clk>; clock-names =3D "stmmaceth", "ptp_ref"; resets =3D <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; - reset-names =3D "stmmaceth", "ahb"; + reset-names =3D "stmmaceth", "stmmaceth-ocp"; snps,axi-config =3D <&socfpga_axi_setup>; status =3D "disabled"; }; --=20 2.25.1