From nobody Mon Nov 25 10:44:18 2024 Received: from mail11.truemail.it (mail11.truemail.it [217.194.8.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1940C1DC19F; Mon, 28 Oct 2024 10:54:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.194.8.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730112874; cv=none; b=SHEU1zT7GrN1M1vQMo6+uE9hHSOmG6x1bqzBg2OChoTSoAubUios5wr84z4iO3vKVT6ZMG4HRd/PIZrjQOUXyjJuU7vyhcrcr28SygaPlz7T8zumMfuaOe1AHUGm3nP0o3hfzeRTkikBN6EuMAxxevnuNWFcg9/QftLZO2WI/iI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730112874; c=relaxed/simple; bh=T4AOAHhhAAV6BIM0MHwbxoio5jRcZJ0jwDX3JoS67Tg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BpgBdTDIedCwMML1y/VBnSWmcBVjY/TaDwlgOgrKS6IAN+vUT6lZjH+qs29UKQA9AmZsJydS0umMOK8yhRFK6Eb29uR9NGbuECbUk6+iIVh5OyNuHn10x3+GyJDY0xeno/CCYkXby4vseUzXsV1bPo616PxrdE/wlqKiBWUttBw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dolcini.it; spf=pass smtp.mailfrom=dolcini.it; dkim=pass (2048-bit key) header.d=dolcini.it header.i=@dolcini.it header.b=kGcOko++; arc=none smtp.client-ip=217.194.8.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dolcini.it Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=dolcini.it Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=dolcini.it header.i=@dolcini.it header.b="kGcOko++" Received: from francesco-nb.pivistrello.it (93-49-2-63.ip317.fastwebnet.it [93.49.2.63]) by mail11.truemail.it (Postfix) with ESMTPA id BEFBB1F928; Mon, 28 Oct 2024 11:54:21 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dolcini.it; s=default; t=1730112862; bh=UGWeCLNvpCgUVFKDrNCiEgB3WmbeAvlFwjq74rMtEVM=; h=From:To:Subject; b=kGcOko++DGamSrD7Hb4AQXyWCpXJciW9+cowdcUFG8wK88ndwd9RmOJQ/YwrOJXgZ svfFdpRmAJd9h70GZ+flD77LfGhQi/kaow1fiY3+7LlIkb9ODxdNGvflJtAmrI1OsM PshyKMtBpYty1MdFZ6g4hotifqm0sE1ycftiw/x0qv5twnAdagLpESGpgHfZzAuYwz 3nuOeCtGkqCEM3g2qUr6ZS4sIdgxzX5eeQfZ0EmsBZ8T6SU2ge6Q4Y+t0MFrYhJJL1 Q5avX6HW+k1SwSJFttfYJ/qo9+0vJNOrlDQapX81UTIGfggS8nvBEgPTJgU0rIeky7 auRUC4Hw6fq6w== From: Francesco Dolcini To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathias Nyman , Francesco Dolcini Cc: Parth Pancholi , linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/2] dt-bindings: usb: add TUSB73x0 PCIe Date: Mon, 28 Oct 2024 11:54:12 +0100 Message-Id: <20241028105413.146510-2-francesco@dolcini.it> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241028105413.146510-1-francesco@dolcini.it> References: <20241028105413.146510-1-francesco@dolcini.it> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Parth Pancholi Add device tree bindings for TI's TUSB73x0 PCIe-to-USB 3.0 xHCI host controller. The controller supports software configuration through PCIe registers, such as controlling the PWRONx polarity via the USB control register (E0h). Datasheet: https://www.ti.com/lit/ds/symlink/tusb7320.pdf Signed-off-by: Parth Pancholi Signed-off-by: Francesco Dolcini --- v4: - add $ref: usb-xhci.yaml - description: wrap to 80 columns, add that the two variants use the same device ID - revise the example, based on comment from Rob and taking marvell,prestera.yaml as an example (this binding was reviewed and amended by Rob in the past). v3: use lowercase hex in compatible v2: rename property to ti,tusb7320-pwron-active-high and change type to flag --- .../bindings/usb/ti,tusb73x0-pci.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.y= aml diff --git a/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml b/D= ocumentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml new file mode 100644 index 000000000000..e98a2e0bfcbb --- /dev/null +++ b/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/ti,tusb73x0-pci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TUSB73x0 USB 3.0 xHCI Host Controller (PCIe) + +maintainers: + - Francesco Dolcini + +description: + TUSB73x0 USB 3.0 xHCI Host Controller via PCIe x1 Gen2 interface. + The TUSB7320 supports up to two downstream ports, the TUSB7340 supports = up + to four downstream ports, both variants share the same PCI device ID. + +properties: + compatible: + const: pci104c,8241 + + reg: + maxItems: 1 + + ti,tusb7320-pwron-active-high: + $ref: /schemas/types.yaml#/definitions/flag + description: + Configure the polarity of the PWRONx# signals. When this is present,= the + PWRONx# pins are active high and their internal pull-down resistors = are + disabled. When this is absent, the PWRONx# pins are active low (defa= ult) + and their internal pull-down resistors are enabled. + +required: + - compatible + - reg + +allOf: + - $ref: usb-xhci.yaml + +additionalProperties: false + +examples: + - | + pcie@0 { + reg =3D <0x0 0x1000>; + ranges =3D <0x02000000 0x0 0x100000 0x10000000 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + + usb@0 { + compatible =3D "pci104c,8241"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + ti,tusb7320-pwron-active-high; + }; + }; --=20 2.39.5 From nobody Mon Nov 25 10:44:18 2024 Received: from mail11.truemail.it (mail11.truemail.it [217.194.8.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEBDA1DC1B2; Mon, 28 Oct 2024 10:54:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.194.8.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730112873; cv=none; b=CtvTEtT3W5NB3O5AYwYFbKRFIcf/68i0mYNujPd99foP/37mU1x8U0/fC7JScN3B5pFriNAMri4wdhIE3TF+FjpqrQNwQso2qGwUTkznqT+D6ogJe+gpn/Ciktd9OmlPmOGAVZQKiuIt0klAMhne6ElxdDIUkJQUzfC4FvgmrXI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730112873; c=relaxed/simple; bh=WWM5j4iyr5uf9zwNqp3cN4Hkp2o454JK/QH2zlUNTck=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=c8zr6+8f69Zo2Q+C/3IB6sVxa8ibqzF1A2jO+NqGSvpwx2IPrImD8KWAjHZB6A8etZBDZAgaaMFwp8BlMLVAhtZjvNrMq51wikJifw9gr6Th4udHiNPX+T1QWyUSqKBLaVVcwcsIXpWz4n0bPfmVn0+Bge5V+bMJEC6Gd4Egpuw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dolcini.it; spf=pass smtp.mailfrom=dolcini.it; dkim=pass (2048-bit key) header.d=dolcini.it header.i=@dolcini.it header.b=tUI/dh5U; arc=none smtp.client-ip=217.194.8.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dolcini.it Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=dolcini.it Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=dolcini.it header.i=@dolcini.it header.b="tUI/dh5U" Received: from francesco-nb.pivistrello.it (93-49-2-63.ip317.fastwebnet.it [93.49.2.63]) by mail11.truemail.it (Postfix) with ESMTPA id 621741F935; Mon, 28 Oct 2024 11:54:22 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dolcini.it; s=default; t=1730112862; bh=Lh7fePJXXUmxKfVX2o4rq/UZ/vQBYBldJd5mNKxr/A4=; h=From:To:Subject; b=tUI/dh5UrbTqI2w3m+gLhHOZd859Cft13v5ayaFkLG1GfnG3el/n/axi81YVHqjOy xio154WS2x1vP57HxbpUNcSogGVK7qQrpvmDHG/i8WgNRFdaaqEH//Jeowo9qwa91T YicDv8HBKZE3kexeJ83vknWpgsNZgvYE//XRi87tW2kV2h6RfpWgcYaqyNSLv4rJxx RhI0BlNhGB4tpYDl0sUjF1eESatdAsvXIMZcH5V2L+VAxUEVJ4rgcUd6wleqUTpWCd mRD70dwd2xNHH+udP2WGgiFir9QsJ+r/LsmYLGJlI9fyv55OqVbeFnEO/7RlkOko0i rafToiE6WxLEA== From: Francesco Dolcini To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathias Nyman , Francesco Dolcini Cc: Parth Pancholi , linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/2] USB: xhci: add support for PWRON active high Date: Mon, 28 Oct 2024 11:54:13 +0100 Message-Id: <20241028105413.146510-3-francesco@dolcini.it> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241028105413.146510-1-francesco@dolcini.it> References: <20241028105413.146510-1-francesco@dolcini.it> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Parth Pancholi Some PCIe-to-USB controllers such as TI's TUSB73x0 3.0 xHCI host controller supports controlling the PWRONx polarity via the USB control register (E0h). Add support for device tree property ti,tusb7320-pwron-active-high which indicates PWRONx to be active high and configure the E0h register accordingly. This enables the software control for the TUSB73x0's PWRONx outputs with an inverted polarity from the default configuration which could be used as USB EN signals for the other hubs or devices. Signed-off-by: Parth Pancholi Signed-off-by: Francesco Dolcini --- v4: no changes v3: no changes v2: s/polarity-invert/active-high --- drivers/usb/host/xhci-pci.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index 91dccd25a551..4bdef01735eb 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -641,6 +641,9 @@ int xhci_pci_common_probe(struct pci_dev *dev, const st= ruct pci_device_id *id) =20 dma_set_max_seg_size(&dev->dev, UINT_MAX); =20 + if (device_property_read_bool(&dev->dev, "ti,tusb7320-pwron-active-high")) + pci_clear_and_set_config_dword(dev, 0xE0, 0, 1 << 22); + return 0; =20 put_usb3_hcd: --=20 2.39.5