From nobody Sat Feb 7 16:47:44 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9B7D161320; Mon, 28 Oct 2024 09:40:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730108436; cv=none; b=c8uBqIRO8n1xKLbW3y2I6LVvT7pxhNrqpQ7ZDlBEBNPMVgylm6HqV7SOMWiJ9XZ4MOPjHDebzEYFGCo/n3/HIlFvDaPwZVu8WtrsYDCPEHzXVY4EtxdQpqKaot30ILSGdjA8nGi9eC/Af/NeC87wMjtexxbTbczVfLUIw3SL3QQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730108436; c=relaxed/simple; bh=fOfCtMTTqempwM/M8Zy6RaQ+0MELCkS3ty5RpQLNX8I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UksVwZnq7PJLsk6SCDolaNiSk7pGannRjqw7aEmffTBcpxkhETMOHe2/nbofduoMz4f7R8VztzleTVULAOd5J5eKbHItUHjk9nnYySFbb/LhnZR4pYF3EViVEeqZSl5FrpDjekMmBX78u1g/H3zGoqlhXKvnCj3hCxFkornIzl8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TMWEb3Q3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TMWEb3Q3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AAD72C4CEC3; Mon, 28 Oct 2024 09:40:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730108435; bh=fOfCtMTTqempwM/M8Zy6RaQ+0MELCkS3ty5RpQLNX8I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TMWEb3Q3yr8sCY6ZLd++1Af1iFAAgAf3jSpETEVxbSccuguh6Cym2Gy0O5Ke8gqrC l5hThnrs87kVHIuDBxZmVkSq1poOrkDHM5x5HUXaraiyME1BiLZ2esgzvPO7Y4Ot5e bjGZudSe67agjEV28Y3gCStBWuGGggC97WWT2CcNoUsTBDAWL1FvpPwbas9N+tdNtK w8X2G2eQhWRt7LfDwo4moHlF8IhsecpR/PWczONikDyrTvfKsVbhSaFyFwA8akimW2 rAF62ze9EJPFvPfwyFiRkrpRcBbThL/JNNr5imv6a2GX4RfpPJgaauHUZDlKbVpeoF Ta9UPxKwRrkTQ== From: "Aneesh Kumar K.V (Arm)" To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Cc: Suzuki K Poulose , Steven Price , Will Deacon , Catalin Marinas , Marc Zyngier , Mark Rutland , Oliver Upton , Joey Gouly , Zenghui Yu , "Aneesh Kumar K.V (Arm)" Subject: [PATCH 1/4] arm64: Update the values to binary from hex Date: Mon, 28 Oct 2024 15:10:11 +0530 Message-ID: <20241028094014.2596619-2-aneesh.kumar@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241028094014.2596619-1-aneesh.kumar@kernel.org> References: <20241028094014.2596619-1-aneesh.kumar@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This matches the ARM ARM representation. No functional change in this patch. Signed-off-by: Aneesh Kumar K.V (Arm) --- arch/arm64/include/asm/memory.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memor= y.h index 0480c61dbb4f..ca42f6d87c16 100644 --- a/arch/arm64/include/asm/memory.h +++ b/arch/arm64/include/asm/memory.h @@ -178,17 +178,17 @@ /* * Memory types for Stage-2 translation */ -#define MT_S2_NORMAL 0xf -#define MT_S2_NORMAL_NC 0x5 -#define MT_S2_DEVICE_nGnRE 0x1 +#define MT_S2_NORMAL 0b1111 +#define MT_S2_NORMAL_NC 0b0101 +#define MT_S2_DEVICE_nGnRE 0b0001 =20 /* * Memory types for Stage-2 translation when ID_AA64MMFR2_EL1.FWB is 0001 * Stage-2 enforces Normal-WB and Device-nGnRE */ -#define MT_S2_FWB_NORMAL 6 -#define MT_S2_FWB_NORMAL_NC 5 -#define MT_S2_FWB_DEVICE_nGnRE 1 +#define MT_S2_FWB_NORMAL 0b0110 +#define MT_S2_FWB_NORMAL_NC 0b0101 +#define MT_S2_FWB_DEVICE_nGnRE 0b0001 =20 #ifdef CONFIG_ARM64_4K_PAGES #define IOREMAP_MAX_ORDER (PUD_SHIFT) --=20 2.43.0 From nobody Sat Feb 7 16:47:44 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23A361C3F27; Mon, 28 Oct 2024 09:40:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730108442; cv=none; b=FkS84KdfaP7GzPkhl5CkDWNLEkaS4g3KU8qQ1pewHVw/yEnNzL4+6a60VXPOtUAjUDW3SszewC1zToAjng/3qV9CDNa5UXW6mZy1eKOk3ieQ71DUS2O6pzZ0ZOVypVEWqt0U1YHSLA6tdtwj0aJl9M9eZjN86qKrPVo45GojLVo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730108442; c=relaxed/simple; bh=RL1PZZNf/Qj/0CoaY+xr8w3mCVtSPwhdkys11uyrEvE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qE0z/z183MAtwKdlR4FNKjt+ORdKvUly1kETa0V9U3a8i+HxK6f7UrcyDvsQm6sgE0o+zWgI00TfMoZ1mBGT/nsnKE3RwRlgAMynKuZUzYOSZ7KvdcktCwOpcpNZtIZVMcXgPe+ADhCmTt9Z8LS2z04ths+HTxpSvtW27x9Am0U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HlSAs4nH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HlSAs4nH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7022BC4CEC3; Mon, 28 Oct 2024 09:40:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730108441; bh=RL1PZZNf/Qj/0CoaY+xr8w3mCVtSPwhdkys11uyrEvE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HlSAs4nHSi8Xsp1PizspeIZXy72a6PgV2vUn6GZDzYeFo5s/f3OEKccFiiaEfWYo6 KbLSASzGtqlGRfJWRpeJbqkFUcS25er91XoEvH9eGWzp+wUWoGSM69I/9zz3ZG4yKD XDbv63ZzJhUTGzbyDugx79sYl2qD8AAohXOmhVAPtLIHXk4gnGtT+nYnUpYIi04ks5 NJXKMmA196rgn3y6KQEBsJUwCEgvnjD2YRrYEZKAW84wFeUB7JyIr0kzqXBXEV2yMw +tBdbjz+OHqAaHAqDqyaI1Ml64RYfZH1XH+UkuSCkF8/H/l+evz/FTk8pLSI2pNasd ucGbLvsHnKKoQ== From: "Aneesh Kumar K.V (Arm)" To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Cc: Suzuki K Poulose , Steven Price , Will Deacon , Catalin Marinas , Marc Zyngier , Mark Rutland , Oliver Upton , Joey Gouly , Zenghui Yu , "Aneesh Kumar K.V (Arm)" Subject: [PATCH 2/4] arm64: cpufeature: add Allocation Tag Access Permission (MTE_PERM) feature Date: Mon, 28 Oct 2024 15:10:12 +0530 Message-ID: <20241028094014.2596619-3-aneesh.kumar@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241028094014.2596619-1-aneesh.kumar@kernel.org> References: <20241028094014.2596619-1-aneesh.kumar@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This indicates if the system supports MTE_PERM. This will be used by KVM for stage 2 mapping. This is a CPUCAP_SYSTEM feature because if we enable the feature all cpus must have it. Signed-off-by: Aneesh Kumar K.V (Arm) --- arch/arm64/include/asm/cpufeature.h | 5 +++++ arch/arm64/include/asm/memory.h | 2 ++ arch/arm64/kernel/cpufeature.c | 9 +++++++++ arch/arm64/tools/cpucaps | 1 + 4 files changed, 17 insertions(+) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/c= pufeature.h index 3d261cc123c1..6e6631890021 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -805,6 +805,11 @@ static inline bool system_supports_mte(void) return alternative_has_cap_unlikely(ARM64_MTE); } =20 +static inline bool system_supports_notagaccess(void) +{ + return alternative_has_cap_unlikely(ARM64_MTE_PERM); +} + static inline bool system_has_prio_mask_debugging(void) { return IS_ENABLED(CONFIG_ARM64_DEBUG_PRIORITY_MASKING) && diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memor= y.h index ca42f6d87c16..006a649d4ac7 100644 --- a/arch/arm64/include/asm/memory.h +++ b/arch/arm64/include/asm/memory.h @@ -179,6 +179,7 @@ * Memory types for Stage-2 translation */ #define MT_S2_NORMAL 0b1111 +#define MT_S2_NORMAL_NOTAGACCESS 0b0100 #define MT_S2_NORMAL_NC 0b0101 #define MT_S2_DEVICE_nGnRE 0b0001 =20 @@ -187,6 +188,7 @@ * Stage-2 enforces Normal-WB and Device-nGnRE */ #define MT_S2_FWB_NORMAL 0b0110 +#define MT_S2_FWB_NORMAL_NOTAGACCESS 0b1110 #define MT_S2_FWB_NORMAL_NC 0b0101 #define MT_S2_FWB_DEVICE_nGnRE 0b0001 =20 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 718728a85430..608e24e313ad 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -305,6 +305,7 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = =3D { =20 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] =3D { ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_F= PMR_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1= _MTEPERM_SHIFT, 4, 0), ARM64_FTR_END, }; =20 @@ -2742,6 +2743,14 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .matches =3D has_cpuid_feature, ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) }, + { + .desc =3D "MTE Allocation Tag Access Permission", + .capability =3D ARM64_MTE_PERM, + .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, + .matches =3D has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTEPERM, IMP) + }, + #endif /* CONFIG_ARM64_MTE */ { .desc =3D "RCpc load-acquire (LDAPR)", diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index eedb5acc21ed..81c6599d2a95 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -62,6 +62,7 @@ KVM_PROTECTED_MODE MISMATCHED_CACHE_TYPE MTE MTE_ASYMM +MTE_PERM SME SME_FA64 SME2 --=20 2.43.0 From nobody Sat Feb 7 16:47:44 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56F4F1991C3; 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charset="utf-8" commit d77e59a8fccd ("arm64: mte: Lock a page for MTE tag initialisation") updated the locking such the kernel now allows VM_SHARED mapping with MTE. Update the code comment to reflect this. Signed-off-by: Aneesh Kumar K.V (Arm) --- arch/arm64/kvm/mmu.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index a509b63bd4dd..b5824e93cee0 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1390,11 +1390,8 @@ static int get_vma_page_shift(struct vm_area_struct = *vma, unsigned long hva) * able to see the page's tags and therefore they must be initialised firs= t. If * PG_mte_tagged is set, tags have already been initialised. * - * The race in the test/set of the PG_mte_tagged flag is handled by: - * - preventing VM_SHARED mappings in a memslot with MTE preventing two VMs - * racing to santise the same page - * - mmap_lock protects between a VM faulting a page in and the VMM perfor= ming - * an mprotect() to add VM_MTE + * The race in the test/set of the PG_mte_tagged flag is handled by + * using PG_mte_lock and PG_mte_tagged together. */ static void sanitise_mte_tags(struct kvm *kvm, kvm_pfn_t pfn, unsigned long size) @@ -1646,7 +1643,10 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phy= s_addr_t fault_ipa, } =20 if (!fault_is_perm && !device && kvm_has_mte(kvm)) { - /* Check the VMM hasn't introduced a new disallowed VMA */ + /* + * not a permission fault implies a translation fault which + * means mapping the page for the first time + */ if (mte_allowed) { sanitise_mte_tags(kvm, pfn, vma_pagesize); } else { --=20 2.43.0 From nobody Sat Feb 7 16:47:44 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3F681991C3; Mon, 28 Oct 2024 09:40:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730108452; cv=none; b=fc3jKbDUawasJHQc/FlTroSEDJw2+dPD4exrU27GBeuUMqYCTDJL4xQ981dgRrmPshHxTc7quOm5KGlJSysMQg0UqMsFs6aK2BGjIqTkB9cr+3GzV0uOWzk0cOLToCaPoZjqeQfI+0BWeNI0+b6eGt9BFdv0qpBBIaZPp7p60Qk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730108452; c=relaxed/simple; bh=G2GbVBqUrl/bAsu9wwCmWG5UWW1Trj57AeTzu57FnfQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MuEeO2n73bCxJ1qZZy4UnpyVakHhH+UPZnxYj36Aza+t+NyUXIfUQhoS2NpuIdW8yJwnzOVJiwNyJCpuSQC0qDJ+63hWO1al7xE7HUpRUICrR2wx3EAuDutyz5o4XJhcFlzX8GY3xiM0kv/2yO4yYJL3zvR9WAVWsrJDqD/1zAY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jSS9RfBk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jSS9RfBk" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 864ABC4CEC3; Mon, 28 Oct 2024 09:40:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730108452; bh=G2GbVBqUrl/bAsu9wwCmWG5UWW1Trj57AeTzu57FnfQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jSS9RfBkSCnnPdCu2wVQvHxuuqy4udopoF4zaUlic+tFZf2ZW8eoma6SZoY4+7Agu ILxq83L5EJ6nt/N6TDvo/HYW6ATlKxGP5T5+r3VIlVFXbcTwK7WddFAbcp7ywPAq0a BWY8wK1oamFTPBHzHf+uASLl/5BjsT3Znk5P/T1zT0VkNUoJ2/IohdIYBfiNRxKXLS YAVzh8OSGb9YPZV7XPLkhJa0pnhUa5qkQsXkKi7x6cRfm/bPqVDkz+m2Io+sXYA4eF jzcr8TIBH50Vqz68u90QC+7pxSIEQxwdLgirrXhRV6yo9TpmKqPQ1Pi3Sj0VkPtI2t G2fVt+FoqpdPA== From: "Aneesh Kumar K.V (Arm)" To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Cc: Suzuki K Poulose , Steven Price , Will Deacon , Catalin Marinas , Marc Zyngier , Mark Rutland , Oliver Upton , Joey Gouly , Zenghui Yu , "Aneesh Kumar K.V (Arm)" Subject: [PATCH 4/4] arm64: mte: Use stage-2 NoTagAccess memory attribute if supported Date: Mon, 28 Oct 2024 15:10:14 +0530 Message-ID: <20241028094014.2596619-5-aneesh.kumar@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241028094014.2596619-1-aneesh.kumar@kernel.org> References: <20241028094014.2596619-1-aneesh.kumar@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, the kernel won't start a guest if the MTE feature is enabled and the guest RAM is backed by memory which doesn't support access tags. Update this such that the kernel uses the NoTagAccess memory attribute while mapping pages from VMAs for which MTE is not allowed. The fault from accessing the access tags with such pages is forwarded to VMM so that VMM can decide to kill the guest or remap the pages so that access tag storage is allowed. NOTE: We could also use KVM_EXIT_MEMORY_FAULT for this. I chose to add a new EXIT type because this is arm64 specific exit type. Signed-off-by: Aneesh Kumar K.V (Arm) --- arch/arm64/include/asm/kvm_emulate.h | 5 +++++ arch/arm64/include/asm/kvm_pgtable.h | 1 + arch/arm64/kvm/hyp/pgtable.c | 16 +++++++++++++--- arch/arm64/kvm/mmu.c | 28 ++++++++++++++++++++++------ include/uapi/linux/kvm.h | 7 +++++++ 5 files changed, 48 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/= kvm_emulate.h index a601a9305b10..fa0149a0606a 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -373,6 +373,11 @@ static inline bool kvm_vcpu_trap_is_exec_fault(const s= truct kvm_vcpu *vcpu) return kvm_vcpu_trap_is_iabt(vcpu) && !kvm_vcpu_abt_iss1tw(vcpu); } =20 +static inline bool kvm_vcpu_trap_is_tagaccess(const struct kvm_vcpu *vcpu) +{ + return !!(ESR_ELx_ISS2(kvm_vcpu_get_esr(vcpu)) & ESR_ELx_TagAccess); +} + static __always_inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *v= cpu) { return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC; diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/= kvm_pgtable.h index 03f4c3d7839c..5657ac1998ad 100644 --- a/arch/arm64/include/asm/kvm_pgtable.h +++ b/arch/arm64/include/asm/kvm_pgtable.h @@ -252,6 +252,7 @@ enum kvm_pgtable_prot { =20 KVM_PGTABLE_PROT_DEVICE =3D BIT(3), KVM_PGTABLE_PROT_NORMAL_NC =3D BIT(4), + KVM_PGTABLE_PROT_NORMAL_NOTAGACCESS =3D BIT(5), =20 KVM_PGTABLE_PROT_SW0 =3D BIT(55), KVM_PGTABLE_PROT_SW1 =3D BIT(56), diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c index b11bcebac908..bc0d9f08c49a 100644 --- a/arch/arm64/kvm/hyp/pgtable.c +++ b/arch/arm64/kvm/hyp/pgtable.c @@ -677,9 +677,11 @@ static int stage2_set_prot_attr(struct kvm_pgtable *pg= t, enum kvm_pgtable_prot p { kvm_pte_t attr; u32 sh =3D KVM_PTE_LEAF_ATTR_LO_S2_SH_IS; + unsigned long prot_mask =3D KVM_PGTABLE_PROT_DEVICE | + KVM_PGTABLE_PROT_NORMAL_NC | + KVM_PGTABLE_PROT_NORMAL_NOTAGACCESS; =20 - switch (prot & (KVM_PGTABLE_PROT_DEVICE | - KVM_PGTABLE_PROT_NORMAL_NC)) { + switch (prot & prot_mask) { case KVM_PGTABLE_PROT_DEVICE | KVM_PGTABLE_PROT_NORMAL_NC: return -EINVAL; case KVM_PGTABLE_PROT_DEVICE: @@ -692,6 +694,12 @@ static int stage2_set_prot_attr(struct kvm_pgtable *pg= t, enum kvm_pgtable_prot p return -EINVAL; attr =3D KVM_S2_MEMATTR(pgt, NORMAL_NC); break; + case KVM_PGTABLE_PROT_NORMAL_NOTAGACCESS: + if (system_supports_notagaccess()) + attr =3D KVM_S2_MEMATTR(pgt, NORMAL_NOTAGACCESS); + else + return -EINVAL; + break; default: attr =3D KVM_S2_MEMATTR(pgt, NORMAL); } @@ -872,7 +880,9 @@ static void stage2_unmap_put_pte(const struct kvm_pgtab= le_visit_ctx *ctx, static bool stage2_pte_cacheable(struct kvm_pgtable *pgt, kvm_pte_t pte) { u64 memattr =3D pte & KVM_PTE_LEAF_ATTR_LO_S2_MEMATTR; - return kvm_pte_valid(pte) && memattr =3D=3D KVM_S2_MEMATTR(pgt, NORMAL); + return kvm_pte_valid(pte) && + ((memattr =3D=3D KVM_S2_MEMATTR(pgt, NORMAL)) || + (memattr =3D=3D KVM_S2_MEMATTR(pgt, NORMAL_NOTAGACCESS))); } =20 static bool stage2_pte_executable(kvm_pte_t pte) diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index b5824e93cee0..e56c6996332e 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1647,12 +1647,10 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, ph= ys_addr_t fault_ipa, * not a permission fault implies a translation fault which * means mapping the page for the first time */ - if (mte_allowed) { + if (mte_allowed) sanitise_mte_tags(kvm, pfn, vma_pagesize); - } else { - ret =3D -EFAULT; - goto out_unlock; - } + else + prot |=3D KVM_PGTABLE_PROT_NORMAL_NOTAGACCESS; } =20 if (writable) @@ -1721,6 +1719,15 @@ static void handle_access_fault(struct kvm_vcpu *vcp= u, phys_addr_t fault_ipa) kvm_set_pfn_accessed(kvm_pte_to_pfn(pte)); } =20 +static inline void kvm_prepare_notagaccess_exit(struct kvm_vcpu *vcpu, + gpa_t gpa, gpa_t size) +{ + vcpu->run->exit_reason =3D KVM_EXIT_ARM_NOTAG_ACCESS; + vcpu->run->notag_access.flags =3D 0; + vcpu->run->notag_access.gpa =3D gpa; + vcpu->run->notag_access.size =3D size; +} + /** * kvm_handle_guest_abort - handles all 2nd stage aborts * @vcpu: the VCPU pointer @@ -1833,6 +1840,14 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) =20 gfn =3D ipa >> PAGE_SHIFT; memslot =3D gfn_to_memslot(vcpu->kvm, gfn); + + if (kvm_vcpu_trap_is_tagaccess(vcpu)) { + /* exit to host and handle the error */ + kvm_prepare_notagaccess_exit(vcpu, gfn << PAGE_SHIFT, PAGE_SIZE); + ret =3D 0; + goto out; + } + hva =3D gfn_to_hva_memslot_prot(memslot, gfn, &writable); write_fault =3D kvm_is_write_fault(vcpu); if (kvm_is_error_hva(hva) || (write_fault && !writable)) { @@ -2145,7 +2160,8 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm, if (!vma) break; =20 - if (kvm_has_mte(kvm) && !kvm_vma_mte_allowed(vma)) { + if (kvm_has_mte(kvm) && !system_supports_notagaccess() && + !kvm_vma_mte_allowed(vma)) { ret =3D -EINVAL; break; } diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 637efc055145..a8268a164c4d 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -178,6 +178,7 @@ struct kvm_xen_exit { #define KVM_EXIT_NOTIFY 37 #define KVM_EXIT_LOONGARCH_IOCSR 38 #define KVM_EXIT_MEMORY_FAULT 39 +#define KVM_EXIT_ARM_NOTAG_ACCESS 40 =20 /* For KVM_EXIT_INTERNAL_ERROR */ /* Emulate instruction failed. */ @@ -446,6 +447,12 @@ struct kvm_run { __u64 gpa; __u64 size; } memory_fault; + /* KVM_EXIT_ARM_NOTAG_ACCESS */ + struct { + __u64 flags; + __u64 gpa; + __u64 size; + } notag_access; /* Fix the size of the union. */ char padding[256]; }; --=20 2.43.0