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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2024 05:35:38.0378 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d92c094a-c9ef-4313-bf40-08dcf7125a95 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB53.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9286 Content-Type: text/plain; charset="utf-8" When Secure TSC is enabled and TscInvariant (bit 8) in CPUID_8000_0007_edx is set, the kernel complains with the below firmware bug: [Firmware Bug]: TSC doesn't count with P0 frequency! Secure TSC does not need to run at P0 frequency; the TSC frequency is set by the VMM as part of the SNP_LAUNCH_START command. Skip this check when Secure TSC is enabled Signed-off-by: Nikunj A Dadhania Tested-by: Peter Gonda Reviewed-by: Tom Lendacky --- arch/x86/kernel/cpu/amd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 015971adadfc..4769c10cba04 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -370,7 +370,8 @@ static void bsp_determine_snp(struct cpuinfo_x86 *c) =20 static void bsp_init_amd(struct cpuinfo_x86 *c) { - if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { + if (cpu_has(c, X86_FEATURE_CONSTANT_TSC) && + !cc_platform_has(CC_ATTR_GUEST_SNP_SECURE_TSC)) { =20 if (c->x86 > 0x10 || (c->x86 =3D=3D 0x10 && c->x86_model >=3D 0x2)) { --=20 2.34.1