From nobody Mon Nov 25 13:32:54 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3D3E218EFEB; Mon, 28 Oct 2024 05:35:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730093705; cv=none; b=gKy5k1idNRh7HkxAurZPVm0zpfRocrKQMOMKdUKcSdzXgyvewmLTQBM/Tg2ug4dula2HapJoy6dboHIaOGo0+hXXIFaSN5dk06YsSgWPpIZll8B6W8WN6rFcSs3cm4tZ/b7cSu5auV8fvq7wh10/Y9TjLbn20jD8wICJj0CPZH0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730093705; c=relaxed/simple; bh=PIgxPuVFNmmVzLYAIcp+raLzts/wiHCDE7X/gEKw+2o=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RoaB9Iq644W3UDVMopuCZofHuy//0CosxW8YaarhoKhVDDQvoAEXE37EXoi2x0mmO6Keck+xxfGCDMV131Il6LjqdjE1j9hbOU3dM36y++aYC+x/qr9RSALqLaXl/p19yImBrnh+1ez3kGnfQkAXdKgtgZyTo+V/eDW3+zXIXGA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4F7CA497; Sun, 27 Oct 2024 22:35:32 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.84]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C87843F66E; Sun, 27 Oct 2024 22:34:58 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Anshuman Khandual , Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , Mark Rutland , kvmarm@lists.linux.dev, linux-doc@vger.kernel.org Subject: [PATCH V2 6/7] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9 Date: Mon, 28 Oct 2024 11:04:25 +0530 Message-Id: <20241028053426.2486633-7-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241028053426.2486633-1-anshuman.khandual@arm.com> References: <20241028053426.2486633-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Fine grained trap control for MDSELR_EL1 register needs to be configured in HDFGRTR2_EL2, and HDFGWTR2_EL2 registers when kernel enters at EL1, but EL2 is also present. This adds a new helper __init_el2_fgt2() initializing this new FEAT_FGT2 based fine grained registers. MDCR_EL2.EBWE needs to be enabled for additional (beyond 16) breakpoint and watchpoint exceptions when kernel enters at EL1, but EL2 is also present. This updates __init_el2_debug() as required for FEAT_Debugv8p9. While here, also update booting.rst with MDCR_EL3 and SCR_EL3 requirements. Cc: Catalin Marinas Cc: Will Deacon Cc: Jonathan Corbet Cc: Marc Zyngier Cc: Oliver Upton Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: kvmarm@lists.linux.dev Signed-off-by: Anshuman Khandual --- Changes in V2: - Orr MDCR_EL2_EBWE directly without an intermittent register Documentation/arch/arm64/booting.rst | 19 +++++++++++++++++++ arch/arm64/include/asm/el2_setup.h | 26 ++++++++++++++++++++++++++ arch/arm64/include/asm/kvm_arm.h | 1 + 3 files changed, 46 insertions(+) diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm6= 4/booting.rst index b57776a68f15..e69d972018cf 100644 --- a/Documentation/arch/arm64/booting.rst +++ b/Documentation/arch/arm64/booting.rst @@ -285,6 +285,12 @@ Before jumping into the kernel, the following conditio= ns must be met: =20 - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1. =20 + For CPUs with the Fine Grained Traps (FEAT_FGT2) extension present: + + - If EL3 is present and the kernel is entered at EL2: + + - SCR_EL3.FGTEn2 (bit 59) must be initialised to 0b1. + For CPUs with support for HCRX_EL2 (FEAT_HCX) present: =20 - If EL3 is present and the kernel is entered at EL2: @@ -319,6 +325,19 @@ Before jumping into the kernel, the following conditio= ns must be met: - ZCR_EL2.LEN must be initialised to the same value for all CPUs the kernel will execute on. =20 + For CPUs with FEAT_Debugv8p9 extension present: + + - If the kernel is entered at EL1 and EL2 is present: + + - HDFGRTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1 + - HDFGWTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1 + - MDCR_EL2.EBWE (bit 43) must be initialized to 0b1 + + - If EL3 is present: + + - MDCR_EL3.TDA (bit 9) must be initialized to 0b0 + - MDCR_EL3.EBWE (bit 43) must be initialized to 0b1 + For CPUs with the Scalable Matrix Extension (FEAT_SME): =20 - If EL3 is present: diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el= 2_setup.h index e0ffdf13a18b..289e9d8f8ee6 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -97,6 +97,13 @@ // to own it. =20 .Lskip_trace_\@: + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #ID_AA64DFR0_EL1_DebugVer_SHIFT, #4 + cmp x1, #ID_AA64DFR0_EL1_DebugVer_V8P9 + b.lt .Lskip_dbg_v8p9_\@ + + orr x2, x2, #MDCR_EL2_EBWE +.Lskip_dbg_v8p9_\@: msr mdcr_el2, x2 // Configure debug traps .endm =20 @@ -215,6 +222,24 @@ .Lskip_fgt_\@: .endm =20 +.macro __init_el2_fgt2 + mrs x1, id_aa64mmfr0_el1 + ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4 + cmp x1, #ID_AA64MMFR0_EL1_FGT_FGT2 + b.lt .Lskip_fgt2_\@ + + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #ID_AA64DFR0_EL1_DebugVer_SHIFT, #4 + cmp x1, #ID_AA64DFR0_EL1_DebugVer_V8P9 + b.lt .Lskip_dbg_v8p9_\@ + + mov_q x0, HDFGWTR2_EL2_nMDSELR_EL1 + msr_s SYS_HDFGWTR2_EL2, x0 + msr_s SYS_HDFGRTR2_EL2, x0 +.Lskip_dbg_v8p9_\@: +.Lskip_fgt2_\@: +.endm + .macro __init_el2_nvhe_prepare_eret mov x0, #INIT_PSTATE_EL1 msr spsr_el2, x0 @@ -240,6 +265,7 @@ __init_el2_nvhe_idregs __init_el2_cptr __init_el2_fgt + __init_el2_fgt2 .endm =20 #ifndef __KVM_NVHE_HYPERVISOR__ diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_= arm.h index 109a85ee6910..34936f550118 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -312,6 +312,7 @@ GENMASK(15, 0)) =20 /* Hyp Debug Configuration Register bits */ +#define MDCR_EL2_EBWE (UL(1) << 43) #define MDCR_EL2_E2TB_MASK (UL(0x3)) #define MDCR_EL2_E2TB_SHIFT (UL(24)) #define MDCR_EL2_HPMFZS (UL(1) << 36) --=20 2.25.1