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Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" Subject: [PATCH v5 04/13] x86/msr-index: define AMD heterogeneous CPU related MSR Date: Sun, 27 Oct 2024 21:02:42 -0500 Message-ID: <20241028020251.8085-5-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241028020251.8085-1-mario.limonciello@amd.com> References: <20241028020251.8085-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6F:EE_|CY8PR12MB7337:EE_ X-MS-Office365-Filtering-Correlation-Id: 66a6bdaf-5df8-44c5-f829-08dcf6f4af8f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?/Jxh3DSewsjOMxKl1Y3r9aKsexnFaLfGS1FLTDgF4K/ctF7XExWK4INGE/AK?= =?us-ascii?Q?qRP/5eCZ6sRAtB1ycVkbZZSUguIGX8TGZTsjCaGdVfYdLWd4D90lHiUbhwGt?= =?us-ascii?Q?AA3zw0Vg26jnMGLvkOM8hyR5fEeEmpgN96+UAENKpvYiRiseznA+E5a1dX+c?= =?us-ascii?Q?pn43Xi5melUZGoINVSXj6zH6141wqsRcBoWPLryWmBoY736bfoWU5riGI6lp?= =?us-ascii?Q?yX+UlNenFHXhVqsUMiB6dcqc1LDLjlFaFRvYLGqH93Kd/UUtOoValntG0O6w?= =?us-ascii?Q?pBOqt69Cna0BitMoVk9biVraeJkysL6PKqqKaEUEg/rZ0J7V/NNqYuV1ssTc?= =?us-ascii?Q?f5I4g7f3b+bY1abty/EIZi4uQDWyEWtXEaYxfH+dHbniSC/842X1VjTzP2AE?= =?us-ascii?Q?EaGbfPFm9LZenB0g8+dX1dCeNaimMkyk2sybGEzkbfvBqRegcXGrYKyrOl2e?= =?us-ascii?Q?FC5nb8/wcebNalpHFpi5xKAti433m1QHgueEnx4/tMRx2LW/My7x5fBqSMVa?= =?us-ascii?Q?/YtiV5l+dvI8+Xx5uL2/YqKxiuYltSea0yWICpBhQNGm8zW9MPFeHMd/E47g?= =?us-ascii?Q?tuTJfA6TR7DWVvAaYldFKyn1FRIOqJmGLcS2iLPB4g5vRIIfxwjzlOK9ZkMv?= =?us-ascii?Q?1FJcoTqnrKsnxTSq70TsXI9gL1XWEL6R5Udvr7CBXynFmzm7SEErRDDP3PYx?= =?us-ascii?Q?1/pKAChLzbGhDdFuaOUmqPAKXYrgS5W/415hiISWEeR2w/BKvnnFqvdnCDwe?= =?us-ascii?Q?bFBIMovG9bEiEr62aEMs+S5q3A32gbPXDeOzHFAoiArFfyDllk281SYUO9PZ?= =?us-ascii?Q?Ly8keFhx8uY1MP9HOqqOXoASqqGQSTHcOOzJhZ8RtqCEI2hvJ+VWv5r/NVry?= =?us-ascii?Q?6SPkNxOhDLMAF4tibQxo1JX1ENATl/Xpy/p49Fz46R6s92oQzqLpSChIhWiu?= =?us-ascii?Q?vHQDy3TyrkUNQS4N2ktOMNOX862gLA5o4DNoKWhjwZ6L6CnUkDYGGXJNy+VK?= =?us-ascii?Q?R+wPJH1iUj2juKToFxsh+AG6uf7VVZCk6BsBOSsMiizDOn8awZlNTQpOkUGE?= =?us-ascii?Q?BgDPXCrDVd11itJoeCpLWw+jCFPgBKoklO9RA2rVkzd1oUGa8asFO7vm0I/l?= =?us-ascii?Q?tggiHm+effNETK6R/To+kLBlZcbv0rX7zIlC05Kp0SI/vscLdzYdJpIk+8Ma?= =?us-ascii?Q?CTAkjEjTADu4jhoMfSRwJzRHyQUWftwpXSBk/zVlo7oelD0TGooLdgS4b+FW?= =?us-ascii?Q?DNwx+JBmKkMI5rhmTYRgiS33NRM52UlM9iuUVhnDffN/FM/pMX9LZbgOArCS?= =?us-ascii?Q?3/bVGfi2O26hdL7t+D/AsLuO1gsHv5k8zH+Nxn8aJRusjO4f5dIR9Ak7dl6E?= =?us-ascii?Q?eEp+wOgjWNqgYlsItCAsUemKq4wPYKlB7h7Ff5f9xzheKy4rUw=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2024 02:03:15.6887 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 66a6bdaf-5df8-44c5-f829-08dcf6f4af8f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7337 Content-Type: text/plain; charset="utf-8" From: Perry Yuan Introduces new MSR registers for AMD hardware feedback support. These registers enable the system to provide workload classification and configuration capabilities. Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Signed-off-by: Mario Limonciello --- arch/x86/include/asm/msr-index.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 3ae84c3b8e6db..0cd5ffe50f4a4 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -712,6 +712,11 @@ #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 =20 +/* AMD Hardware Feedback Support MSRs */ +#define AMD_WORKLOAD_CLASS_CONFIG 0xc0000500 +#define AMD_WORKLOAD_CLASS_ID 0xc0000501 +#define AMD_WORKLOAD_HRST 0xc0000502 + /* AMD Last Branch Record MSRs */ #define MSR_AMD64_LBR_SELECT 0xc000010e =20 --=20 2.43.0