From nobody Mon Nov 25 10:35:25 2024 Received: from mail.kernel-space.org (mail.kernel-space.org [195.201.34.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4AC802022EF; Mon, 28 Oct 2024 21:53:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.201.34.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730152425; cv=none; b=L8rJNr30nbMro/LYNf1Lh1ksqPR6cl1VOf8Togss1b3kbG2m7Oi0wSUHN/UYNF0ezZKA0hjtv1bdD3lANLgckFcppHupuonEl3fraBHPbrDI0iSQAsRIyxKEj3mnU/D5/Zdww4RuNiEYPJefU22Ck7giOtvcWVonsSqhN2Y7j6M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730152425; c=relaxed/simple; bh=3FWrgi8PKTkrKv+6SulOkGmEvYhwgAxDIaHcL3HS1+A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EyoHLWhVF7wgEQS4fKdjHD6KV6CXjxcVoqrUTxRg3PnnAZweJPCW5YSuuBNWuTuKlCf9WMgoQ/H4Rph3FjOtdYFhVp1QPLnJ4jWY2KPSzZe8eVXJW9O41cnK7cvQw0nSnhxw7dGClBkgyPTJnuVqE8uJv+F6sHUlUfwNWRpnJX0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=kernel-space.org; spf=pass smtp.mailfrom=kernel-space.org; dkim=pass (1024-bit key) header.d=kernel-space.org header.i=@kernel-space.org header.b=Yr2D1npL; dkim=pass (1024-bit key) header.d=kernel-space.org header.i=@kernel-space.org header.b=h+DFrBSs; arc=none smtp.client-ip=195.201.34.187 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=kernel-space.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=kernel-space.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=kernel-space.org header.i=@kernel-space.org header.b="Yr2D1npL"; dkim=pass (1024-bit key) header.d=kernel-space.org header.i=@kernel-space.org header.b="h+DFrBSs" Received: from kernel-space.org (localhost [127.0.0.1]) by kernel-space.org (OpenSMTPD) with ESMTP id 3d3417e4; Mon, 28 Oct 2024 21:37:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=kernel-space.org; h=from :date:subject:mime-version:content-type :content-transfer-encoding:message-id:references:in-reply-to:to :cc; s=s1; bh=2f19eioHn5TCVlrkVAhSbBuqGw0=; b=Yr2D1npL7oLOVG2HzS edOr6KYyOV1VUo/JR2H/JvCML7wLHVlTjIyhC1hzV43arjIldQv76t/YNsIGKock ouz0iLK2en4xKGovaa5AqUXVl36+ydDAsA8H2iIJmlumRpGzsc97gY9aPU1tD3+T V0yMNwgT/OSS5TADaxYhfHFnU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=kernel-space.org; h=from :date:subject:mime-version:content-type :content-transfer-encoding:message-id:references:in-reply-to:to :cc; q=dns; s=s1; b=atLGKElImxFTxL5UyyNqaqdDEtmOQ1ngtq80V9J3e9oz hVOs00dakjbo77k0Snoj43rtDRxOGlHxHem83UcCNCL5/9+y1ToYVB+hUsM/uKUZ n5A+GR7dvKSVv6wRlSInqrO+/Vhfzn+LtTRP3p5xa++/HBHiJH1rT/+sDeJHDao= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel-space.org; s=s1; t=1730151476; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NDBwndYuwN6MmN3ffoGoo+VdRigpbscMicZRxfEGvVU=; b=h+DFrBSszcWJiR19/JKIOjxnVQMzvC5+sB4zpaqK3F/B1GRd2szUVmV+bWX5ffI8I5+WM1 l7hufATI4WGhclexih0qEIQ1vsDTJkgTDSCT93pp8Z2SXVhVfXTcwz5YGOed0G4Vyj2zxu 6+PTZ4ZiHx3aQz4emasQsRC0bPfdagA= Received: from [127.0.1.1] (host-95-245-34-85.retail.telecomitalia.it [95.245.34.85]) by kernel-space.org (OpenSMTPD) with ESMTPSA id 66c2615d (TLSv1.3:TLS_AES_256_GCM_SHA384:256:NO); Mon, 28 Oct 2024 21:37:56 +0000 (UTC) From: Angelo Dureghello Date: Mon, 28 Oct 2024 22:45:32 +0100 Subject: [PATCH v9 5/8] iio: dac: ad3552r: changes to use FIELD_PREP Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241028-wip-bl-ad3552r-axi-v0-iio-testing-v9-5-f6960b4f9719@kernel-space.org> References: <20241028-wip-bl-ad3552r-axi-v0-iio-testing-v9-0-f6960b4f9719@kernel-space.org> In-Reply-To: <20241028-wip-bl-ad3552r-axi-v0-iio-testing-v9-0-f6960b4f9719@kernel-space.org> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dlechner@baylibre.com, Mark Brown , Angelo Dureghello , Angelo Dureghello X-Mailer: b4 0.14.1 From: Angelo Dureghello Changes to use FIELD_PREP, so that driver-specific ad3552r_field_prep is removed. Variables (arrays) that was used to call ad3552r_field_prep are removed too. Signed-off-by: Angelo Dureghello --- drivers/iio/dac/ad3552r.c | 167 ++++++++++++++----------------------------= ---- 1 file changed, 50 insertions(+), 117 deletions(-) diff --git a/drivers/iio/dac/ad3552r.c b/drivers/iio/dac/ad3552r.c index 7d61b2fe6624..68cc69308a17 100644 --- a/drivers/iio/dac/ad3552r.c +++ b/drivers/iio/dac/ad3552r.c @@ -6,6 +6,7 @@ * Copyright 2021 Analog Devices Inc. */ #include +#include #include #include #include @@ -210,46 +211,6 @@ static const s32 gains_scaling_table[] =3D { [AD3552R_CH_GAIN_SCALING_0_125] =3D 125 }; =20 -enum ad3552r_dev_attributes { - /* - Direct register values */ - /* From 0-3 */ - AD3552R_SDO_DRIVE_STRENGTH, - /* - * 0 -> Internal Vref, vref_io pin floating (default) - * 1 -> Internal Vref, vref_io driven by internal vref - * 2 or 3 -> External Vref - */ - AD3552R_VREF_SELECT, - /* Read registers in ascending order if set. Else descending */ - AD3552R_ADDR_ASCENSION, -}; - -enum ad3552r_ch_attributes { - /* DAC powerdown */ - AD3552R_CH_DAC_POWERDOWN, - /* DAC amplifier powerdown */ - AD3552R_CH_AMPLIFIER_POWERDOWN, - /* Select the output range. Select from enum ad3552r_ch_output_range */ - AD3552R_CH_OUTPUT_RANGE_SEL, - /* - * Over-rider the range selector in order to manually set the output - * voltage range - */ - AD3552R_CH_RANGE_OVERRIDE, - /* Manually set the offset voltage */ - AD3552R_CH_GAIN_OFFSET, - /* Sets the polarity of the offset. */ - AD3552R_CH_GAIN_OFFSET_POLARITY, - /* PDAC gain scaling */ - AD3552R_CH_GAIN_SCALING_P, - /* NDAC gain scaling */ - AD3552R_CH_GAIN_SCALING_N, - /* Rfb value */ - AD3552R_CH_RFB, - /* Channel select. When set allow Input -> DAC and Mask -> DAC */ - AD3552R_CH_SELECT, -}; - struct ad3552r_ch_data { s32 scale_int; s32 scale_dec; @@ -285,45 +246,6 @@ struct ad3552r_desc { unsigned int num_ch; }; =20 -static const u16 addr_mask_map[][2] =3D { - [AD3552R_ADDR_ASCENSION] =3D { - AD3552R_REG_ADDR_INTERFACE_CONFIG_A, - AD3552R_MASK_ADDR_ASCENSION - }, - [AD3552R_SDO_DRIVE_STRENGTH] =3D { - AD3552R_REG_ADDR_INTERFACE_CONFIG_D, - AD3552R_MASK_SDO_DRIVE_STRENGTH - }, - [AD3552R_VREF_SELECT] =3D { - AD3552R_REG_ADDR_SH_REFERENCE_CONFIG, - AD3552R_MASK_REFERENCE_VOLTAGE_SEL - }, -}; - -/* 0 -> reg addr, 1->ch0 mask, 2->ch1 mask */ -static const u16 addr_mask_map_ch[][3] =3D { - [AD3552R_CH_DAC_POWERDOWN] =3D { - AD3552R_REG_ADDR_POWERDOWN_CONFIG, - AD3552R_MASK_CH_DAC_POWERDOWN(0), - AD3552R_MASK_CH_DAC_POWERDOWN(1) - }, - [AD3552R_CH_AMPLIFIER_POWERDOWN] =3D { - AD3552R_REG_ADDR_POWERDOWN_CONFIG, - AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(0), - AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(1) - }, - [AD3552R_CH_OUTPUT_RANGE_SEL] =3D { - AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE, - AD3552R_MASK_CH_OUTPUT_RANGE_SEL(0), - AD3552R_MASK_CH_OUTPUT_RANGE_SEL(1) - }, - [AD3552R_CH_SELECT] =3D { - AD3552R_REG_ADDR_CH_SELECT_16B, - AD3552R_MASK_CH(0), - AD3552R_MASK_CH(1) - } -}; - static u8 _ad3552r_reg_len(u8 addr) { switch (addr) { @@ -399,11 +321,6 @@ static int ad3552r_read_reg(struct ad3552r_desc *dac, = u8 addr, u16 *val) return 0; } =20 -static u16 ad3552r_field_prep(u16 val, u16 mask) -{ - return (val << __ffs(mask)) & mask; -} - /* Update field of a register, shift val if needed */ static int ad3552r_update_reg_field(struct ad3552r_desc *dac, u8 addr, u16= mask, u16 val) @@ -416,21 +333,11 @@ static int ad3552r_update_reg_field(struct ad3552r_de= sc *dac, u8 addr, u16 mask, return ret; =20 reg &=3D ~mask; - reg |=3D ad3552r_field_prep(val, mask); + reg |=3D val; =20 return ad3552r_write_reg(dac, addr, reg); } =20 -static int ad3552r_set_ch_value(struct ad3552r_desc *dac, - enum ad3552r_ch_attributes attr, - u8 ch, - u16 val) -{ - /* Update register related to attributes in chip */ - return ad3552r_update_reg_field(dac, addr_mask_map_ch[attr][0], - addr_mask_map_ch[attr][ch + 1], val); -} - #define AD3552R_CH_DAC(_idx) ((struct iio_chan_spec) { \ .type =3D IIO_VOLTAGE, \ .output =3D true, \ @@ -510,8 +417,14 @@ static int ad3552r_write_raw(struct iio_dev *indio_dev, val); break; case IIO_CHAN_INFO_ENABLE: - err =3D ad3552r_set_ch_value(dac, AD3552R_CH_DAC_POWERDOWN, - chan->channel, !val); + if (chan->channel =3D=3D 0) + val =3D FIELD_PREP(AD3552R_MASK_CH_DAC_POWERDOWN(0), !val); + else + val =3D FIELD_PREP(AD3552R_MASK_CH_DAC_POWERDOWN(1), !val); + + err =3D ad3552r_update_reg_field(dac, AD3552R_REG_ADDR_POWERDOWN_CONFIG, + AD3552R_MASK_CH_DAC_POWERDOWN(chan->channel), + val); break; default: err =3D -EINVAL; @@ -715,9 +628,9 @@ static int ad3552r_reset(struct ad3552r_desc *dac) } =20 return ad3552r_update_reg_field(dac, - addr_mask_map[AD3552R_ADDR_ASCENSION][0], - addr_mask_map[AD3552R_ADDR_ASCENSION][1], - val); + AD3552R_REG_ADDR_INTERFACE_CONFIG_A, + AD3552R_MASK_ADDR_ASCENSION, + FIELD_PREP(AD3552R_MASK_ADDR_ASCENSION, val)); } =20 static void ad3552r_get_custom_range(struct ad3552r_desc *dac, s32 i, s32 = *v_min, @@ -812,20 +725,20 @@ static int ad3552r_configure_custom_gain(struct ad355= 2r_desc *dac, "mandatory custom-output-range-config property missing\n"); =20 dac->ch_data[ch].range_override =3D 1; - reg |=3D ad3552r_field_prep(1, AD3552R_MASK_CH_RANGE_OVERRIDE); + reg |=3D FIELD_PREP(AD3552R_MASK_CH_RANGE_OVERRIDE, 1); =20 err =3D fwnode_property_read_u32(gain_child, "adi,gain-scaling-p", &val); if (err) return dev_err_probe(dev, err, "mandatory adi,gain-scaling-p property missing\n"); - reg |=3D ad3552r_field_prep(val, AD3552R_MASK_CH_GAIN_SCALING_P); + reg |=3D FIELD_PREP(AD3552R_MASK_CH_GAIN_SCALING_P, val); dac->ch_data[ch].p =3D val; =20 err =3D fwnode_property_read_u32(gain_child, "adi,gain-scaling-n", &val); if (err) return dev_err_probe(dev, err, "mandatory adi,gain-scaling-n property missing\n"); - reg |=3D ad3552r_field_prep(val, AD3552R_MASK_CH_GAIN_SCALING_N); + reg |=3D FIELD_PREP(AD3552R_MASK_CH_GAIN_SCALING_N, val); dac->ch_data[ch].n =3D val; =20 err =3D fwnode_property_read_u32(gain_child, "adi,rfb-ohms", &val); @@ -841,9 +754,9 @@ static int ad3552r_configure_custom_gain(struct ad3552r= _desc *dac, dac->ch_data[ch].gain_offset =3D val; =20 offset =3D abs((s32)val); - reg |=3D ad3552r_field_prep((offset >> 8), AD3552R_MASK_CH_OFFSET_BIT_8); + reg |=3D FIELD_PREP(AD3552R_MASK_CH_OFFSET_BIT_8, (offset >> 8)); =20 - reg |=3D ad3552r_field_prep((s32)val < 0, AD3552R_MASK_CH_OFFSET_POLARITY= ); + reg |=3D FIELD_PREP(AD3552R_MASK_CH_OFFSET_POLARITY, (s32)val < 0); addr =3D AD3552R_REG_ADDR_CH_GAIN(ch); err =3D ad3552r_write_reg(dac, addr, offset & AD3552R_MASK_CH_OFFSET_BITS_0_7); @@ -886,9 +799,9 @@ static int ad3552r_configure_device(struct ad3552r_desc= *dac) } =20 err =3D ad3552r_update_reg_field(dac, - addr_mask_map[AD3552R_VREF_SELECT][0], - addr_mask_map[AD3552R_VREF_SELECT][1], - val); + AD3552R_REG_ADDR_SH_REFERENCE_CONFIG, + AD3552R_MASK_REFERENCE_VOLTAGE_SEL, + FIELD_PREP(AD3552R_MASK_REFERENCE_VOLTAGE_SEL, val)); if (err) return err; =20 @@ -900,9 +813,9 @@ static int ad3552r_configure_device(struct ad3552r_desc= *dac) } =20 err =3D ad3552r_update_reg_field(dac, - addr_mask_map[AD3552R_SDO_DRIVE_STRENGTH][0], - addr_mask_map[AD3552R_SDO_DRIVE_STRENGTH][1], - val); + AD3552R_REG_ADDR_INTERFACE_CONFIG_D, + AD3552R_MASK_SDO_DRIVE_STRENGTH, + FIELD_PREP(AD3552R_MASK_SDO_DRIVE_STRENGTH, val)); if (err) return err; } @@ -938,9 +851,15 @@ static int ad3552r_configure_device(struct ad3552r_des= c *dac) "Invalid adi,output-range-microvolt value\n"); =20 val =3D err; - err =3D ad3552r_set_ch_value(dac, - AD3552R_CH_OUTPUT_RANGE_SEL, - ch, val); + if (ch =3D=3D 0) + val =3D FIELD_PREP(AD3552R_MASK_CH_OUTPUT_RANGE_SEL(0), val); + else + val =3D FIELD_PREP(AD3552R_MASK_CH_OUTPUT_RANGE_SEL(1), val); + + err =3D ad3552r_update_reg_field(dac, + AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE, + AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch), + val); if (err) return err; =20 @@ -958,7 +877,14 @@ static int ad3552r_configure_device(struct ad3552r_des= c *dac) ad3552r_calc_gain_and_offset(dac, ch); dac->enabled_ch |=3D BIT(ch); =20 - err =3D ad3552r_set_ch_value(dac, AD3552R_CH_SELECT, ch, 1); + if (ch =3D=3D 0) + val =3D FIELD_PREP(AD3552R_MASK_CH(0), 1); + else + val =3D FIELD_PREP(AD3552R_MASK_CH(1), 1); + + err =3D ad3552r_update_reg_field(dac, + AD3552R_REG_ADDR_CH_SELECT_16B, + AD3552R_MASK_CH(ch), val); if (err < 0) return err; =20 @@ -970,8 +896,15 @@ static int ad3552r_configure_device(struct ad3552r_des= c *dac) /* Disable unused channels */ for_each_clear_bit(ch, &dac->enabled_ch, dac->model_data->num_hw_channels) { - err =3D ad3552r_set_ch_value(dac, AD3552R_CH_AMPLIFIER_POWERDOWN, - ch, 1); + if (ch =3D=3D 0) + val =3D FIELD_PREP(AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(0), 1); + else + val =3D FIELD_PREP(AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(1), 1); + + err =3D ad3552r_update_reg_field(dac, + AD3552R_REG_ADDR_POWERDOWN_CONFIG, + AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(ch), + val); if (err) return err; } --=20 2.45.0.rc1