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Mon, 28 Oct 2024 14:04:29 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49SE4T9O031010 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2024 14:04:29 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 28 Oct 2024 07:04:23 -0700 From: Luo Jie Date: Mon, 28 Oct 2024 22:04:08 +0800 Subject: [PATCH v5 1/4] dt-bindings: clock: qcom: Add CMN PLL clock controller for IPQ SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241028-qcom_ipq_cmnpll-v5-1-339994b0388d@quicinc.com> References: <20241028-qcom_ipq_cmnpll-v5-0-339994b0388d@quicinc.com> In-Reply-To: <20241028-qcom_ipq_cmnpll-v5-0-339994b0388d@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio CC: , , , , , , , , , , , , Luo Jie , Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730124258; l=4608; i=quic_luoj@quicinc.com; s=20240808; h=from:subject:message-id; bh=hjNN+PqFdSkSj/o6TRXfxOXwvZoIzTjelI3Jk9bcBOU=; b=nv2CVdjAZob6/0hbxjeHVyfw6heHAvdO0VNDeIHuGMTjDGA1BBl+ugCesRinF0RbJqaLGH+62 HLAiJQBMoVcAPTV6wMjAqxkgKuwdJhg09YzCHuBTMcoixQQwB0OVP8l X-Developer-Key: i=quic_luoj@quicinc.com; a=ed25519; pk=P81jeEL23FcOkZtXZXeDDiPwIwgAHVZFASJV12w3U6w= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: jbReC1LhQ6al1hN7sMaKsk7Rld3cib72 X-Proofpoint-GUID: jbReC1LhQ6al1hN7sMaKsk7Rld3cib72 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 priorityscore=1501 lowpriorityscore=0 mlxlogscore=999 phishscore=0 malwarescore=0 impostorscore=0 adultscore=0 spamscore=0 suspectscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410280113 The CMN PLL controller provides clocks to networking hardware blocks and to GCC on Qualcomm IPQ9574 SoC. It receives input clock from the on-chip Wi-Fi, and produces output clocks at fixed rates. These output rates are predetermined, and are unrelated to the input clock rate. The primary purpose of CMN PLL is to supply clocks to the networking hardware such as PPE (packet process engine), PCS and the externally connected switch or PHY device. The CMN PLL block also outputs fixed rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ as sleep clock supplied to GCC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Luo Jie --- .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 85 ++++++++++++++++++= ++++ include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 22 ++++++ 2 files changed, 107 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.y= aml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml new file mode 100644 index 000000000000..db8a3ee56067 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm CMN PLL Clock Controller on IPQ SoC + +maintainers: + - Bjorn Andersson + - Luo Jie + +description: + The CMN (or common) PLL clock controller expects a reference + input clock. This reference clock is from the on-board Wi-Fi. + The CMN PLL supplies a number of fixed rate output clocks to + the devices providing networking functions and to GCC. These + networking hardware include PPE (packet process engine), PCS + and the externally connected switch or PHY devices. The CMN + PLL block also outputs fixed rate clocks to GCC. The PLL's + primary function is to enable fixed rate output clocks for + networking hardware functions used with the IPQ SoC. + +properties: + compatible: + enum: + - qcom,ipq9574-cmn-pll + + reg: + maxItems: 1 + + clocks: + items: + - description: The reference clock. The supported clock rates include + 25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ. + - description: The AHB clock + - description: The SYS clock + description: + The reference clock is the source clock of CMN PLL, which is from the + Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL + clock registers. + + clock-names: + items: + - const: ref + - const: ahb + - const: sys + + "#clock-cells": + const: 1 + + assigned-clocks: + maxItems: 1 + + assigned-clock-rates-u64: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - assigned-clocks + - assigned-clock-rates-u64 + +additionalProperties: false + +examples: + - | + #include + #include + + cmn_pll: clock-controller@9b000 { + compatible =3D "qcom,ipq9574-cmn-pll"; + reg =3D <0x0009b000 0x800>; + clocks =3D <&cmn_pll_ref_clk>, + <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>; + clock-names =3D "ref", "ahb", "sys"; + #clock-cells =3D <1>; + assigned-clocks =3D <&cmn_pll CMN_PLL_CLK>; + assigned-clock-rates-u64 =3D /bits/ 64 <12000000000>; + }; +... diff --git a/include/dt-bindings/clock/qcom,ipq-cmn-pll.h b/include/dt-bind= ings/clock/qcom,ipq-cmn-pll.h new file mode 100644 index 000000000000..936e92b3b62c --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H +#define _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H + +/* CMN PLL core clock. */ +#define CMN_PLL_CLK 0 + +/* The output clocks from CMN PLL of IPQ9574. */ +#define XO_24MHZ_CLK 1 +#define SLEEP_32KHZ_CLK 2 +#define PCS_31P25MHZ_CLK 3 +#define NSS_1200MHZ_CLK 4 +#define PPE_353MHZ_CLK 5 +#define ETH0_50MHZ_CLK 6 +#define ETH1_50MHZ_CLK 7 +#define ETH2_50MHZ_CLK 8 +#define ETH_25MHZ_CLK 9 +#endif --=20 2.34.1 From nobody Mon Nov 25 09:23:04 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D82861DDC16; Mon, 28 Oct 2024 14:04:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730124290; cv=none; b=UR5poz8PnU/KIe/9KjbM6295+x+CQh7MA6oJCw4IOYUV0KoOpe2iadk3Q2MCcjcjMZLLoqItuwKS2lYNVeg3lplrT5+g5ydcvZHXkB0+87wTUTIVw1noFu/ghP4CuSCGBopTyl2GzGjLkCzo+sdnhk09JWtyE4enI8CteWDHR6o= ARC-Message-Signature: i=1; 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Mon, 28 Oct 2024 14:04:34 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 28 Oct 2024 07:04:29 -0700 From: Luo Jie Date: Mon, 28 Oct 2024 22:04:09 +0800 Subject: [PATCH v5 2/4] clk: qcom: Add CMN PLL clock controller driver for IPQ SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241028-qcom_ipq_cmnpll-v5-2-339994b0388d@quicinc.com> References: <20241028-qcom_ipq_cmnpll-v5-0-339994b0388d@quicinc.com> In-Reply-To: <20241028-qcom_ipq_cmnpll-v5-0-339994b0388d@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio CC: , , , , , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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The driver is initially supported for IPQ9574 SoC. The CMN PLL clock controller expects a reference input clock from the on-board Wi-Fi block acting as clock source. The input reference clock needs to be configured to one of the supported clock rates. The controller supplies a number of fixed-rate output clocks. For the IPQ9574, there is one output clock of 353 MHZ to PPE (Packet Process Engine) hardware block, three 50 MHZ output clocks and an additional 25 MHZ output clock supplied to the connected Ethernet devices. The PLL also supplies a 24 MHZ clock as XO and a 32 KHZ sleep clock to GCC, and one 31.25 MHZ clock to PCS. Signed-off-by: Luo Jie --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/ipq-cmn-pll.c | 436 +++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 446 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 30eb8236c9d8..73326ddf5ac0 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -190,6 +190,15 @@ config IPQ_APSS_6018 Say Y if you want to support CPU frequency scaling on ipq based devices. =20 +config IPQ_CMN_PLL + tristate "IPQ CMN PLL Clock Controller" + help + Support for CMN PLL clock controller on IPQ platform. The + CMN PLL consumes the AHB/SYS clocks from GCC and supplies + the output clocks to the networking hardware and GCC blocks. + Say Y or M if you want to support CMN PLL clock on the IPQ + based devices. + config IPQ_GCC_4019 tristate "IPQ4019 Global Clock Controller" help diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 2b378667a63f..83d11434714c 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_X1E80100_TCSRCC) +=3D tcsrcc-x1e80100.o obj-$(CONFIG_CLK_QCM2290_GPUCC) +=3D gpucc-qcm2290.o obj-$(CONFIG_IPQ_APSS_PLL) +=3D apss-ipq-pll.o obj-$(CONFIG_IPQ_APSS_6018) +=3D apss-ipq6018.o +obj-$(CONFIG_IPQ_CMN_PLL) +=3D ipq-cmn-pll.o obj-$(CONFIG_IPQ_GCC_4019) +=3D gcc-ipq4019.o obj-$(CONFIG_IPQ_GCC_5018) +=3D gcc-ipq5018.o obj-$(CONFIG_IPQ_GCC_5332) +=3D gcc-ipq5332.o diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c new file mode 100644 index 000000000000..1da8a4a9a8d5 --- /dev/null +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -0,0 +1,436 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/* + * CMN PLL block expects the reference clock from on-board Wi-Fi block, + * and supplies fixed rate clocks as output to the networking hardware + * blocks and to GCC. The networking related blocks include PPE (packet + * process engine), the externally connected PHY or switch devices, and + * the PCS. + * + * On the IPQ9574 SoC, there are three clocks with 50 MHZ and one clock + * with 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switc= h), + * and one clock with 353 MHZ to PPE. The other fixed rate output clocks + * are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS + * with 31.25 MHZ. + * + * +---------+ + * | GCC | + * +--+---+--+ + * AHB CLK| |SYS CLK + * V V + * +-------+---+------+ + * | +-------------> eth0-50mhz + * REF CLK | IPQ9574 | + * -------->+ +-------------> eth1-50mhz + * | CMN PLL block | + * | +-------------> eth2-50mhz + * | | + * +----+----+----+---+-------------> eth-25mhz + * | | | + * V V V + * GCC PCS NSS/PPE + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define CMN_PLL_REFCLK_SRC_SELECTION 0x28 +#define CMN_PLL_REFCLK_SRC_DIV GENMASK(9, 8) + +#define CMN_PLL_LOCKED 0x64 +#define CMN_PLL_CLKS_LOCKED BIT(8) + +#define CMN_PLL_POWER_ON_AND_RESET 0x780 +#define CMN_ANA_EN_SW_RSTN BIT(6) + +#define CMN_PLL_REFCLK_CONFIG 0x784 +#define CMN_PLL_REFCLK_EXTERNAL BIT(9) +#define CMN_PLL_REFCLK_DIV GENMASK(8, 4) +#define CMN_PLL_REFCLK_INDEX GENMASK(3, 0) + +#define CMN_PLL_CTRL 0x78c +#define CMN_PLL_CTRL_LOCK_DETECT_EN BIT(15) + +#define CMN_PLL_DIVIDER_CTRL 0x794 +#define CMN_PLL_DIVIDER_CTRL_FACTOR GENMASK(9, 0) + +/** + * struct cmn_pll_fixed_output_clk - CMN PLL output clocks information + * @id: Clock specifier to be supplied + * @name: Clock name to be registered + * @rate: Clock rate + */ +struct cmn_pll_fixed_output_clk { + unsigned int id; + const char *name; + unsigned long rate; +}; + +/** + * struct clk_cmn_pll - CMN PLL hardware specific data + * @regmap: hardware regmap. + * @hw: handle between common and hardware-specific interfaces + */ +struct clk_cmn_pll { + struct regmap *regmap; + struct clk_hw hw; +}; + +#define CLK_PLL_OUTPUT(_id, _name, _rate) { \ + .id =3D _id, \ + .name =3D _name, \ + .rate =3D _rate, \ +} + +#define to_clk_cmn_pll(_hw) container_of(_hw, struct clk_cmn_pll, hw) + +static const struct regmap_config ipq_cmn_pll_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x7fc, + .fast_io =3D true, +}; + +static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] =3D { + CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL), + CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), + CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), + CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL), + CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL), + CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), + CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), + CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), + CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), +}; + +/* + * CMN PLL has the single parent clock, which supports the several + * possible parent clock rates, each parent clock rate is reflected + * by the specific reference index value in the hardware. + */ +static int ipq_cmn_pll_find_freq_index(unsigned long parent_rate) +{ + int index =3D -EINVAL; + + switch (parent_rate) { + case 25000000: + index =3D 3; + break; + case 31250000: + index =3D 4; + break; + case 40000000: + index =3D 6; + break; + case 48000000: + case 96000000: + /* + * Parent clock rate 48 MHZ and 96 MHZ take the same value + * of reference clock index. 96 MHZ needs the source clock + * divider to be programmed as 2. + */ + index =3D 7; + break; + case 50000000: + index =3D 8; + break; + default: + break; + } + + return index; +} + +static unsigned long clk_cmn_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_cmn_pll *cmn_pll =3D to_clk_cmn_pll(hw); + u32 val, factor; + + /* + * The value of CMN_PLL_DIVIDER_CTRL_FACTOR is automatically adjusted + * by HW according to the parent clock rate. + */ + regmap_read(cmn_pll->regmap, CMN_PLL_DIVIDER_CTRL, &val); + factor =3D FIELD_GET(CMN_PLL_DIVIDER_CTRL_FACTOR, val); + + return parent_rate * 2 * factor; +} + +static int clk_cmn_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + int ret; + + /* Validate the rate of the single parent clock. */ + ret =3D ipq_cmn_pll_find_freq_index(req->best_parent_rate); + + return ret < 0 ? ret : 0; +} + +/* + * This function is used to initialize the CMN PLL to enable the fixed + * rate output clocks. It is expected to be configured once. + */ +static int clk_cmn_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_cmn_pll *cmn_pll =3D to_clk_cmn_pll(hw); + int ret, index; + u32 val; + + /* + * Configure the reference input clock selection as per the given + * parent clock. The output clock rates are always of fixed value. + */ + index =3D ipq_cmn_pll_find_freq_index(parent_rate); + if (index < 0) + return index; + + ret =3D regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, + CMN_PLL_REFCLK_INDEX, + FIELD_PREP(CMN_PLL_REFCLK_INDEX, index)); + if (ret) + return ret; + + /* + * Update the source clock rate selection and source clock + * divider as 2 when the parent clock rate is 96 MHZ. + */ + if (parent_rate =3D=3D 96000000) { + ret =3D regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, + CMN_PLL_REFCLK_DIV, + FIELD_PREP(CMN_PLL_REFCLK_DIV, 2)); + if (ret) + return ret; + + ret =3D regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_SRC_SELECTION, + CMN_PLL_REFCLK_SRC_DIV, + FIELD_PREP(CMN_PLL_REFCLK_SRC_DIV, 0)); + if (ret) + return ret; + } + + /* Enable PLL locked detect. */ + ret =3D regmap_update_bits(cmn_pll->regmap, CMN_PLL_CTRL, + CMN_PLL_CTRL_LOCK_DETECT_EN, + CMN_PLL_CTRL_LOCK_DETECT_EN); + if (ret) + return ret; + + /* + * Reset the CMN PLL block to ensure the updated configurations + * take effect. + */ + ret =3D regmap_update_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, + CMN_ANA_EN_SW_RSTN, 0); + if (ret) + return ret; + + usleep_range(1000, 1200); + ret =3D regmap_update_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, + CMN_ANA_EN_SW_RSTN, CMN_ANA_EN_SW_RSTN); + if (ret) + return ret; + + /* Stability check of CMN PLL output clocks. */ + return regmap_read_poll_timeout(cmn_pll->regmap, CMN_PLL_LOCKED, val, + (val & CMN_PLL_CLKS_LOCKED), + 100, 100 * USEC_PER_MSEC); +} + +static const struct clk_ops clk_cmn_pll_ops =3D { + .recalc_rate =3D clk_cmn_pll_recalc_rate, + .determine_rate =3D clk_cmn_pll_determine_rate, + .set_rate =3D clk_cmn_pll_set_rate, +}; + +static struct clk_hw *ipq_cmn_pll_clk_hw_register(struct platform_device *= pdev) +{ + struct clk_parent_data pdata =3D { .index =3D 0 }; + struct device *dev =3D &pdev->dev; + struct clk_init_data init =3D {}; + struct clk_cmn_pll *cmn_pll; + struct regmap *regmap; + void __iomem *base; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return ERR_CAST(base); + + regmap =3D devm_regmap_init_mmio(dev, base, &ipq_cmn_pll_regmap_config); + if (IS_ERR(regmap)) + return ERR_CAST(regmap); + + cmn_pll =3D devm_kzalloc(dev, sizeof(*cmn_pll), GFP_KERNEL); + if (!cmn_pll) + return ERR_PTR(-ENOMEM); + + init.name =3D "cmn_pll"; + init.parent_data =3D &pdata; + init.num_parents =3D 1; + init.ops =3D &clk_cmn_pll_ops; + + cmn_pll->hw.init =3D &init; + cmn_pll->regmap =3D regmap; + + ret =3D devm_clk_hw_register(dev, &cmn_pll->hw); + if (ret) + return ERR_PTR(ret); + + return &cmn_pll->hw; +} + +static int ipq_cmn_pll_register_clks(struct platform_device *pdev) +{ + const struct cmn_pll_fixed_output_clk *fixed_clk; + struct clk_hw_onecell_data *hw_data; + struct device *dev =3D &pdev->dev; + struct clk_hw *cmn_pll_hw; + unsigned int num_clks; + struct clk_hw *hw; + int ret, i; + + fixed_clk =3D ipq9574_output_clks; + num_clks =3D ARRAY_SIZE(ipq9574_output_clks); + + hw_data =3D devm_kzalloc(dev, struct_size(hw_data, hws, num_clks + 1), + GFP_KERNEL); + if (!hw_data) + return -ENOMEM; + + /* + * Register the CMN PLL clock, which is the parent clock of + * the fixed rate output clocks. + */ + cmn_pll_hw =3D ipq_cmn_pll_clk_hw_register(pdev); + if (IS_ERR(cmn_pll_hw)) + return PTR_ERR(cmn_pll_hw); + + /* Register the fixed rate output clocks. */ + for (i =3D 0; i < num_clks; i++) { + hw =3D clk_hw_register_fixed_rate_parent_hw(dev, fixed_clk[i].name, + cmn_pll_hw, 0, + fixed_clk[i].rate); + if (IS_ERR(hw)) { + ret =3D PTR_ERR(hw); + goto unregister_fixed_clk; + } + + hw_data->hws[fixed_clk[i].id] =3D hw; + } + + /* + * Provide the CMN PLL clock. The clock rate of CMN PLL + * is configured to 12 GHZ by DT property assigned-clock-rates-u64. + */ + hw_data->hws[CMN_PLL_CLK] =3D cmn_pll_hw; + hw_data->num =3D num_clks + 1; + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_data); + if (ret) + goto unregister_fixed_clk; + + platform_set_drvdata(pdev, hw_data); + + return 0; + +unregister_fixed_clk: + while (i > 0) + clk_hw_unregister(hw_data->hws[fixed_clk[--i].id]); + + return ret; +} + +static int ipq_cmn_pll_clk_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + int ret; + + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return ret; + + ret =3D devm_pm_clk_create(dev); + if (ret) + return ret; + + /* + * To access the CMN PLL registers, the GCC AHB & SYSY clocks + * of CMN PLL block need to be enabled. + */ + ret =3D pm_clk_add(dev, "ahb"); + if (ret) + return dev_err_probe(dev, ret, "Fail to add AHB clock\n"); + + ret =3D pm_clk_add(dev, "sys"); + if (ret) + return dev_err_probe(dev, ret, "Fail to add SYS clock\n"); + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + /* Register CMN PLL clock and fixed rate output clocks. */ + ret =3D ipq_cmn_pll_register_clks(pdev); + pm_runtime_put(dev); + if (ret) + return dev_err_probe(dev, ret, + "Fail to register CMN PLL clocks\n"); + + return 0; +} + +static void ipq_cmn_pll_clk_remove(struct platform_device *pdev) +{ + struct clk_hw_onecell_data *hw_data =3D platform_get_drvdata(pdev); + int i; + + /* + * The clock with index CMN_PLL_CLK is unregistered by + * device management. + */ + for (i =3D 0; i < hw_data->num; i++) { + if (i !=3D CMN_PLL_CLK) + clk_hw_unregister(hw_data->hws[i]); + } +} + +static const struct dev_pm_ops ipq_cmn_pll_pm_ops =3D { + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + +static const struct of_device_id ipq_cmn_pll_clk_ids[] =3D { + { .compatible =3D "qcom,ipq9574-cmn-pll", }, + { } +}; +MODULE_DEVICE_TABLE(of, ipq_cmn_pll_clk_ids); + +static struct platform_driver ipq_cmn_pll_clk_driver =3D { + .probe =3D ipq_cmn_pll_clk_probe, + .remove =3D ipq_cmn_pll_clk_remove, + .driver =3D { + .name =3D "ipq_cmn_pll", + .of_match_table =3D ipq_cmn_pll_clk_ids, + .pm =3D &ipq_cmn_pll_pm_ops, + }, +}; +module_platform_driver(ipq_cmn_pll_clk_driver); + +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPQ CMN PLL Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Mon Nov 25 09:23:04 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 969641DDC21; Mon, 28 Oct 2024 14:04:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730124295; cv=none; b=QnTKxsRNXlDV3jyUxNv5ZkSu6GnTQec5tjzdlf7QF2Rt+Q4yPGOQKXJ/y8FzGXA6qyR7EDWQmwrxesBxwMyuuHRESbXLOmEvoe+r5YI3PRo9vfF3kcilZbaBnZWA/rJuPmwtP6srbo2OP2YgHUdSAMZqClT7BrdDndWhmzM3ZGc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730124295; c=relaxed/simple; bh=vG3DMDeDtIAizT7d5yDcrA3ylY/kTZ9djArHmSaKkT0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; 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a=ed25519-sha256; t=1730124258; l=1117; i=quic_luoj@quicinc.com; s=20240808; h=from:subject:message-id; bh=vG3DMDeDtIAizT7d5yDcrA3ylY/kTZ9djArHmSaKkT0=; b=hTGPQesl++00FNlvMJP2FNy6ROsMQiE63w9cf5F77NZlLxqosGsHZDRDkEgRJUaZ1bSWc/QWB 6zHoecMFhXaDZqyRJ/vaUYl2DTL/6/qErQyH6TLl95BBvnYVEH4Uhsc X-Developer-Key: i=quic_luoj@quicinc.com; a=ed25519; pk=P81jeEL23FcOkZtXZXeDDiPwIwgAHVZFASJV12w3U6w= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Db1p4D7wvNtk9cOkThZAX1QmFbCjUxvf X-Proofpoint-GUID: Db1p4D7wvNtk9cOkThZAX1QmFbCjUxvf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 priorityscore=1501 lowpriorityscore=0 mlxlogscore=784 phishscore=0 malwarescore=0 impostorscore=0 adultscore=0 spamscore=0 suspectscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410280113 The CMN PLL hardware block is available in the Qualcomm IPQ SoC such as IPQ9574 and IPQ5332. It provides fixed rate output clocks to Ethernet related hardware blocks such as external Ethernet PHY or switch. This driver is initially being enabled for IPQ9574. All boards based on IPQ9574 SoC will require to include this driver in the build. This CMN PLL hardware block does not provide any other specific function on the IPQ SoC other than enabling output clocks to Ethernet related devices. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Luo Jie --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5fdbfea7a5b2..11aefa9ef7b8 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1308,6 +1308,7 @@ CONFIG_QCOM_CLK_SMD_RPM=3Dy CONFIG_QCOM_CLK_RPMH=3Dy CONFIG_IPQ_APSS_6018=3Dy CONFIG_IPQ_APSS_5018=3Dy +CONFIG_IPQ_CMN_PLL=3Dm CONFIG_IPQ_GCC_5018=3Dy CONFIG_IPQ_GCC_5332=3Dy CONFIG_IPQ_GCC_6018=3Dy --=20 2.34.1 From nobody Mon Nov 25 09:23:04 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FC0D1DDC3F; Mon, 28 Oct 2024 14:04:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Mon, 28 Oct 2024 14:04:45 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49SE4iV3031135 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2024 14:04:44 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 28 Oct 2024 07:04:39 -0700 From: Luo Jie Date: Mon, 28 Oct 2024 22:04:11 +0800 Subject: [PATCH v5 4/4] arm64: dts: qcom: Add CMN PLL node for IPQ9574 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241028-qcom_ipq_cmnpll-v5-4-339994b0388d@quicinc.com> References: <20241028-qcom_ipq_cmnpll-v5-0-339994b0388d@quicinc.com> In-Reply-To: <20241028-qcom_ipq_cmnpll-v5-0-339994b0388d@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio CC: , , , , , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730124258; l=3979; i=quic_luoj@quicinc.com; s=20240808; h=from:subject:message-id; bh=Tg6LNppTIuWtA+krGH0NCUp5FPo/KCQV5VDmFVSFNi4=; b=bmqGUrfXGFR4/akAPgt/Bx6poRlc2COUcwcpaY38jHmGkzpkPtxivM2sCQg8qe7FjKaeEhV1b v6GriMb4KlCC/qsEE6X4uDtnCghIatuJ4YIXSWGFl/O79sqF9Ew7QRf X-Developer-Key: i=quic_luoj@quicinc.com; a=ed25519; pk=P81jeEL23FcOkZtXZXeDDiPwIwgAHVZFASJV12w3U6w= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: JI-Z65EWI7ySiN8V0I4pvT9v2QQ0QyiM X-Proofpoint-GUID: JI-Z65EWI7ySiN8V0I4pvT9v2QQ0QyiM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 clxscore=1015 impostorscore=0 suspectscore=0 spamscore=0 mlxscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410280113 The CMN PLL clock controller allows selection of an input clock rate from a defined set of input clock rates. It in-turn supplies fixed rate output clocks to the hardware blocks that provide the ethernet functions such as PPE (Packet Process Engine) and connected switch or PHY, and to GCC. The reference clock of CMN PLL is routed from XO to the CMN PLL through the internal WiFi block. .XO (48 MHZ or 96 MHZ)-->WiFi (multiplier/divider)-->48 MHZ to CMN PLL. The reference input clock from WiFi to CMN PLL is fully controlled by the bootstrap pins which select the XO frequency (48 MHZ or 96 MHZ). Based on this frequency, the divider in the internal Wi-Fi block is automatically configured by hardware (1 for 48 MHZ, 2 for 96 MHZ), to ensure output clock to CMN PLL is 48 MHZ. Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 16 ++++++++++++++- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 26 ++++++++++++++++++++= +++- 2 files changed, 40 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/= boot/dts/qcom/ipq9574-rdp-common.dtsi index 91e104b0f865..f026c2a9d0c0 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi @@ -3,7 +3,7 @@ * IPQ9574 RDP board common device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights re= served. */ =20 /dts-v1/; @@ -164,6 +164,20 @@ &usb3 { status =3D "okay"; }; =20 +/* + * The bootstrap pins for the board select the XO clock frequency, + * which automatically enables the right dividers to ensure the + * reference clock output to CMNPLL is 48 MHZ. + */ +&cmn_pll_ref_clk { + clock-div =3D <1>; + clock-mult =3D <1>; +}; + &xo_board_clk { clock-frequency =3D <24000000>; }; + +&xo_clk { + clock-frequency =3D <48000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qc= om/ipq9574.dtsi index 14c7b3a78442..ad9cdb1f76db 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -3,10 +3,11 @@ * IPQ9574 SoC device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights re= served. */ =20 #include +#include #include #include #include @@ -19,6 +20,12 @@ / { #size-cells =3D <2>; =20 clocks { + cmn_pll_ref_clk: cmn-pll-ref-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&xo_clk>; + #clock-cells =3D <0>; + }; + sleep_clk: sleep-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -28,6 +35,11 @@ xo_board_clk: xo-board-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; }; + + xo_clk: xo-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; }; =20 cpus { @@ -243,6 +255,18 @@ mdio: mdio@90000 { status =3D "disabled"; }; =20 + cmn_pll: clock-controller@9b000 { + compatible =3D "qcom,ipq9574-cmn-pll"; + reg =3D <0x0009b000 0x800>; + clocks =3D <&cmn_pll_ref_clk>, + <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>; + clock-names =3D "ref", "ahb", "sys"; + #clock-cells =3D <1>; + assigned-clocks =3D <&cmn_pll CMN_PLL_CLK>; + assigned-clock-rates-u64 =3D /bits/ 64 <12000000000>; + }; + qfprom: efuse@a4000 { compatible =3D "qcom,ipq9574-qfprom", "qcom,qfprom"; reg =3D <0x000a4000 0x5a1>; --=20 2.34.1